首页 |元器件品牌

IDT723644L20PFI [IDT]

Bi-Directional FIFO, 1KX36, 12ns, Synchronous, CMOS, PQFP128, TQFP-128;
IDT723644L20PFI
型号： IDT723644L20PFI
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

Bi-Directional FIFO, 1KX36, 12ns, Synchronous, CMOS, PQFP128, TQFP-128

时钟 先进先出芯片 内存集成电路
文件： 总35页 (文件大小：313K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
CMOS SyncBiFIFO WITH BUS-MATCHING  
256 x 36 x 2,  
512 x 36 x 2,  
IDT723624  
IDT723634  
IDT723644  
1,024 x 36 x 2  
• Serial or parallel programming of partial flags  
• Port B bus sizing of 36-bits (long word), 18-bits (word) and  
9-bits (byte)  
• Big- or Little-Endian format for word and byte bus sizes  
• Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
• Mailbox bypass registers for each FIFO  
• Free-running CLKA and CLKB may be asynchronous or coinci-  
dent (simultaneous reading and writing of data on a single clock  
edge is permitted)  
FEATURES:  
• Memory storage capacity:  
IDT723624  
IDT723634  
IDT723644  
–
–
–
256 x 36 x 2  
512 x 36 x 2  
1,024 x 36 x 2  
• Clock frequencies up to 83 MHz (8 ns access time)  
• Two independent clocked FIFOs buffering data in opposite  
directions  
• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRB flag functions)  
• Auto power down minimizes power dissipation  
• Available in space saving 128-pin Thin Quad Flatpack (TQFP)  
• Programmable Almost-Empty and Almost-Full flags; each has  
three default offsets (8, 16 and 64)  
•
Industrial temperature range (–40°C to +85°C) is available  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
Port-A  
Control  
Logic  
CSA  
W/RA  
ENA  
RAM ARRAY  
256 x 36  
36  
36  
MBA  
512 x 36  
1,024 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO1  
FIFO2  
SPM  
FS0/SD  
FS1/SEN  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
A
0-A35  
B0-B35  
10  
EFA/ORA  
Status Flag  
Logic  
FFB/IRB  
AFB  
AEA  
36  
Read  
Write  
Pointer  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
RAM ARRAY  
256 x 36  
36  
36  
512 x 36  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
1,024 x 36  
Port-B  
Control  
Logic  
Mail 2  
Register  
BM  
SIZE  
MBF2  
3270 drw01  
TheSyncBiFIFOisatrademarkandtheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
MARCH 2001  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
1
2001 Integrated Device Technology, Inc.  
DSC-3270/1  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
These devices are a synchronous (clocked) FIFO, meaning each port  
DESCRIPTION:  
employsasynchronousinterface.Alldatatransfersthroughaportaregated  
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor  
each port are independent of one another and can be asynchronous or  
coincident. The enables for each port are arranged to provide a simple  
bidirectional interface between microprocessors and/or buses with syn-  
chronous control.  
The IDT723624/723634/723644 is a monolithic, high-speed, low-  
power, CMOS bidirectional synchronous (clocked) FIFO memory which  
supportsclockfrequenciesupto83MHzandhasreadaccesstimesasfastas  
8ns.Twoindependent256/512/1,024 x 36dual-portSRAMFIFOsonboard  
eachchipbufferdatainoppositedirections.FIFOdataonPortBcanbeinput  
andoutputin36-bit,18-bit,or9-bitformatswithachoiceofBig-orLittle-Endian  
configurations.  
PIN CONFIGURATION  
INDEX  
W/RA  
102  
101  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
CLKB  
PRS2  
1
2
3
4
5
6
7
8
ENA  
CLKA  
GND  
A35  
A34  
A33  
Vcc  
B35  
B34  
B33  
B32  
GND  
GND  
B31  
B30  
B29  
B28  
B27  
B26  
Vcc  
A32  
Vcc  
A31  
A30  
GND  
A29  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
A28  
A27  
A26  
A25  
A24  
A23  
B25  
B24  
BM  
GND  
B23  
B22  
B21  
B20  
B19  
B18  
GND  
B17  
B16  
SIZE  
Vcc  
BE/FWFT  
GND  
A22  
Vcc  
A21  
A20  
A19  
A18  
GND  
A17  
A16  
A15  
B15  
B14  
B13  
B12  
GND  
B11  
B10  
A14  
A13  
Vcc  
A12  
GND  
A11  
A10  
3270 drw02  
TQFP (PK128-1, order code: PF)  
TOP VIEW  
2
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
whetherornottheFIFOmemoryisempty.FFshowswhetherthememoryis  
fullornot.TheIRandORfunctionsareselectedintheFirstWordFallThrough  
mode.IRindicateswhetherornottheFIFOhasavailablememorylocations.  
ORshowswhethertheFIFOhasdataavailableforreadingornot.Itmarksthe  
presenceofvaliddataontheoutputs.  
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and  
aprogrammableAlmost-Fullflag(AFAandAFB). AEAandAEB indicatewhen  
aselectednumberofwordsremainintheFIFOmemory.AFAandAFBindicate  
whenthe FIFOcontains more thana selectednumberofwords.  
FFA/IRA,FFB/IRB,AFAandAFBaretwo-stagesynchronizedtotheport  
clockthatwrites dataintoits array.EFA/ORA,EFB/ORB, AEAandAEBare  
two-stage synchronized to the port clock that reads data from its array.  
ProgrammableoffsetsforAEA,AEB,AFAandAFBareloaded inparallelusing  
PortAorinserialviatheSDinput.TheSerialProgrammingModepin(SPM)  
makesthisselection.Threedefaultoffsetsettingsarealsoprovided.TheAEA  
andAEBthresholdcanbesetat8,16or64locationsfromtheemptyboundary  
andtheAFAandAFBthresholdcanbesetat8,16or64locationsfromthefull  
boundary. All these choices are made using the FS0 and FS1 inputs during  
MasterReset.  
Two or more devices may be used in parallel to create wider data  
paths. If, atanytime, the FIFOis notactivelyperforminga function, the chip  
willautomaticallypowerdown. Duringthepowerdownstate,supplycurrent  
consumption (ICC) is at a minimum. Initiating any operation (by activating  
controlinputs)willimmediatelytake the device outofthe powerdownstate.  
The IDT723624/723634/723644 are characterized for operation from  
0°Cto70°C.Industrial temperaturerange(-40°Cto+85°C)isavailable.They  
arefabricatedusingIDT’shighspeed,submicronCMOStechnology.  
Communication between each port may bypass the FIFOs via two  
mailboxregisters.ThemailboxregisterwidthmatchestheselectedPortBbus  
width.EachMailboxregisterhasaflag(MBF1andMBF2)tosignalwhennew  
mailhasbeenstored.  
TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial  
Reset.MasterResetinitializesthereadandwritepointerstothefirstlocation  
of the memory array, configures the FIFO for Big- or Little-Endian byte  
arrangementandselectsserialflagprogramming,parallelflagprogramming,  
oroneofthreepossibledefaultflagoffsetsettings,8,16or64.Therearetwo  
MasterResetpins,MRS1 andMRS2.  
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe  
memory.UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e.,  
programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset  
is usefulsince itpermits flushingofthe FIFOmemorywithoutchangingany  
configurationsettings.EachFIFOhasitsown,independentPartialResetpin,  
PRS1 and PRS2.  
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,  
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray.A  
read operation is required to access that word (along with all other words  
residing in memory). In the First Word Fall Through mode (FWFT), the first  
long-word(36-bitwide)writtentoanemptyFIFOappearsautomaticallyonthe  
outputs,noreadoperationisrequired(nevertheless,accessingsubsequent  
wordsdoesnecessitateaformalreadrequest).ThestateoftheBE/FWFT pin  
duringFIFOoperationdetermines themodeinuse.  
EachFIFOhasacombinedEmpty/OutputReadyFlag(EFA/ORAand  
EFB/ORB)andacombinedFull/InputReadyFlag(FFA/IRAand FFB/IRB).  
TheEFandFFfunctionsareselectedintheIDTStandardmode.EFindicates  
3
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
PINDESCRIPTIONS  
Symbol  
A0-A35  
AEA  
Name  
I/O  
I/O  
O
Description  
PortAData  
36-bitbidirectionaldataportforsideA.  
PortAAlmost-  
EmptyFlag  
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwordsinFIFO2isless  
thanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.  
AEB  
PortBAlmost-  
EmptyFlag  
O
O
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsinFIFO1isless  
thanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.  
AFA  
PortAAlmost-  
Full Flag  
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofemptylocationsinFIFO1  
islessthanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.  
AFB  
PortBAlmost-  
Full Flag  
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofemptylocationsinFIFO2  
FIFO2is less thanorequaltothevalueintheAlmost-FullBOffsetregister,Y2.  
B0-B35  
PortAData  
I/O  
I
36-bitbidirectionaldataportforsideB.  
BE/FWFT Big-Endian/  
FirstWord  
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this case,  
dependingonthe bus size, the mostsignificantbyte orwordonPortAis readfromPortBfirst (A-to-Bdata  
flow)orwrittentoPortBfirst(B-to-A dataflow).ALOWonBEwillselectLittle-Endianoperation.Inthis case,  
the leastsignificantbyte orwordonPortAis readfromPortBfirst(forA-to-Bdata flow)orwrittentoPortBfirst  
(B-to-Adataflow). AfterMasterReset,this pinselects thetimingmode.AHIGHon FWFTselects IDT  
Standardmode,aLOWselectsFirstWordFallThroughmode.Oncethetimingmodehasbeen  
selected,thelevelonFWFTmustbestaticthroughoutdeviceoperation.  
Fall Through  
Select  
(1)  
BM  
Bus-Match  
Select  
(Port B)  
I
I
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A LOW  
selects longwordoperation. BMworks withSIZEandBEtoselectthe bus size andendianarrangementfor  
PortB.ThelevelofBMmustbestaticthroughoutdeviceoperation.  
CLKA  
CLKB  
PortAClock  
CLKAis a continuous clockthatsynchronizes alldata transfers throughPortAandcanbe asynchronous or  
coincidenttoCLKB.FFA/IRA,EFA/ORA,AFA,andAEAareallsynchronizedtotheLOW-to-HIGHtransitionof  
CLKA.  
PortBClock  
CLKBis a continuous clockthatsynchronizes alldata transfers throughPortBandcanbe asynchronous or  
coincidenttoCLKA.FFB/IRB,EFB/ORB,AFB,andAEBaresynchronizedtotheLOW-to-HIGHtransitionof  
CLKB.  
CSA  
CSB  
Port A Chip  
Select  
I
I
CSAmustbe LOWtoenable toLOW-to-HIGHtransitionofCLKAtoreadorwrite onPortA. The A0-A35  
outputsareinthehigh-impedancestatewhenCSAis HIGH.  
Port B Chip  
Select  
CSBmust be LOW to enable a LOW-to-HIGH transition of CLKB to read or write on Port B. The B0-B35  
outputsareinthehigh-impedancestatewhenCSBis HIGH.  
EFA/ORA PortAEmpty/  
OutputReady  
Flag  
O
This is adualfunctionpin.IntheIDTStandardmode,theEFA functionis selected. EFA indicates whetheror  
nottheFIFO2memoryisempty. IntheFWFTmode,theORAfunctionisselected.ORAindicatesthepresence  
ofvaliddataonA0-A35outputs,availableforreading.EFA/ORAis synchronizedtotheLOW-to-HIGH  
transitionofCLKA.  
EFB/ORB PortBEmpty/  
OutputReady  
Flag  
O
This is adualfunctionpin.IntheIDTStandardmode,theEFB functionis selected. EFB indicates whetheror  
nottheFIFO1memoryisempty.IntheFWFTmode,theORBfunctionisselected.ORBindicatesthepresence  
ofvaliddataontheB0-B35outputs,availableforreading.EFB/ORBissynchronizedtotheLOW-to-HIGHtransition  
ofCLKB.  
ENA  
ENB  
PortAEnable  
PortBEnable  
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.  
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.  
FFA/IRA PortAFull/  
InputRead  
O
This is a dualfunctionpin. Inthe IDTStandardmode, theFFA functionis selected. FFA indicates whetheror  
nottheFIFO1memoryis full.IntheFWFTmode,theIRAfunctionis selected. IRAindicates whetherornot  
thereis spaceavailableforwritingtotheFIFO1memory. FFA/IRAis synchronizedtotheLOW-to-HIGH  
transitionofCLKA.  
Flag  
FFB/IRB  
PortBFull/  
Input Ready  
Flag  
O
This is a dualfunctionpin. Inthe IDTStandardmode, theFFB functionis selected.FFB indicates whetheror  
not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not  
there is space available for writing to the FIFO memory. FFB/IRB is synchronized to the LOW-to-HIGH transition  
of CLKB.  
4
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
PINDESCRIPTIONS(CONTINUED)  
Symbol  
Name  
I/O  
Description  
FS1/SEN FlagOffset  
I
FS1/SENandFS0/SDaredual-purposeinputsusedforflagoffsetregisterprogramming.DuringMasterReset,  
FS1/SEN andFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.Threeoffsetregister  
programmingmethods are available:automaticallyloadone ofthree presetvalues (8, 16, or64), parallelload  
fromPortA, andserialload.  
Select1/  
SerialEnable,  
FS0/SD FlagOffset  
Select0/  
I
Whenserialloadisselectedforflagoffsetregisterprogramming,FS1/SENisusedasanenablesynchronousto  
theLOW-to-HIGHtransitionofCLKA.WhenFS1/SENis LOW,arisingedgeonCLKAloadthebitpresenton  
FS0/SDintothe XandYregisters. The numberofbitwrites requiredtoprogramthe offsetregisters is 32forthe  
723624, 36for the 723634, and40forthe 723644. The first bit write stores the Y1registerMSB and the last bit  
writestorestheX2registerLSB.  
SerialData  
MBA  
MBB  
MBF1  
Port A Mailbox  
Select  
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35  
outputsareactive,aHIGHlevelonMBAselectsdatafromthemail2registerforoutputandaLOWlevelselects  
FIFO2outputregisterdataforoutput.  
PortBMailbox  
Select  
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35  
outputsareactive,aHIGHlevelonMBBselectsdatafromthemail1registerforoutputandaLOWlevelselects  
FIFO1outputregisterdataforoutput.  
Mail1Register  
Flag  
O
MBF1 is setLOWby a LOW-to-HIGH transition of CLKA that writes data tothe mail1register. Writes tothe  
mail1registerare inhibitedwhile MBF1 is LOW. MBF1 is setHIGHbya LOW-to-HIGHtransitionofCLKBwhen  
a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of  
FIFO1.  
MBF2  
MRS1  
Mail2Register  
Flag  
O
I
MBF2 issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.Writestothe  
mail2registerare inhibitedwhile MBF2 is LOW.MBF2 is setHIGHbya LOW-to-HIGHtransitionofCLKAwhena  
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of  
FIFO2.  
FIFO1Master  
Reset  
ALOWonthispininitializestheFIFO1readandwritepointerstothefirstlocationofmemoryandsetsthePortB  
outputregistertoallzeroes.ALOW-to-HIGHtransitiononMRS1selectstheprogrammingmethod(serialorparallel)  
andoneofthreeprogrammableflagdefaultoffsetsforFIFO1andFIFO2.Italso configuresPortBforbussizeand  
endianarrangement. FourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur  
whileMRS1isLOW.  
MRS2  
FIFO2Master  
Reset  
I
ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePortA  
outputregistertoallzeroes.ALOW-to-HIGHtransitiononMRS2toggledsimultaneouslywithMRS1,selectsthe  
programmingmethod(serialorparallel)andoneoftheprogrammableflagdefaultoffsetsforFIFO2.FourLOW-  
to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccurwhile MRS2isLOW.  
PRS1  
PRS2  
SIZE(1)  
FIFO1Partial  
Reset  
I
I
I
ALOWonthispininitializestheFIFO1readandwritepointerstothefirstlocationofmemoryandsetsthePortB  
outputregistertoallzeroes.DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,program  
mingmethod(serialorparallel),andprogrammableflagsettingsareallretained.  
FIFO2Partial  
Reset  
ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsetsthePortA  
outputregistertoallzeroes.DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,program  
mingmethod(serialorparallel),andprogrammableflagsettingsareallretained.  
BusSizeSelect  
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is  
HIGHselects word(18-bit)bus size. SIZEworks withBMandBEtoselectthe bus size andendianarrangement  
forPortB.ThelevelofSIZEmustbestaticthroughoutdeviceoperation.  
(1)  
SPM  
SerialProgram-  
mingMode  
I
I
I
ALOWonthispinselectsserialprogrammingofpartialflagoffsets.AHIGHonthispinselectsparallel  
programmingordefaultoffsets(8,16,or64).  
W/RA  
W/RB  
Port-AWrite/  
ReadSelect  
A HIGHselects a write operationand a LOW selects a readoperationonPortA fora LOW-to- HIGHtransitionof  
CLKA. The A0-A35outputs are inthe HIGHimpedance state whenW/RAis HIGH.  
Port-BWrite/  
ReadSelect  
A LOWselects a write operationanda HIGHselects a readoperationonPortBfora LOW-to-HIGHtransitionof  
CLKB. The B0-B35outputs are inthe HIGHimpedance state whenW/RBis LOW.  
NOTE:  
1. BM, SIZE and SPM are not TTL compatible. These inputs should be tied to GND or VCC.  
5
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
ABSOLUTEMAXIMUMRATINGSOVEROPERATINGFREE-AIRTEMPERATURE  
RANGE (Unless otherwise noted)(1)  
Symbol  
Rating  
Commercial and Industrial  
Unit  
V
VCC  
SupplyVoltageRange  
InputVoltageRange  
OutputVoltageRange  
–0.5 to 7  
–0.5 to VCC+0.5  
–0.5 to VCC+0.5  
±20  
(2)  
VI  
V
(2)  
VO  
V
IIK  
Input Clamp Current (VI < 0 or VI > VCC)  
Output Clamp Current (VO = < 0 or VO > VCC)  
Continuous Output Current (VO = 0 to VCC)  
Continuous Current Through VCC or GND  
StorageTemperatureRange  
mA  
mA  
mA  
mA  
°C  
IOK  
±50  
IOUT  
ICC  
±50  
±400  
TSTG  
–65 to 150  
NOTES:  
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at  
these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods  
may affect device reliability.  
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.  
RECOMMENDEDOPERATINGCONDITIONS  
Symbol  
VCC  
VIH  
Parameter  
Min. Typ. Max. Unit  
SupplyVoltage(Com'l/Ind'l)  
4.5  
2
5.0  
—
—
—
—
—
—
5.5  
—
0.8  
–4  
8
V
V
High-LevelInputVoltage(Com'l/Ind'l)  
Low-LevelInputVoltage(Com'l/Ind'l)  
High-LevelOutputCurrent(Com'l/Ind'l)  
Low-LevelOutputCurrent(Com'l/Ind'l)  
OperatingFree-AirTemperatureCommercial  
OperatingFree-AirTemperatureIndustrial  
VIL  
—
—
—
0
V
IOH  
mA  
mA  
°C  
°C  
IOL  
TA  
70  
85  
TA  
-40  
ELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATING  
FREE-AIRTEMPERATURERANGE(Unlessotherwisenoted)  
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)  
IDT723624  
IDT723634  
IDT723644  
Com'l & Ind'l(1)  
tCLK= 12, 15, 20, 30 ns  
Symbol  
VOH  
VOL  
Parameter  
Test Conditions  
IOH = –4 mA  
IOL = 8 mA  
Min.  
2.4  
—
Typ.(2)  
—
—
—
—
—
—
4
Max.  
Unit  
V
OutputLogic"1"Voltage  
VCC = 4.5V,  
VCC = 4.5V,  
VCC = 5.5V,  
VCC = 5.5V,  
VCC = 5.5V,  
VCC = 5.5V,  
VI = 0,  
—
OutputLogic"0"Voltage  
0.5  
±10  
±10  
8
V
ILI  
InputLeakageCurrent(anyInput)  
OutputLeakageCurrent  
VI = VCC or 0  
VO = VCC or 0  
—
µ A  
µ A  
mA  
mA  
pF  
ILO  
—
(3)  
ICC2  
Standby Current (with CLKA and CLKB running)  
StandbyCurrent(noclocksrunning)  
InputCapacitance  
VI = VCC –0.2 V or 0  
—
(3)  
ICC3  
VI = VCC –0.2 V or 0  
f = 1 MHz  
—
1
4)  
(
CIN  
—
—
(4)  
COUT  
OutputCapacitance  
VO = 0,  
f = 1 MHz  
—
8
—
pF  
NOTES:  
1. Industrial temperature range product for the 20ns speed grade is available as a standard device. All other speed grades are available by special order.  
2. All typical values are at VCC = 5V, TA = 25°C.  
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).  
4. Characterized values, not currently tested.  
6
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION  
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723624/723634/723644 with  
CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data  
outputs were disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number  
of IDT723624/723634/723644 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.  
CALCULATING POWER DISSIPATION  
WithICC(f) takenfromFigure1,themaximumpowerdissipation(PT)oftheseFIFOs maybecalculatedby:  
2
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC X fo)  
where:  
N
∆ICC  
dc  
CL  
fo  
=
=
=
=
=
number of used outputs = 36-bit (long word), 18-bit (word) or 9-bit (byte) bus size  
increase in power supply current for each input at a TTL HIGH level  
duty cycle of inputs at a TTL HIGH level of 3.4 V  
outputcapacitanceload  
switchingfrequencyofanoutput  
300  
250  
f
data = 1/2 fS  
T
A
= 25°C  
C
L
= 0pF  
VCC = 5.5V  
VCC = 5.0V  
200  
150  
100  
VCC = 4.5V  
50  
0
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
3270 drw03  
fS  
Clock Frequency MHz  
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)  
7
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY  
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE  
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)  
Commercial  
Com'l & Ind'l(1) Commercial  
IDT723624L12 IDT723624L15 IDT723624L20 IDT723624L30  
IDT723634L12 IDT723634L15 IDT723634L20 IDT723634L30  
IDT723644L12 IDT723644L15 IDT723644L20 IDT723644L30  
Symbol  
fS  
Parameter  
Clock Frequency, CLKA or CLKB  
Clock Cycle Time, CLKA or CLKB  
Pulse Duration, CLKA or CLKB HIGH  
PulseDuration,CLKAandCLKBLOW  
Min. Max.  
Min.  
—
15  
6
Max.  
66.7  
—
Min.  
—
20  
8
Max.  
50  
Min. Max.  
Unit  
MHz  
ns  
—
12  
5
83  
—
—
—
—
—
30  
10  
10  
6
33.4  
—
tCLK  
tCLKH  
tCLKL  
tDS  
—
—
—
—
ns  
5
6
—
8
—
—
ns  
SetupTime, A0-A35before CLKA↑ andB0-B35  
beforeCLKB↑  
3
4
—
5
—
—
ns  
tENS1  
tENS2  
tRSTS  
tFSS  
SetupTime, CSAandW/RAbefore CLKA↑;CSB  
andW/RBbefore CLKB↑  
4
3
—
—
—
—
4.5  
4.5  
5
—
—
—
—
5
5
—
—
—
—
6
6
—
—
—
—
ns  
ns  
ns  
ns  
SetupTime ENAandMBAbefore CLKA↑;ENB  
andMBBbeforeCLKB↑  
Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW  
beforeCLKA↑ orCLKB↑(2)  
5
6
7
Setup Time, FS0 and FS1 before MRS1 and MRS2  
HIGH  
7.5  
7.5  
8.5  
9.5  
tBES  
SetupTime, BE/FWFT beforeMRS1 and MRS2HIGH 7.5  
—
—
—
—
—
—
7.5  
7.5  
4
—
—
—
—
—
—
8.5  
8.5  
5
—
—
—
—
—
—
9.5  
9.5  
6
—
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
ns  
tSPMS  
tSDS  
tSENS  
tFWS  
tDH  
Setup Time, SPM before MRS1 and MRS2HIGH  
SetupTime,FS0/SDbeforeCLKA↑  
7.5  
3
SetupTime,FS1/SENbeforeCLKA↑  
SetupTime,BE/FWFTbeforeCLKA↑  
3
4
5
6
0
0
0
0
HoldTime,A0-A35afterCLKA↑ andB0-B35after  
CLKB↑  
0.5  
1
1
1
tENH  
tRSTH  
tFSH  
HoldTime, CSA, W/RA, ENA, andMBAafterCLKA↑; 0.5  
CSB,W/RB, ENB, andMBBafterCLKB↑  
—
—
—
1
4
2
—
—
—
1
4
3
—
—
—
1
5
3
—
—
—
ns  
ns  
ns  
Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW  
afterCLKA↑ orCLKB↑(2)  
4
Hold Time, FS0 and FS1 after MRS1 and MRS2  
HIGH  
2
tBEH  
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH  
Hold Time, SPM afterMRS1 and MRS2 HIGH  
HoldTime, FS0/SDafterCLKA↑  
2
2
—
—
—
—
—
2
2
1
1
2
—
—
—
—
—
3
3
1
1
3
—
—
—
—
—
3
3
1
1
3
—
—
—
—
—
ns  
ns  
ns  
ns  
ns  
tSPMH  
tSDH  
0.5  
0.5  
2
tSENH  
tSPH  
HoldTime,FS1/SENHIGHafterCLKA↑  
Hold Time, FS1/SEN HIGH after MRS1 and MRS2  
HIGH  
tSKEW1(3)  
SkewTime betweenCLKA↑ andCLKB↑ for  
EFA/ORA, EFB/ORB, FFA/IRA, and FFB/IRB  
5
—
—
7.5  
12  
—
—
9
—
—
11  
20  
—
—
ns  
ns  
(3,4)  
tSKEW2  
SkewTimebetweenCLKA↑ andCLKB↑ for AEA,  
AEB, AFA, and AFB  
12  
16  
NOTES:  
1. Industrial temperature range is available by special order for speed grades faster than 20ns.  
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.  
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.  
4. Design simulated, not tested.  
8
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY  
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF  
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)  
Commercial  
Com'l & Ind'l(1) Commercial  
IDT723624L12 IDT723624L15 IDT723624L20 IDT723624L30  
IDT723634L12 IDT723634L15 IDT723634L20 IDT723634L30  
IDT723644L12 IDT723644L15 IDT723644L20 IDT723644L30  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max. Unit  
tA  
AccessTime,CLKA↑ toA0-A35andCLKB↑  
toB0-B35  
2
8
2
10  
2
12  
2
15  
12  
12  
12  
12  
12  
ns  
ns  
ns  
ns  
ns  
ns  
tWFF  
tREF  
tPAE  
tPAF  
tPMF  
PropagationDelayTime, CLKA↑ toFFA/IRA  
and CLKB↑ to FFB/IRB  
2
1
1
1
0
8
8
8
8
8
2
1
1
1
0
8
8
8
8
8
2
1
1
1
0
10  
10  
10  
10  
10  
2
1
1
1
0
PropagationDelayTime,CLKA↑ toEFA/ORA  
andCLKB↑ toEFB/ORB  
PropagationDelayTime, CLKA↑ to AEAand  
CLKB↑ toAEB  
PropagationDelayTime,CLKA toAFAand  
CLKB↑ toAFB  
PropagationDelayTime,CLKA↑ toMBF1LOW  
or MBF2 HIGH and CLKB↑ to MBF2 LOW or  
MBF1 HIGH  
tPMR  
tMDV  
tRSF  
PropagationDelayTime,CLKA↑ toB0-B35(2)  
2
2
1
8
8
2
2
1
10  
10  
15  
2
2
1
12  
12  
20  
2
2
1
15  
15  
30  
ns  
ns  
ns  
andCLKB↑ toA0-A35(3)  
Propagation Delay Time, MBA to A0-A35 valid  
and MBB to B0-B35 valid  
Propagation Delay Time,MRS1 or PRS1 LOW  
to AEB LOW, AFA HIGH, and MBF1 HIGH and  
MRS2 or PRS2 LOW to AEALOW, AFB HIGH,  
and MBF2 HIGH  
10  
tEN  
tDIS  
Enable Time, CSAorW/RALOWtoA0-A35  
Active and CSBLOW and W/RB HIGH to  
B0-B35Active  
2
1
6
6
2
1
10  
8
2
1
12  
10  
2
1
14  
11  
ns  
ns  
Disable Time, CSA or W/RA HIGH to A0-A35  
at high impedance and CSB HIGH or W/RB  
LOWtoB0-B35atHIGHimpedance  
NOTES:  
1. Industrial temperature range is available by special order for speed grades faster than 20ns.  
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.  
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.  
9
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)  
— ENDIAN SELECTION  
SIGNALDESCRIPTION  
MASTER RESET (MRS1, MRS2)  
Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction  
isactive,permittingachoiceofBigorLittle-Endianbytearrangementfordata  
writtentoorreadfromPortB. This selectiondetermines the orderbywhich  
bytes (or words) of data are transferred through this port. For the following  
illustrations,assumethatabyte(orword)bussizehasbeenselectedforPort  
B. (Note thatwhenPortBis configuredfora longwordsize, the Big-Endian  
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding  
aLOWpulsetoMRS1andMRS2simultaneously. Afterwards,eachofthetwo  
FIFO memories of the IDT723624/723634/723644 undergoes a complete  
resetbytakingitsassociatedMasterReset(MRS1,MRS2)inputLOWforat  
leastfourPortAClock(CLKA)andfourPortBClock(CLKB)LOW-to-HIGH  
transitions.TheMasterResetinputscanswitchasynchronouslytotheclocks.  
AMasterResetinitializes the associatedreadandwrite pointers tothe first  
locationofthememoryandforcestheFull/InputReadyflag(FFA/IRA,FFB/  
IRB)LOW, the Empty/OutputReadyflag(EFA/ORA, EFB/ORB)LOW, the  
Almost-Emptyflag(AEA,AEB)LOW,andforces theAlmost-Fullflag(AFA,  
AFB)HIGH.AMasterResetalsoforces the MailboxFlag(MBF1,MBF2)of  
theparallelmailboxregisterHIGH.AfteraMasterReset,theFIFO’sFull/Input  
Ready flag is set HIGH after two write clock cycles. Then the FIFO is ready  
tobewrittento.  
ALOW-to-HIGHtransitiononaFlFO1MasterReset(MRS1)inputlatches  
thevalueoftheBig-Endian(BE)inputfordeterminingtheorderbywhichbytes  
aretransferredthroughPortB.Italsolatchesthevaluesof theFlagSelect(FS0,  
FS1)andSerialProgrammingMode(SPM)inputsforchoosingtheAlmost-  
FullandAlmost-Emptyoffsetprogrammingmethod.  
ALOW-to-HIGHtransitionona FlFO2MasterReset(MRS2)clears the  
FlagOffsetregistersofFIFO2(X2,Y2).ALOW-to-HIGHtransitionoftheFIFO2  
MasterReset(MRS2)togetherwiththe FIFO1MasterReset(MRS1)input  
latchesthevalueoftheBig-Endian(BE)inputforthePortBandalsolatches  
thevaluesof theFlagSelect(FS0,FS1)andSerialProgrammingMode(SPM)  
inputs forchoosingthe Almost-FullandAlmost-Emptyoffsetprogramming  
method (for details see Table 1, Flag Programming, and the Programming  
oftheAlmost-EmptyandAlmost-Fullflagssection).TherelevantFIFOMaster  
Resettimingdiagramcanbe foundinFigure 3.  
1
functionhas noapplicationandthe BEinputis a “don’tcare” .)  
A HIGH on the BE/FWFT input when the Master Reset (MRS1 , MRS2)  
inputsgofromLOWtoHIGHwillselectaBig-Endianarrangement.Whendata  
ismovinginthedirectionfromPortAtoPortB,themostsignificantbyte(word)  
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant  
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When  
dataismovinginthedirectionfromPortBtoPortA,thebyte(word)writtento  
PortBfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong  
word;thebyte(word)writtentoPortBlastwillbereadfromPortAastheleast  
significantbyte (word)ofthe longword.  
A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2)  
inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata  
ismovinginthedirectionfromPortAtoPortB,theleastsignificantbyte(word)  
ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant  
byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When  
dataismovinginthedirectionfromPortBtoPortA,thebyte(word)writtento  
PortBfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong  
word;thebyte(word)writtentoPortBlastwillbereadfromPortAasthemost  
significantbyte(word)ofthelongword.RefertoFigure2foranillustrationof  
the BE function. See Figure 3 (Master Reset) for the Endian select timing  
diagram.  
— TIMING MODE SELECTION  
AfterMasterReset,theFWFTselectfunctionisactive,permittingachoice  
betweentwopossible timingmodes:IDTStandardmode orFirstWordFall  
Through(FWFT)mode.OncetheMasterReset(MRS1,MRS2)inputisHIGH,  
aHIGHontheBE/FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA  
(forFIFO1)andCLKB(forFIFO2)willselectIDTStandardmode.Thismode  
usestheEmptyFlagfunction(EFA,EFB)toindicatewhetherornotthereare  
anywords presentinthe FIFOmemory. Ituses the FullFlagfunction(FFA,  
FFB)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.  
InIDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must  
berequestedusingaformalreadoperation.RefertoFigure3(MasterReset)  
foraFirstWordFallThroughselecttimingdiagram.  
OncetheMasterReset(MRS1,MRS2)inputisHIGH,aLOWontheBE/  
FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and  
CLKB(forFIFO2)willselectFWFTmode.ThismodeusestheOutputReady  
function(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedata  
outputs(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)  
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.In  
theFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata  
outputs,noreadrequestnecessary.Subsequentwordsmustbeaccessedby  
PARTIAL RESET (PRS1, PRS2)  
EachofthetwoFIFOmemoriesofthesedevicesundergoesalimitedreset  
bytakingitsassociatedPartialReset(PRS1,PRS2)inputLOWforatleastfour  
PortAClock(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions.  
The PartialResetinputs canswitchasynchronouslytothe clocks. APartial  
ResetinitializestheinternalreadandwritepointersandforcestheFull/Input  
Readyflag(FFA/IRA,FFB/IRB)LOW, the Empty/OutputReadyflag(EFA/  
ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the  
Almost-Fullflag(AFA,AFB)HIGH.APartialResetalsoforcestheMailboxFlag  
(MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,the  
FIFO’sFull/InputReadyflagissetHIGHaftertwowriteclockcycles.Thenthe  
FIFO is ready to be written to.  
Whateverflagoffsets,programmingmethod(parallelorserial),andtiming  
mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial  
Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof  
the reset operation. A Partial Reset may be useful in the case where  
reprogrammingaFIFOfollowingaMasterResetwouldbeinconvenient.See  
Figure4forthePartialResettimingdiagram.  
NOTE:  
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with  
unused inputs) must not be left open, rather they must be either HIGH or LOW.  
10  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
performingaformalreadoperation.RefertoFigure3(MasterReset)foraFirst the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723624,  
WordFallThroughselecttimingdiagram. IDT723634,orIDT723644,respectively.Thehighestnumberedinputisused  
FollowingMasterReset,thelevelappliedtotheBE/FWFTinputtochoose asthemostsignificantbitofthebinarynumberineachcase.Validprogramming  
thedesiredtimingmodemustremainstaticthroughoutFIFOoperation.  
valuesfortheregistersrangefrom1to252fortheIDT723624;1to508forthe  
IDT723634;and1to1,020fortheIDT723644.Afteralltheoffsetregistersare  
programmed from Port A, the Port B Full/Input Ready flag (FFB/IRB) is set  
PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS  
FourregistersintheIDT723624/723634/723644areusedtoholdtheoffset HIGH,andbothFIFOsbeginnormaloperation.RefertoFigure5foratiming  
valuesfortheAlmost-EmptyandAlmost-Fullflags.ThePortBAlmost-Empty diagramillustrationofparallelprogrammingoftheflagoffsetvalues.  
flag(AEB)OffsetregisterislabeledX1andthePortAAlmost-Emptyflag(AEA)  
OffsetregisterislabeledX2.ThePortAAlmost-Fullflag(AFA)Offsetregister — SERIAL LOAD  
islabeledY1andthePortBAlmost-Fullflag(AFB)OffsetregisterislabeledY2.  
ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset  
TheindexofeachregisternamecorrespondstoitsFIFOnumber.Theoffset withSPMLOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGH  
registers can be loaded with preset values during the reset of a FIFO, transitionofMRS1andMRS2.Afterthisresetiscomplete,theXandYregister  
programmedinparallelusingtheFIFO’sPortAdatainputs,orprogrammed valuesareloadedbit-wisethroughtheFS0/SDinputoneachLOW-to-HIGH  
in serial using the Serial Data (SD) input (see Table 1).  
SPM,FS0/SDandFS1/SENfunctionthesamewayinbothIDTStandard bitwritesneededtocompletetheprogrammingfortheIDT723624,IDT723634,  
andFWFTmodes.  
transitionofCLKAthattheFS1/SENinputisLOW.Thereare32-,36-,or40-  
orIDT723644,respectively.ThefourregistersarewrittenintheorderY1,X1,  
Y2,andfinally,X2. Thefirst-bitwritestores themostsignificantbitoftheY1  
registerandthelast-bitwritestorestheleastsignificantbitoftheX2register.Each  
— PRESET VALUES  
ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith register value can be programmed from 1 to 508 (IDT723624), 1 to 1,020  
oneofthethreepresetvalueslistedinTable1,theSerialProgramMode(SPM) (IDT723634), or 1 to 2,044 (IDT723644).  
andatleastoneoftheflag-selectinputsmustbeHIGHduringtheLOW-to-HIGH  
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,thePort  
transitionofitsMasterResetinput(MRS1,MRS2).Forexample,toloadthe AFull/InputReady(FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.  
preset value of 64 into X1 and Y1, SPM, FS0 and FS1 must be HIGH when FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit  
FlFO1reset(MRS1)returnsHIGH.Flag-offsetregistersassociatedwithFIFO2 isloadedtoallownormalFIFO1operation.ThePortBFull/InputReady(FFB/  
areloadedwithoneofthepresetvaluesinthesamewaywithFIFO2Master IRB)flagalsoremainsLOWthroughouttheserialprogrammingprocess,until  
Reset(MRS2),toggledsimultaneouslywithFIFO1MasterReset(MRS1).For allregisterbitsarewritten.FFB/IRBissetHIGHbytheLOW-to-HIGHtransition  
relevantpresetvalue loadingtimingdiagram, see Figure 3.  
ofCLKBafterthelastbitis loadedtoallownormalFIFO2operation.  
SeeFigure6forSerialProgrammingoftheAlmost-FullFlagandAlmost-  
Empty Flag Offset Values (IDT Standard and FWFT Modes).  
— PARALLEL LOAD FROM PORT A  
ToprogramtheX1,X2,Y1,andY2registersfromPortA,performaMaster  
ResetonbothFlFOssimultaneouslywithSPMHIGHandFS0andFS1LOW FIFO WRITE/READ OPERATION  
during the LOW-to-HIGH transition of MRS1 and MRS2. After this reset is  
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect  
complete,thefirstfourwritestoFIFO1donotstoredataintheRAMbutload (CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh-  
theoffsetregistersintheorderY1,X1,Y2,X2.ThePortAdatainputsusedby  
TABLE 1 — FLAG PROGRAMMING  
SPM  
FS1/SEN  
FS0/SD  
MRS1  
MRS2  
X1 AND Y1 REGlSTERS(1)  
X2 AND Y2 REGlSTERS(2)  
H
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
↑
64  
X
H
64  
64  
H
X
↑
16  
X
H
16  
16  
H
X
↑
8
X
H
8
ParallelprogrammingviaPortA  
SerialprogrammingviaSD  
Reserved  
8
ParallelprogrammingviaPortA  
SerialprogrammingviaSD  
Reserved  
H
↑
L
↑
L
L
↑
↑
Reserved  
Reserved  
L
↑
Reserved  
Reserved  
NOTES:  
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.  
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.  
11  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay  
active outputs whenbothCSA andW/RAare LOW.  
changestates duringthesetupandholdtimewindowofthecycle.  
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,  
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH  
transitionofCLKAwhenCSA isLOW,W/RAisHIGH,ENAisHIGH,MBAis thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe  
LOW,andFFA/IRAisHIGH.DataisreadfromFIFO2totheA0-A35outputs LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.  
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput  
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand registersonlywhenareadisselectedusingtheport’sChipSelect,Write/Read  
writes on Port A are independent of any concurrent Port B operation.  
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception  
select,Enable,andMailboxselect.  
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause  
thatthePortBWrite/Readselect(W/RB)istheinverseofthePortAWrite/Read theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe  
select(W/RA).ThestateofthePortBdata(B0-B35)linesiscontrolledbythe Readclock.Thedatawordwillnotbeautomaticallysenttotheoutputregister.  
PortBChipSelect(CSB)andPortBWrite/Readselect(W/RB).TheB0-B35 Instead, data residing in the FIFO’s memory array is clocked to the output  
lines are in the high-impedance state when eitherCSB is HIGH or W/RB is registeronlywhenareadisselectedusingtheport’sChipSelect,Write/Read  
LOW. The B0-B35 lines are active outputs when CSB is LOW andW/RBis select,Enable,andMailboxselect.WriteandReadtimingdiagramsforPort  
HIGH.  
AcanbefoundinFigure7and14.RelevantPortBWriteandReadcycletiming  
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH diagrams togetherwithBus-MatchingandEndianselectoperations canbe  
transitionofCLKBwhenCSB is LOW,W/RBis LOW,ENBis HIGH,MBBis found in Figures 8 through 13.  
LOW,andFFB/IRBisHIGH.DataisreadfromFIFO1totheB0-B35outputs  
SYNCHRONIZED FIFO FLAGS  
byaLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENB  
isHIGH,MBBisLOW,andEFB/ORBisHIGH(seeTable3).FIFOreadsand  
writes on Port B are independent of any concurrent Port A operation.  
ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects  
andWrite/Readselects areonlyforenablingwriteandreadoperations and  
arenotrelatedtohigh-impedancecontrolofthedataoutputs.Ifaportenable  
Each FIFO is synchronized to its port clock through at least two flip-flop  
stages.Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability  
ofmetastableeventswhenCLKAandCLKBoperateasynchronouslytoone  
another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.  
TABLE 2 — PORT A ENABLE FUNCTION TABLE  
CSA  
W/RA  
ENA  
MBA  
CLKA  
Data A (A0-A35) I/O  
PORT FUNCTION  
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
High-Impedance  
Input  
None  
None  
H
H
L
Input  
FIFO1 write  
Mail1write  
H
L
↑
Input  
X
↑
Output  
Output  
Output  
Output  
None  
L
H
L
L
FIFO2read  
None  
L
H
H
X
↑
L
H
Mail2 read (set MBF2 HIGH)  
TABLE 3 — PORT B ENABLE FUNCTION TABLE  
CSB  
W/RB  
ENB  
MBB  
CLKB  
Data B (B0-B35) I/O  
PORT FUNCTION  
H
L
L
L
L
L
L
L
X
L
X
L
X
X
L
X
X
↑
High-Impedance  
Input  
None  
None  
L
H
H
L
Input  
FIFO2 write  
Mail2write  
L
H
L
↑
Input  
H
H
H
H
X
↑
Output  
Output  
Output  
Output  
None  
H
L
L
FIFO1read  
None  
H
H
X
↑
H
Mail1 read (set MBF1 HIGH)  
12  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted  
EFB/ORB,AEB,FFB/IRB,andAFBaresynchronizedtoCLKB.Tables4and  
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReady  
flagsynchronizingclock.Therefore,anOutputReadyflagisLOWifawordin  
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles  
oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime  
thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntil  
thethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simulta-  
neouslyforcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFO  
outputregister.  
5 show the relationship of each port flag to FIFO1 and FIFO2.  
EMPTY/OUTPUTREADYFLAGS(EFA/ORA,EFB/ORB)  
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(ORA,  
ORB)functionisselected.WhentheOutputReadyflagisHIGH,newdatais  
presentintheFIFOoutputregister.WhentheOutputReadyflagisLOW,the  
previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO  
reads are ignored.  
InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty  
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo  
cyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlagisLOW  
ifawordinmemoryisthenextdatatobesenttotheFlFOoutputregisterand  
twocycles oftheportClockthatreads datafromtheFIFOhavenotelapsed  
sincethetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOW  
untilthesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,  
forcing the Empty Flag HIGH; only then can data be read.  
IntheIDTStandardmode,theEmptyFlag(EFA,EFB)functionisselected.  
WhentheEmptyFlagisHIGH,dataisavailableintheFIFO’sRAMmemory  
forreadingtotheoutputregister.WhentheEmptyFlagisLOW,theprevious  
datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare  
ignored.  
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock  
thatreadsdatafromitsarray.ForboththeFWFTandIDTStandardmodes,  
the FIFOreadpointeris incrementedeachtime a newwordis clockedtoits  
outputregister.ThestatemachinethatcontrolsanOutputReadyflagmonitors  
a write pointer and read pointer comparator that indicates when the FIFO  
memorystatusisempty,empty+1,orempty+2.  
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing  
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs  
TABLE 4— FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)  
Synchronized  
to CLKB  
Synchronized  
to CLKA  
Number of Words in FIFO Memory(1,2)  
(3)  
(3)  
(3)  
IDT723624  
IDT723634  
IDT723644  
EFB/ORB  
AEB  
AFA  
FFA/IRA  
0
1toX1  
0
1toX1  
0
1toX1  
L
H
H
H
H
L
L
H
H
H
L
H
H
H
H
L
(X1+1)to[256-(Y1+1)]  
(256-Y1)to255  
256  
(X1+1)to[512-(Y1+1)]  
(512-Y1)to511  
512  
(X1+1)to[1,024-(Y1+1)]  
(1,024-Y1)to1,023  
1,024  
H
H
H
L
NOTES:  
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.  
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register  
(no read operation necessary), it is not included in the FIFO memory count.  
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.  
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.  
TABLE 5— FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)  
Synchronized  
Synchronized  
Number of Words in FIFO Memory(1,2)  
to CLKA  
to CLKB  
(3)  
(3)  
(3)  
IDT723624  
IDT723634  
IDT723644  
EFA/ORA  
AEA  
AFB  
H
FFB/IRB  
0
1toX2  
0
1toX2  
0
1toX2  
L
H
H
H
H
L
L
H
H
H
H
L
H
(X2+1)to[256-(Y2+1)]  
(256-Y2)to255  
256  
(X2+1)to[512-(Y2+1)]  
(512-Y2)to511  
512  
(X2+1)to[1,024-(Y2+1)]  
(1,024-Y2)to1,023  
1,024  
H
H
H
H
L
L
NOTES:  
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.  
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register  
(no read operation necessary), it is not included in the FIFO memory count.  
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.  
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.  
13  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle registersareloadedwithpresetvaluesduringaFlFOreset,programmedfrom  
can be the first synchronization cycle (see Figures 15, 16, 17, and 18).  
PortA,orprogrammedserially(seeAlmost-EmptyflagandAlmost-Fullflag  
offsetprogrammingsection).AnAlmost-FullflagisLOWwhenthenumberof  
words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y)  
forthe IDT723624,IDT723634,orIDT723644respectively.AnAlmost-Full  
flagisHIGHwhenthenumberofwordsinitsFIFOislessthanorequalto[256-  
(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723624, IDT723634, or  
IDT723644 respectively. Note that a data word present in the FIFO output  
registerhas beenreadfrommemory.  
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock  
are requiredaftera FIFOreadforits Almost-Fullflagtoreflectthe newlevel  
of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-  
(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave  
notelapsedsincethereadthatreducedthenumberofwordsinmemoryto[256/  
512/1,024-(Y+1)].AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH  
transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber  
ofwordsinmemoryto[256/512/1,024-(Y+1)].ALOW-to-HIGHtransitionof  
anAlmost-Fullflagsynchronizingclockbeginsthefirstsynchronizationcycle  
ifitoccursattime tSKEW2 orgreaterafterthereadthatreducesthenumberof  
words in memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent  
synchronizingclockcyclemaybethefirstsynchronizationcycle(seeFigures  
25 and 26).  
FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)  
Thisisadualpurposeflag.InFWFTmode,theInputReady(IRAandIRB)  
function is selected. In IDT Standard mode, the Full Flag (FFA and FFB)  
functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis  
HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory  
locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites  
to the FIFO are ignored.  
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat  
writesdatatoitsarray.ForbothFWFTandIDTStandardmodes,eachtime  
awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine  
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer  
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2.  
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready  
to be written to in a minimum of two cycles of the Full/Input Ready flag  
synchronizingclock.Therefore,anFull/InputReadyflagisLOWiflessthan  
twocyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsince  
the next memory write location has been read. The second LOW-to-HIGH  
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets  
the Full/InputReadyflagHIGH.  
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock  
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat  
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcycle  
can be the first synchronization cycle (see Figures 19, 20, 21, and 22).  
MAILBOX REGISTERS  
Each FIFO has a 36-bit bypass register to pass command and control  
informationbetweenPortAandPortBwithoutputtingitinqueue.TheMailbox  
select (MBA, MBB) inputs choose between a mail register and a FIFO for a  
port data transfer operation. The usable width of both the Mail1 and Mail2  
registersmatchestheselectedbussizeforPortB.  
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen  
a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the  
selectedPortBbussizeisalso36bits,thentheusablewidthoftheMail1register  
employsdatalinesA0-A35.IftheselectedPortBbussizeis18bits,thenthe  
usablewidthoftheMail1Registeremploys datalines A0-A17.(Inthis case,  
A18-A35are don’tcare inputs.)Ifthe selectedPortBbus size is 9bits, then  
theusablewidthoftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,  
A9-A35 are don’t care inputs.)  
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2  
RegisterwhenaPortBwriteisselectedbyCSB, W/RB,andENBwithMBB  
HIGH.Ifthe selectedPortBbus size is also36bits,thenthe usable widthof  
theMail2employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits,  
thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthis  
case,B18-B35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits,  
thentheusablewidthoftheMail1RegisteremploysdatalinesB0-B8.(Inthis  
case, B9-B35are don’tcare inputs.)  
Writingdatatoamailregistersetsitscorrespondingflag(MBF1 orMBF2)  
LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.  
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe  
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe  
mailregisterwhenthe portMailboxselectinputis HIGH.  
ALMOST-EMPTY FLAGS (AEA, AEB)  
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads  
data from its array. The state machine that controls an Almost-Empty flag  
monitorsawritepointerandreadpointercomparatorthatindicateswhenthe  
FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.  
Thealmost-emptystateisdefinedbythecontentsofregisterX1forAEBand  
registerX2forAEA.Theseregisters areloadedwithpresetvalues duringa  
FIFOreset,programmedfromPortA,orprogrammedserially(see Almost-  
Empty flag and Almost-Full flag offset programming section). An Almost-  
EmptyflagisLOWwhenitsFIFOcontainsXorlesswordsandisHIGHwhen  
itsFIFOcontains(X+1)ormorewords.AdatawordpresentintheFIFOoutput  
registerhas beenreadfrommemory.  
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock  
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel  
offill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormorewords  
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsince  
thewritethatfilledthememorytothe(X+1)level.AnAlmost-Emptyflagisset  
HIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter  
theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransition  
ofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronization  
cycleifitoccursattimetSKEW2 orgreaterafterthewritethatfillstheFIFOto(X+1)  
words.Otherwise,thesubsequentsynchronizingclockcyclemaybethefirst  
synchronization cycle. (See Figures 23 and 24).  
TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition  
onCLKBwhena PortBreadis selectedbyCSB, W/RB,andENBwithMBB  
HIGH.Fora36-bitbussize,36bitsofmailboxdataareplacedonB0-B35.For  
an18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.(Inthiscase,  
B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are  
placed on B0-B8. (In this case, B9-B35 are indeterminate.)  
ALMOST-FULL FLAGS (AFA, AFB)  
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites  
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitors  
a write pointer and read pointer comparator that indicates when the FIFO  
memorystatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate  
isdefinedbythecontentsofregisterY1forAFAandregisterY2forAFB.These  
14  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition dataisreadfromtheFIFO1RAMandbeforedataiswrittentotheFIFO2RAM.  
onCLKAwhenaPortAreadisselectedbyCSA,W/RA,andENAwithMBA Thesebus-matchingoperationsarenotavailablewhentransferringdatavia  
HIGH.  
mailboxregisters.Furthermore,boththeword-andbyte-sizebusselections  
Fora 36-bit bus size, 36 bits of mailboxdata are placed onA0-A35. For limitthewidthofthedatabusthatcanbeusedformailregisteroperations.In  
an18-bitbussize,18bitsofmailboxdataareplacedonA0-A17.(Inthiscase, thiscase,onlythosebytelanesbelongingtotheselectedword-orbyte-size  
A18-A35are indeterminate.)Fora 9-bitbus size, 9bits ofmailboxdata are buscancarrymailboxdata.Theremainingdataoutputswillbeindeterminate.  
placedonA0-A8. (Inthis case, A9-A35are indeterminate.)  
Theremainingdatainputswillbedon’tcareinputs.Forexample,whenaword-  
Thedatainamailregisterremainsintactafteritisreadandchangesonly sizebusisselected,thenmailboxdatacanbetransmittedonlybetweenA0-  
whennewdataiswrittentotheregister.TheEndianselectfeaturehasnoeffect A17andB0-B17.Whenabyte-sizebusisselected,thenmailboxdatacanbe  
onmailboxdata.FormailregisterandMailRegisterflagtimingdiagrams,see transmitted only between A0-A8 and B0-B8. (See Figures 27 and 28).  
Figure 27 and 28.  
BUS-MATCHING FIFO1 READS  
BUS SIZING  
DataisreadfromtheFIFO1RAMin36-bitlongwordincrements.Ifalong  
The Port B bus can be configured in a 36-bit long word, 18-bit word, or wordbus size is implemented, the entire longwordimmediatelyshifts tothe  
9-bit byte format for data read from FIFO1 or written to FIFO2. The levels FIFO1outputregister.IfbyteorwordsizeisimplementedonPortB,onlythe  
appliedtothePortBBus Sizeselect(SIZE)andtheBus-Matchselect(BM) firstoneortwobytesappearontheselectedportionoftheFIFO1outputregister,  
determinethePortBbussize.TheselevelsshouldbestaticthroughoutFIFO withtherestofthelongwordstoredinauxiliaryregisters.Inthiscase,subsequent  
operation.BothbussizeselectionsareimplementedatthecompletionofMaster FIFO1readsoutputtherestofthelongwordtotheFIFO1outputregisterinthe  
Reset,bythetimetheFull/InputReadyflagissetHIGH,asshowninFigure order shown by Figure 2.  
2.  
WhenreadingdatafromFIFO1inbyteorwordformat,theunusedB0-B35  
TwodifferentmethodsforsequencingdatatransferareavailableforPort outputsareindeterminate.  
Bwhenthebussizeselectioniseitherbyte-orword-size.Theyarereferred  
toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant  
bytefirst).ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-  
to-HIGHtransitionofMRS1andMRS2selectstheendianmethodthatwillbe  
active during FIFO operation. BE is a don’t care input when the bus size  
selected for Port B is long word. The endian method is implemented at the  
completionofMasterReset,bythetimetheFull/InputReadyflagissetHIGH,  
as shown in Figure 2.  
BUS-MATCHING FIFO2 WRITES  
DataiswrittentotheFIFO2RAMin36-bitlongwordincrements.Datawritten  
toFIFO2withabyteorwordbussizestorestheinitialbytesorwordsinauxiliary  
registers.TheCLKBrisingedgethatwritesthefourthbyteorthesecondword  
oflongwordtoFIFO2alsostores theentirelongwordintheFIFO2memory.  
The bytes are arranged in the manner shown in Figure 2.  
WhenwritingdatatoFIFO2inbyteorwordformat,theunusedB0-B35inputs  
aredon'tcareinputs.  
Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories  
ontheIDT723624/723634/723644.Bus-matchingoperationsaredoneafter  
15  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
A35 A27  
A26 A18  
A17 A9  
A8 A0  
BYTE ORDER ON PORT A:  
Write to FIFO1/  
Read from FIFO2  
D
A
B
C
B35 B27  
B26 B18  
B17 B9  
B8 B0  
BE BM SIZE  
Read from FIFO1/  
Write to FIFO2  
A
B
D
C
X
L
X
(a) LONG WORD SIZE  
BYTE ORDER ON PORT B:  
BE BM SIZE  
B35 B27  
B35 B27  
B26 B18  
B26 B18  
B17 B9  
B8 B0  
1st: Read from FIFO1/  
Write to FIFO2  
A
B
H
H
L
B17 B9  
B8 B0  
2nd: Read from FIFO1/  
Write to FIFO2  
C
D
(b) WORD SIZE  
BIG ENDIAN  
B17 B9  
C
B35 B27  
B35 B27  
B26 B18  
B8 B0  
1st: Read from FIFO1/  
Write to FIFO2  
BE BM SIZE  
D
L
H
L
B26 B18  
B17 B9  
B8 B0  
2nd: Read from FIFO1/  
Write to FIFO2  
A
B
(c) WORD SIZE  
LITTLE-ENDIAN  
B35 B27  
B35 B27  
B35 B27  
B26 B18  
B17 B9  
B8 B0  
BE BM SIZE  
1st: Read from FIFO1/  
Write to FIFO2  
A
H
H
H
B26 B18  
B26 B18  
B17 B9  
B17 B9  
B8 B0  
2nd: Read from FIFO1/  
Write to FIFO2  
B
B8 B0  
3rd: Read from FIFO1/  
Write to FIFO2  
C
B35 B27  
B26 B18  
B17 B9  
B8 B0  
4th: Read from FIFO1/  
Write to FIFO2  
D
(d) BYTE SIZE  
BIG-ENDIAN  
B35 B27  
B35 B27  
B35 B27  
B35 B27  
B26 B18  
B17 B9  
B8 B0  
BE BM SIZE  
1st: Read from FIFO1/  
Write to FIFO2  
D
L
H
H
B26 B18  
B26 B18  
B17 B9  
B17 B9  
B8 B0  
2nd: Read from FIFO1/  
Write to FIFO2  
C
B8 B0  
3rd: Read from FIFO1/  
Write to FIFO2  
B
B26 B18  
B17 B9  
B8 B0  
4th: Read from FIFO1/  
Write to FIFO2  
A
(e) BYTE SIZE  
LITTLE-ENDIAN  
3270 drw 04  
Figure 2. Bus Sizing  
16  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
CLKA  
CLKB  
tRSTS  
tRSTH  
MRS1  
tBEH  
tBES  
tFWS  
BE/FWFT  
BE  
0,1  
FWFT  
tSPMS  
tFSS  
tSPMH  
SPM  
FS1,FS0  
FFA/IRA  
tFSH  
tWFF  
tWFF  
(3)  
tREF  
EFB/ORB  
AEB  
tRSF  
tRSF  
tRSF  
AFA  
MBF1  
3270 drw05  
NOTES:  
1. FIFO2 (MRS2) Master Reset is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset (MRS1) must toggle simultaneously with MRS2.  
2. PRS1 must be HIGH during Master Reset.  
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.  
Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)  
CLKA  
CLKB  
tRSTS  
tRSTH  
PRS1  
tWFF  
tWFF  
FFA/IRA  
(3)  
tREF  
EFB/ORB  
tRSF  
AEB  
tRSF  
tRSF  
AFA  
MBF1  
3270 drw06  
NOTES:  
1. Partial Reset is performed in the same manner for FIFO2.  
2. MRS1 must be HIGH during Partial Reset.  
3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.  
Figure 4. FIFO1 Partial Reset(1) (IDT Standard and FWFT Modes)  
17  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
CLKA  
2
1
4
MRS1,  
MRS2  
t
FSS  
t
FSH  
SPM  
t
FSS  
t
FSH  
0,0  
FS1,FS0  
t
WFF  
FFA/IRA  
(1)  
tSKEW1  
tENS2  
tENH  
ENA  
A0-A35  
CLKB  
tDH  
t
DS  
AFB Offset  
(Y 2)  
AEA Offset  
(X 2)  
AEB Offset  
(X1)  
AFA Offset  
First Word to FIFO1  
(Y1)  
1
2
t
WFF  
3270 drw07  
FFB/IRB  
NOTES:  
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA  
and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.  
2. CSA=LOW, W/RA=HIGH,MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.  
Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)  
CLKA  
4
MRS1,  
MRS2  
t
FSS  
tFSH  
SPM  
t
WFF  
(1)  
tSKEW  
FFA/IRA  
t
SENS  
t
FSS  
t
SENH  
SDH  
t
SENS  
t
SENH  
tSPH  
FS1/SEN  
tSDS  
t
tSDS  
tSDH  
FS0/SD(3)  
AFA Offset  
(Y1) MSB  
AEA Offset  
(X2) LSB  
CLKB  
4
t
WFF  
3270 drw08  
FFB/IRB  
NOTES:  
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA  
and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.  
2. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA and FFB/IRB is set HIGH.  
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).  
Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes)  
18  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tCLK  
tCLKH  
tCLKL  
CLKA  
FFA/IRA HIGH  
t
ENH  
ENH  
t
ENS1  
CSA  
tENS1  
t
W/RA  
t
ENS2  
ENS2  
t
ENH  
ENH  
MBA  
ENA  
t
tENS2  
tENS2  
tENH  
t
tENH  
tDS  
tDH  
W1(1)  
W2(1)  
A0 - A35  
No Operation  
3270 drw09  
NOTE:  
1. Written to FIFO1.  
Figure 7. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
tCLK  
tCLKH  
tCLKL  
CLKB  
FFB/IRB  
HIGH  
tENS1  
tENH  
CSB  
tENS1  
tENH  
W/RB  
tENS2  
tENH  
MBB  
tENS2  
tENS2  
tENH  
tENH  
tENS2  
tENH  
ENB  
B0-B35  
NOTE:  
tDH  
t
DS  
W1(1)  
W2(1)  
No Operation  
3270 drw10  
1. Written to FIFO2.  
DATA SIZE TABLE FOR LONG-WORD WRITES TO FIFO2  
SIZE MODE(1)  
DATA WRITTEN TO FIFO2  
DATA READ FROM FIFO2  
BM  
SIZE  
BE  
B35-B27  
B26-B18  
B17-B9  
B8-B0  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
L
X
X
A
B
C
D
A
B
C
D
NOTE:  
1. BE is selected at Master Reset: BM and SIZE must be static throughout device operation.  
Figure 8. Port B Long-Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
19  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
CLKB  
FFB/IRB HIGH  
tENS1  
tENH  
CSB  
t
ENS1  
ENS2  
W/RB  
t
t
ENS2  
ENS2  
tENH  
t
ENH  
MBB  
tENS2  
t
t
ENH  
tENH  
ENB  
tDH  
tDS  
B0-B17  
3270 drw11  
DATA SIZE TABLE FOR WORD WRITES TO FIFO2  
SIZE MODE(1)  
SIZE  
WRITE NO. DATA WRITTEN TO FIFO2  
DATA READ FROM FIFO2  
BM  
BE  
B17-B9  
B8-B0  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
1
2
1
2
A
C
C
A
B
D
D
B
H
L
L
H
A
B
C
D
H
L
A
B
C
D
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.  
Figure 9. Port B Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
CLKB  
HIGH  
FFB/IRB  
tENH  
tENS1  
CSB  
tENS1  
W/RB  
MBB  
tENH  
tENH  
tENS2  
tENS2  
tENH  
tENS2  
tENH  
ENB  
tDS  
tDH  
B0-B8  
3270 drw12  
DATA SIZE TABLE FOR BYTE WRITES TO FIFO2  
SIZE MODE(1)  
WRITE  
NO.  
DATA WRITTEN  
TO FIFO2  
DATA READ FROM FIFO2  
BM  
SIZE  
BE  
B8-B0  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
H
H
H
H
A
B
C
C
D
H
L
A
B
D
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.  
Figure 10. Port B Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
20  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tCLK  
tCLKH  
tCLKL  
CLKB  
EFB/ORB HIGH  
CSB  
W/RB  
MBB  
tENS2  
tENH  
tENS2  
tENH  
tENH  
tENS2  
ENB  
t
MDV  
No Operation  
W2(1)  
tDIS  
t
A
t
A
t
EN  
W1(1)  
W2(1)  
B0-B35  
Previous Data  
(Standard Mode)  
t
MDV  
tDIS  
tA  
t
A
OR  
tEN  
W3(1)  
(1)  
B0-B35  
W1  
(FWFT Mode)  
3270 drw13  
NOTE:  
1. Read From FIFO1.  
DATA SIZE TABLE FOR FIFO LONG-WORD READS FROM FIFO1  
SIZE MODE(1)  
SIZE  
DATA WRITTEN TO FIFO1  
DATA READ FROM FIFO1  
BM  
BE  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
B35-B27  
B26-B18  
B17-B9  
B8-B0  
L
X
X
A
B
C
D
A
B
C
D
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.  
Figure 11. Port B Long-Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
CLKB  
EFB/ORB HIGH  
CSB  
W/RB  
MBB  
ENB  
tENS2  
tMDV  
tENH  
No Operation  
Read 2  
tA  
tA  
tDIS  
tDIS  
tEN  
tEN  
B0-B17  
(Standard Mode)  
Read 1  
Read 2  
Previous Data  
tMDV  
OR  
t
A
tA  
Read 1  
B0-B17  
(FWFT Mode)  
Read 3  
3270 drw14  
NOTE:  
1. Unused word B18-B35 are indeterminate for word size reads.  
DATA SIZE TABLE FOR WORD READS FROM FIFO1  
SIZE MODE(1)  
SIZE  
DATA WRITTEN TO FIFO1  
READ NO.  
DATA READ FROM FIFO1  
BM  
BE  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
B17-B9  
B8-B0  
H
L
L
H
A
B
C
D
1
2
A
C
B
D
H
L
A
B
C
D
1
2
C
A
D
B
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .  
Figure 12. Port-B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
21  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
CLKB  
EFB/ORB  
HIGH  
CSB  
W/RB  
MBB  
tENS2  
tENH  
ENB  
No Operation  
t
DIS  
DIS  
t
MDV  
t
A
t
A
t
A
t
A
t
EN  
B0-B8  
Read 2  
Read 1  
Previous Data  
Read 4  
Read 5  
Read 3  
(Standard Mode)  
t
MDV  
t
OR  
t
A
tA  
tA  
t
A
t
EN  
B0-B8  
Read 1  
Read 2  
Read 3  
Read 4  
(FWFT Mode)  
3270 drw15  
NOTE:  
1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate.  
DATA SIZE TABLE FOR BYTE READS FROM FIFO1  
SIZE MODE(1)  
DATA WRITTEN TO FIFO1  
READ NO.  
DATA READ  
FROM FIFO1  
BM  
SIZE  
BE  
A35-A27  
A26-A18  
A17-A9  
A8-A0  
B8-B0  
1
2
3
4
A
B
C
D
D
C
B
A
H
H
H
H
A
B
C
D
D
1
2
3
4
H
L
A
B
C
NOTE:  
1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.  
Figure 13. Port-B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)  
tCLK  
tCLKL  
tCLKH  
CLKA  
EFA/ORA HIGH  
CSA  
W/RA  
MBA  
tENS2  
tENS2  
tENH  
tENH  
tENH  
tENS2  
ENA  
No Operation  
W2(1)  
t
MDV  
t
DIS  
DIS  
t
A
t
A
t
EN  
A0-A35  
W1(1)  
W2(1)  
Previous Data  
(Standard Mode)  
t
MDV  
t
tA  
t
A
OR  
t
EN  
A0-A35  
W1(1)  
W3(1)  
(FWFT Mode)  
3270 drw16  
NOTE:  
1. Read From FIFO2.  
Figure 14. Port-A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)  
22  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tCLK  
tCLKL  
tCLKH  
CLKA  
CSA  
LOW  
HIGH  
WRA  
t
ENS2  
ENS2  
t
ENH  
MBA  
t
tENH  
ENA  
IRA  
HIGH  
tDS  
tDH  
A0-A35  
W1  
t
CLK tCLKL  
(1)  
tCLKH  
tSKEW1  
CLKB  
1
2
3
t
REF  
tREF  
ORB  
FIFO1 Empty  
LOW  
CSB  
W/RB  
HIGH  
LOW  
MBB  
tENS2  
tENH  
ENB  
tA  
Old Data in FIFO1 Output Register  
B0-B35  
W1  
3270 drw17  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word tothe FIFO1 output register in three CLKB cycles.  
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB  
cycle later than shown.  
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.  
Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)  
23  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
t
CLK  
t
CLKL  
t
CLKH  
CLKA  
CSA  
LOW  
HIGH  
WRA  
t
ENS2  
ENS2  
t
ENH  
ENH  
MBA  
t
t
ENA  
FFA  
HIGH  
tDS  
tDH  
W1  
A0-A35  
t
CLK  
(1)  
SKEW1  
t
CLKH  
t
tCLKL  
CLKB  
1
2
t
REF  
t
REF  
FIFO1 Empty  
LOW  
EFB  
CSB  
W/RB  
HIGH  
LOW  
MBB  
tENH  
tENS2  
ENB  
B0-B35  
NOTES:  
tA  
W1  
3270 drw18  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge  
and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.  
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.  
Figure 16. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)  
24  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tCLK  
tCLKH  
tCLKL  
CLKB  
CSB  
LOW  
LOW  
W/RB  
MBB  
ENB  
tENS2  
tENH  
tENH  
tENS2  
IRB  
HIGH  
tDH  
tDS  
W1  
B0-B35  
t
CLK  
(1)  
SKEW1  
tCLKH  
t
CLKL  
t
1
2
CLKA  
ORA  
3
t
REF  
tREF  
FIFO2 Empty  
CSA  
W/RA  
MBA  
LOW  
LOW  
LOW  
tENS2  
tENH  
ENA  
A0-A35  
NOTES:  
tA  
Old Data in FIFO2 Output Register  
W1  
3270 drw19  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word tothe FIFO2 output register in three CLKA cycles.  
If the time between the CLKB edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA  
cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.  
Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)  
25  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
t
CLK  
t
CLKL  
t
CLKH  
CLKB  
CSB  
LOW  
LOW  
W/RB  
tENS2  
tENH  
MBB  
ENB  
tENS2  
tENH  
HIGH  
FFB  
tDH  
tDS  
W1  
B0-B35  
(1)  
t
CLK  
tSKEW1  
t
CLKH  
t
CLKL  
1
2
CLKA  
t
REF  
t
REF  
EFA  
FIFO2 Empty  
LOW  
LOW  
LOW  
CSA  
W/RA  
MBA  
tENS2  
tENH  
ENA  
tA  
A0-A35  
W1  
3270 drw20  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge  
and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.  
Figure 18. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)  
26  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tCLK  
tCLKH  
tCLKL  
CLKB  
LOW  
CSB  
W/RB  
HIGH  
LOW  
MBB  
tENS2  
tENH  
ENB  
ORB  
HIGH  
tA  
Previous Word in FIFO1 Output Register  
Next Word From FIFO1  
B0-B35  
(1)  
tCLK  
tSKEW1  
tCLKH  
tCLKL  
1
2
CLKA  
t
WFF  
t
WFF  
IRA  
FIFO1 Full  
LOW  
CSA  
W/RA  
HIGH  
tENH  
tENS2  
MBA  
tENS2  
tENH  
ENA  
tDS  
tDH  
Write  
A0-A35  
3270 drw21  
To FIFO1  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising  
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.  
Figure 19. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)  
27  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
tCLK  
tCLKH  
tCLKL  
CLKB  
LOW  
CSB  
W/RB  
HIGH  
LOW  
MBB  
tENS2  
tENH  
ENB  
EFB  
HIGH  
tA  
Previous Word in FIFO1 Output Register  
Next Word From FIFO1  
B0-B35  
(1)  
t
CLK tCLKL  
tSKEW1  
tCLKH  
CLKA  
1
2
t
WFF  
t
WFF  
FFA  
FIFO1 Full  
CSA LOW  
W/RA HIGH  
tENS2  
tENH  
MBA  
tENS2  
tENH  
ENA  
tDH  
tDS  
Write  
A0-A35  
3270 drw22  
To FIFO1  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge  
and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.  
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.  
Figure 20. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)  
28  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
tCLK  
tCLKH  
tCLKL  
CLKA  
CSA  
LOW  
LOW  
LOW  
W/RA  
MBA  
tENS2  
tENH  
ENA  
ORA  
HIGH  
tA  
Previous Word in FIFO2 Output Register  
SKEW1  
Next Word From FIFO2  
A0-A35  
(1)  
tCLK  
t
tCLKH  
tCLKL  
1
2
CLKB  
t
WFF  
t
WFF  
IRB  
CSB  
FIFO2 FULL  
LOW  
W/RB  
LOW  
tENS2  
tENH  
MBB  
ENB  
tENS2  
tENH  
tDS  
tDH  
Write  
B0-B35  
To FIFO2  
3270 drw23  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising  
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.  
2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.  
Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)  
29  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
tCLK  
tCLKH  
tCLKL  
CLKA  
LOW  
LOW  
LOW  
CSA  
W/RA  
MBA  
tENS2  
tENH  
ENA  
EFA  
HIGH  
tA  
Previous Word in FIFO2 Output Register  
Next Word From FIFO2  
A0-A35  
(1)  
tCLK  
tSKEW1  
tCLKH  
tCLKL  
CLKB  
1
2
t
WFF  
t
WFF  
FIFO2 Full  
LOW  
FFB  
CSB  
W/RB  
LOW  
tENS2  
tENH  
MBB  
ENB  
t
ENS2  
t
ENH  
tDS  
tDH  
Write  
B0-B35  
To FIFO2  
3270 drw24  
NOTES:  
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge  
and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.  
2. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.  
Figure 22. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)  
30  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
CLKA  
tENS2  
tENH  
ENA  
(1)  
tSKEW2  
1
2
CLKB  
t
PAE  
t
PAE  
AEB  
X1 Words in FIFO1  
(X1+1) Words in FIFO1  
ENS2  
t
t
ENH  
ENB  
3270 drw25  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge  
and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.  
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.  
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.  
Figure 23. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)  
CLKB  
tENH  
tENS2  
ENB  
(1)  
tSKEW2  
1
2
CLKA  
t
PAE  
t
PAE  
AEA  
X2 Words in FIFO2  
(X2+1) Words in FIFO2  
ENS2  
t
tENH  
ENA  
3270 drw26  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge  
and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.  
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.  
3. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.  
Figure 24. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)  
(1)  
tSKEW2  
1
2
CLKA  
ENA  
tENH  
tENS2  
t
PAF  
t
PAF  
(D-Y1) Words in FIFO1  
[D-(Y1+1)] Words in FIFO1  
AFA  
CLKB  
tENS2  
tENH  
ENB  
3270 drw 27  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge  
and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.  
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.  
3. D = Maximum FIFO Depth = 256 for the IDT723624, 512 for the IDT723634, 1,024 for the IDT723644.  
4. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.  
Figure 25. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)  
31  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
(1)  
tSKEW2  
1
2
CLKB  
ENB  
tENH  
tPAF  
tENS2  
tPAF  
(D-Y2) Words in FIFO2  
tENH  
AFB  
[D-(Y2+1)] Words in FIFO2  
CLKA  
ENA  
tENS2  
3270 drw28  
NOTES:  
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge  
and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.  
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.  
3. D = Maximum FIFO Depth = 256 for the IDT723624, 512 for the IDT723634, 1,024 for the IDT723644.  
4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.  
Figure 26. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)  
CLKA  
tENS1  
t
ENH  
ENH  
CSA  
tENS1  
t
W/RA  
t
ENS2  
ENS2  
t
ENH  
MBA  
t
tENH  
ENA  
tDH  
tDS  
W1  
A0-A35  
CLKB  
t
PMF  
t
PMF  
MBF1  
CSB  
W/RB  
MBB  
ENB  
tENH  
tENS2  
t
PMR  
tEN  
t
MDV  
tDIS  
B0-B35  
W1 (Remains valid in Mail1 Register after read)  
3270 drw29  
FIFO1 Output Register  
NOTE:  
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will be  
indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data  
(B9-B35 will be indeterminate).  
Figure 27. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)  
32  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
CLKB  
tENS1  
tENH  
CSB  
W/RB  
MBB  
ENB  
t
ENS1  
ENS2  
t
ENH  
t
t
ENH  
tENS2  
t
t
ENH  
DH  
tDS  
W1  
B0-B35  
CLKA  
t
PMF  
tPMF  
MBF2  
CSA  
W/RA  
MBA  
ENA  
tENH  
tENS2  
t
PMR  
tEN  
tDIS  
t
MDV  
W1 (Remains valid in Mail 2 Register after read)  
A0-A35  
3270 drw30  
FIFO2 Output Register  
NOTE:  
1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don’t care inputs). In this first case A0-A17 will have valid data  
(A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don’t care inputs). In this second  
case, A0-A8 will have valid data (A9-A35 will be indeterminate).  
Figure 28. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)  
33  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
IDT723624/723634/723644CMOSSyncBiFIFO™WITHBUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2  
PARAMETER MEASUREMENT INFORMATION  
5 V  
1.1 k Ω  
From Output  
Under Test  
30 pF(1)  
680Ω  
PROPAGATION DELAY  
LOAD CIRCUIT  
3 V  
3 V  
Timing  
Input  
1.5 V  
High-Level  
1.5 V  
Input  
GND  
1.5 V  
1.5 V  
GND  
3 V  
t
S
th  
t
W
3 V  
Data,  
Enable  
Input  
1.5 V  
1.5 V  
Low-Level  
1.5 V  
GND  
GND  
Input  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
VOLTAGE WAVEFORMS  
PULSE DURATIONS  
3 V  
Output  
Enable  
1.5 V  
1.5 V  
t
PZL  
GND  
t
PLZ  
3 V  
≈
3 V  
Input  
1.5 V  
1.5 V  
1.5 V  
Low-Level  
Output  
GND  
V
OL  
t
PD  
t
PZH  
tPD  
V
OH  
V
OH  
In-Phase  
Output  
1.5 V  
1.5 V  
High-Level  
Output  
1.5 V  
V
t
PHZ  
OL  
≈
OV  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
3270 drw31  
NOTE:  
1. Includes probe and jig capacitance.  
Figure 29. Output Load and AC Test Conditions  
34  
ORDERING INFORMATION  
IDT  
X
XX  
X
X
XXXXXX  
Device Type Power  
Speed  
Package  
Process/  
Temperature  
Range  
BLANK  
I(1)  
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)  
Thin Quad Flat Pack (TQFP, PK128-1)  
PF  
Commercial Only  
Commercial Only  
Com’l & Ind’l  
12  
15  
20  
30  
Clock Cycle Time (tCLK)  
Speed in Nanoseconds  
Commercial Only  
Low Power  
L
256 x 36 x 2 SyncBiFIFO with Bus-Matching  
512 x 36 x 2 SyncBiFIFO with Bus-Matching  
1,024 x 36 x 2 SyncBiFIFO with Bus-Matching  
3270 drw32  
723624  
723634  
723644  
NOTE:  
1. Industrial temperature range is available by special order for speed grades faster than 20ns.  
DATASHEETDOCUMENTHISTORY  
10/04/2000  
03/22/2001  
pgs. 1 through 35, except pgs. 20, 24-26, 32 and 33.  
pgs. 6 and 7.  
CORPORATE HEADQUARTERS  
2975StenderWay  
Santa Clara, CA 95054  
for SALES:  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
www.idt.com  
for TECH SUPPORT:  
408-330-1753  
FIFOhelp@idt.com  
PFPkg:www.idt.com/docs/PSC4045.pdf  
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.  
The SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.  
35  

相关型号：

IDT723644L30PF

 x36 Synchronous Bidirectional FIFO
ETC

IDT723646

 CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT

IDT723646L12PF

 CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT

IDT723646L12PF8

 Bi-Directional FIFO, 1KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT

IDT723646L12PFG

 FIFO, 1KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT

IDT723646L15PF

 CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT

IDT723646L15PF8

 Bi-Directional FIFO, 1KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT

IDT723646L15PF9

 FIFO, 1KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT

IDT723646L20PF

 Bi-Directional FIFO, 1KX36, 12ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT

IDT723646L30PF

 Bi-Directional FIFO, 1KX36, 15ns, Synchronous, CMOS, PQFP128, TQFP-128
IDT

IDT723651

 CMOS SyncFIFOO 512 x 36, 1024 x 36, 2048 x 36
IDT

IDT723651L15PF

 CMOS SyncFIFOO 512 x 36, 1024 x 36, 2048 x 36
IDT
©2020 ICPDF网 联系我们和版权申明