IDT72521L50G [IDT]
PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18; 并行双向FIFO 512× 18 1024× 18
| 型号： | IDT72521L50G |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18 |
| 文件： | 总28页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72511
IDT72521
PARALLEL BIDIRECTIONAL FIFO
512 x 18 & 1024 x 18
Integrated Device Technology, Inc.
FEATURES:
• Two side-by-side FIFO memory arrays for bidirectional
data transfers
• 512 x 18-Bit - 512 x 18-Bit (IDT72511)
• 1024 x 18-Bit - 1024 x 18-Bit (IDT72521)
• 18-bit data buses on Port A side and Port B side
• Can be configured for 18-to-18-bit or 36-to-36-bit com-
munication
DESCRIPTION:
The IDT72511 and IDT72521 are highly integrated first-in,
first-out memories that enhance processor-to-processor and
processor-to-peripheral communications. IDT BiFIFOs inte-
grate two side-by-side memory arrays for data transfers in
two directions.
The BiFIFOs have two ports, A and B, that both have
standard microprocessor interfaces. All BiFIFO operations
are controlled from the 18-bit wide Port A. Port B is also 18
bits wide and can be connected to another processor or a
peripheral controller. The BiFIFOs have a 9-bit bypass path
that allows the device connected to Port A to pass messages
directly to the Port B device.
• Fast 35ns access time
• Fully programmable standard microprocessor interface
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
Ten registers are accessible through Port A, a Com-
mand Register, a Status Register, and eight Configuration
Registers.
• Two programmable flags, Almost-Empty and Almost-Full
for each FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• Any of the eight flags can be assigned to four external
flag pins
• Flexible reread/rewrite capabilities
• Six general-purpose programmable I/O pins
• Standard DMA control pins for data exchange with
peripherals
The IDT BiFIFO has programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight inter-
nal flags can be assigned to any of four external flag pins
(FLGA-FLGD) through one Configuration Register.
Port B has programmable I/O, reread/rewrite and DMA
functions. Six programmable I/O pins are manipulated through
• 68-pin PGA and PLCC packages
SIMPLIFIED BLOCK DIAGRAM
18-Bit
FIFO
18-bits
18-bits
9-bits
Bypass
Data
Data
Port
A
Port
B
18-Bit
FIFO
Programmable
I/O Logic
I/O
Registers
Processor
Interface
B
Processor
Interface
A
Control
Flags
Control
Programmable
Flag Logic
Handshake
Interface
DMA
2668 drw 01
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DECEMBER 1995
1996 Integrated Device Technology, Inc.
DSC-2668/6
5.32
1
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
two Configuration Registers. The Reread and Rewrite controls
will read or write Port B data blocks multiple times. The
BiFIFO has three pins, REQ, ACK and CLK, to control DMA
transfers from Port B devices.
PIN CONFIGURATIONS
DB17 FLGB FLGD A0
DA15 DA13 DA11
11
10
09
08
07
06
05
04
03
02
01
DB13 DB14
DB11 DB12 DB15 FLGA FLGC A1
DA17 DA14 DA12 PIO5 PIO4
DA9 DA10
DB9
DB10
GND DB8
RB GND
PIO3 DA8
LDRER
GND
DSA
RS
WB
DB7
DB5
VCC
DB16
DB6
VCC
GND
PIO2
G68-1
PGA
TOP VIEW
LDREW
DA7 DA16
DB3
DB2
DB4
PIO0 DA0 DA2 DA5DA6
DB1 CLK REQ
RER R/WA
PIO1 DA1
DA3
J
DA4
K
DB0 ACK REW GND
CSA
F
A
B
C
D
E
G
H
L
2668 drw 02
PIN 1
DESIGNATOR
INDEX
9
10
8
7
6
5
4
3
2
68 67 66 65 64 63 62 61
60
DB2
DB3
DB4
DB5
DB6
DB7
DB16
W B (R/WB)
V CC
RB (DSB)
GND
GND
DA5
DA6
DA7
DA16
PIO 2
1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
LDREW
GND
RS
VCC
DS A
GND
LDRER
PIO 3
DA8
54
53
52
51
50
49
48
47
46
45
44
J68-1
PLCC
TOP VIEW
DB8
DB9
DB10
DB11
DA9
DA10
PIO 4
DB12
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2668 drw 03
5.32
2
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
DA0-DA17
CSA
Name
Data A
I/O
Description
I/O Data inputs and outputs for the 18-bit Port A bus.
Chip Select A
I
I
Port A is accessed when Chip Select A is LOW.
DSA
Data Strobe
A
Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is
read out of Port A on the falling edge of Data Strobe when Chip Select is LOW.
R/WA
Read/Write A
I
I
This pin controls the read or write direction of Port A. When CSA is LOW and R/WA is HIGH,
data is read from Port A on the falling edge of DSA. When CSA is LOW and R/WA is LOW, data
is written into Port A on the rising edge of DSA.
A0, A1
Addresses
When Chip Select A is asserted, A0, A1, and Read/Write A are used to select one of six internal
resources.
DB0-DB17
RB (DSB)
Data B
Read B
I/O Data inputs and outputs for the 18-bit Port B bus.
I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is
programmed to peripheral mode this pin functions as an output. This pin can function as part of
an Intel-style interface (RB) or as part of a Motorola-style interface (DSB). As an Intel-style
interface, data is read from Port B on a falling edge of RB. As a Motorola-style interface, data is
read on the falling edge of DSB or written on the rising edge of DSB through PortB. The default
is Intel-style processor mode. (RB as an input).
WB (R/WB) Write B
I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is
programmed to peripheral mode this pin functions as an output. This pin can function as part of
an Intel-style interface (WB) or as part of a Motorola-style interface (R/WB). As an Intel-style
interface, data is written to Port B on a rising edge of WB. As a Motorola-style interface, data is
read (R/WB = HIGH) or written (R/WB = LOW) to Port B in conjunction with a Data Strobe B
falling or rising edge. The default is Intel-style processor mode (WB as an input.)
RER
Reread
I
I
I
I
I
Loads A→B FIFO Read Pointer with the value of the Reread Pointer when LOW.
Loads B→A FIFO Write Pointer with the value of the Rewrite Pointer when LOW.
Loads the Reread Pointer with the value of the A→B FIFO Read Pointer when HIGH.
Loads the Rewrite Pointer with the value of the B→A FIFO Write Pointer when HIGH.
REW
Rewrite
LDRER
LDREW
REQ
Load Reread
Load Rewrite
Request
When Port B is programmed in peripheral mode, asserting this pin begins a data transfer.
Request can be programmed either active HIGH or active LOW.
ACK
CLK
Acknowledge
O
When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a
Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed
either active HIGH or active LOW.
Clock
Flags
I
This pin is used to generate timing for ACK, RB, WB, DSB and R/WB when Port B is in the
peripheral mode.
FLGA-
FLGD
O
These four outputs pins can be assigned any one of the eight internal flags in the BiFIFO. Each
of the two internal FIFOs (A→B and B→A) has four internal flags: Empty, Almost-Empty,
Almost-Full and Full.
PIO0-PIO5 Program-
mable Inputs/
I/O Six general purpose I/O pins. The input or output direction of each pin can be set independently.
Outputs
RS
Reset
I
A LOW on this pin will perform a reset of all BiFIFO functions.
There are two +5V power pins.
VCC
GND
Power
Ground
There are five Ground pins at 0V.
2668 tbl 01
5.32
3
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETAILED BLOCK DIAGRAM
Reread Pointer
Load Reread Reread
Write Pointer Read Pointer
CSA
DSA
R/WA
A1
LDRER
LDREW
Port A
Control
Port B
Control
RER
REW
A0
RB (DSB) ==
WB (R/WB) ==
A
B FIFO
18
18
Bypass Path
Port B
Port A
DB0-DB17
DA0-DA17
9
9
B
A FIFO
18
18
Read Pointer
Write Pointer
Load Rewrite
Rewrite Pointer
Rewrite
Command
16
Reset
RS
Status
FLGA*
FLGB*
FLGC*
Configuration 0
REQ*
ACK*
CLK
DMA
Control
Programmable
Flag Logic
Configuration 1
Configuration 2
Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7
FLGD*
PIO5 ==
PIO4 ==
PIO3 ==
PIO2 ==
PIO1 ==
PIO0 ==
Programmable
I/O Logic
NOTES:
2668 drw 04
(*) Can be programmed either active high or active low in internal configuration registerers.
(==) Can be programmed through an internal configuration register to be either an input or an output.
5.32
4
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
is connected to the BiFIFO, Port B is programmed to periph-
eral interface mode and the interface pins are outputs.
FUNCTIONAL DESCRIPTION
IDT’s BiFIFO family is versatile for both multiprocessor
and peripheral applications. Data can be sent through both
FIFO memories concurrently, thus freeing both processors
from laborious direct memory access (DMA) protocols and
frequent interrupts.
Two full 18-bit wide FIFOs are integrated into the IDT
BiFIFO, making simultaneous data exchange possible. Each
FIFO is monitored by separate internal read and write point-
ers, so communication is not only bidirectional, it is also
totally independent in each direction. The processor con-
nected to Port A of the BiFIFO can send or receive mes-
sages directly to the Port B device using the BiFIFO’s 9-bit
bypass path.
The BiFIFO can be used in different bus configurations:
18 bits to 18 bits and 36 bits to 36 bits. One BiFIFO can be
used for the 18- to 18-bit configuration, and two BiFIFOs are
required for 36- to 36-bit configuration. This configuration
can be extended to wider bus widths (54- to 54-bits, 72- to
72-bits, …) by adding more BiFIFOs to the configuration.
The microprocessor or microcontroller connected to Port
A controls all operations of the BiFIFO. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B can be programmed to interface either with a second
processor or a peripheral device. When Port B is programmed
in processor interface mode, the Port B interface pins are
inputs driven by the second processor. If a peripheral device
18- to 18-bit Configurations
A single BiFIFO can be configured to connect an 18-bit
processor to another 18-bit processor or an 18-bit peripheral.
The upper BiFIFO shown in each of the Figures 1 and 2 can
be used in 18- to 18-bit configurations for processor and
peripheral interface modes respectively.
36- to 36-bit Configurations
In a 36- to 36-bit configuration, two BiFIFOs operate in
parallel. Both BiFIFOs are programmed simultaneously, 18
data bits to each device. Figures 1 and 2 show multiple
BiFIFOs configured for processor and peripheral interface
modes respectively.
Processor Interface Mode
When a microprocessor or microcontroller is connected to
Port B, all BiFIFOs in the configuration must be programmed
to processor interface mode. In this mode, all Port B inter-
face controls are inputs. Both REQ and CLK pins should be
pulled LOW to ensure that the setup and hold time require-
ments for these pins are met during reset. Figure 1 shows
the BiFIFO in processor interface mode.
IDT
BiFIFO
Cntl A Cntl B
ACK
REQ
CLK
Data A Data B
Processor
B
Processor
A
Address
Control
Control
Data
Data
IDT
BiFIFO
36
36
Cntl A Cntl B
RAM
RAM
ACK
REQ
CLK
Data B
Data A
18
18
2668 drw 05
Figure 1. 36-Bit Processor to 36-Bit Processor Configuration
NOTE:
1. 36- to 36-bit processor interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to CSA, A1, A0, R/WA,
and DSA; Cntl B refers to R/WB and DSB or RB and WB.
5.32
5
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Peripheral Interface Mode
When either of the internal FIFOs are accessed, 18 bits of
If Port B is connected to a peripheral controller, all data are transferred across Port A. Since the bypass path is
BiFIFOs in the configuration must be programmed in peri- only 9 bits wide, the least significant byte (DA0-DA7, DA16) is
pheral interface mode. In this mode, all the Port B interface used on Port A. All of the registers are 16 bits wide which
pins are all outputs. To assure fixed high states for RB and means only the data bits (DA0-DA15) are passed by Port A.
WB before they are programmed into an output, these two
pins should be pulled up to VCC with 10K resistors. Of Bypass Path
course, only one set of Port B interface pins should be used
The bypass path acts as a bidirectional bus transceiver
to control a single peripheral device, while the other interface directly between Port A and Port B. The direct connection
pins are all ignored. Figure 2 shows a BiFIFO configuration requires that the Port A interface pins are inputs and the Port
connected to a peripheral.
B interface pins are outputs. The bypass path is 9 bits wide in
an 18- to 18-bit configuration or 18 bits wide in a 36- to 36-
bit configuration.
Port A Interface
The BiFIFO is straightforward to use in microprocessor-
During bypass operations, the BiFIFOs must be pro-
based systems because each BiFIFO port has a standard grammed into peripheral interface mode. Bit 10 of Configura-
microprocessor control set. Port A has access to six re- tion Register 5 (see Table 10) is set to 1 for peripheral
sources: the A→B FIFO, the B→A FIFO, the 9-bit direct data interface mode.
bus (bypass path), the configuration registers, status and
command registers. The Port A Address and Read/Write Command Register
pins determine the resource being accessed as shown in
Table 1. Data Strobe is used to move data in and out of the Register, a Status Register, and eight Configuration
BiFIFO. Registers.
Ten registers are accessible through Port A, a Command
IDT
BiFIFO
Cntl A Cntl B
ACK
REQ
CLK
DMA or System
Clock
Data A Data B
Peripheral
Controller
Cntl
Processor
Address
ACK
REQ
Control
I/O
Data
Data
Data
36
IDT
BiFIFO
36
Cntl
A
Cntl B
RAM
ACK
REQ
CLK
Data A Data B
2668 drw 06
18
18
Figure 2. 36-Bit Processor to 36-Bit Peripheral Configuration
NOTE:
1. 36- to 36-bit peripheral interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to CSA, A1, A0, R/
WA, and DSA; Cntl B refers to R/WB and DSB or RB and WB.
5.32
6
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The Command Register is written by setting CSA = 0, A1 = command operands shown in Table 4.
1, A0 = 1. Commands written into the BiFIFO have a 4-bit
Intelligent reread/rewrite is performed by interchanging
opcode (bit8 – bit 11) and a 3-bit operand (bit 0 – bit 2) as the Port B Read Pointer with the Reread Pointer or by
shown in Figure 3. The commands can be used to reset the interchanging the Port B Write Pointer with the Rewrite Pointer.
BiFIFO, to select the Configuration Register, to perform intel- No command operands are required to perform a reread/
ligent reread/rewrite, to set the Port B DMA direction, to set rewrite operation.
the Status Register format, and to modify the Port B Read
When Port B of the BiFIFO is in peripheral mode, the DMA
and Write Pointers. The command opcodes are shown in direction is controlled by the Command Register. Table 5
Table 2.
The reset command initializes different portions of the
shows the Port B read/write DMA direction operands.
Two commands are provided to increment the Port B Read
BiFIFO depending on the command operand. Table 3 shows and Write Pointers. No operands are required for these
the reset command operands.
commands.
The configuration Register address is set directly by the
COMMAND FORMAT
15
12
X
11
8
7
3
2
0
X
X
X
Command Opcode
X
X
X
X
X
Command Operand
2668 tbl 02
Figure 3. Format for Commands Written into Port A
5.32
7
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
request DMA circuitry can also be reset independently. A
software Reset All command resets all the pointers, the DMA
request circuitry, and sets all the Configuration Registers to
their default condition. Note that a hardware reset is NOT the
same as a software Reset All command. Table 6 shows the
BiFIFO state after the different hardware and software resets
Reset
The IDT72511 and IDT72521 have a hardware reset pin
(RS) that resets all BiFIFO functions. A hardware reset re-
quiresthefollowingfourconditions:RB andWB mustbeHIGH,
RER and REW must be HIGH, LDRER and LDREW must be
LOW, and DSA must be HIGH (Figure 9). After a hardware
reset, the BiFIFO is in the following state: Configuration
Registers 0-3 are 0000H, Configuration Register 4 is set to
6420H, and Configuration Registers 5, 6 and 7 are 0000H.
Additionally, all the pointers including the Reread and Rewrite
Pointers are set to 0, the DMA direction is set to B→A write,
and the internal DMA request circuitry is cleared (set to its
initial state).
Status Register
The Status Register reports the state of the programmable
flags and the DMA read/write direction. The Status Register
is read by setting CSA = 0, A1 = 1, A0 = 1 (see Table 1). See
Table 7 for the Status Register format.
Configuration Registers
AsoftwareresetcommandcanresetA→Bpointersandthe
B→A pointers to 0 independently or together. The internal
The eight Configuration Register formats are shown in
RESET COMMAND FUNCTIONS
PORT A RESOURCE SELECTION
Reset
A
CS
A1
A0
Read
Write
Operands
Function
0
0
0
B→A FIFO
A→B FIFO
000
No Operation
0
0
0
1
1
0
9-bit Bypass Path 9-bit Bypass Path
001
Reset B→A FIFO (Read, Write, and Rewrite
Configuration
Registers
Configuration
Registers
Pointers = 0)
010
Reset A→B FIFO (Read, Write, and Reread
0
1
1
1
Status Register
Command
Register
Pointers = 0)
011
100
101
110
111
Reset B→A and A→B FIFO
Reset Internal DMA Request Circuitry
No Operation
X
X
Disabled
Disabled
2668 tbl 03
Table 1. Accessing Port A Resources Using CSA, A0 and A1
No Operation
COMMAND OPERATIONS
Reset All
Command
Opcode
2668 tbl 04
Function
Table 3. Reset Command Functions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Reset BiFIFO (see Table 3)
SELECT CONFIGURATION REGISTER/
COMMAND FUNCTIONS
Select Configuration Register (see Table 4)
Load Reread Pointer with Read Pointer Value
Load Rewrite Pointer with Write Pointer Value
Load Read Pointer with Reread Pointer Value
Load Write Pointer with Rewrite Pointer Value
Set DMA Transfer Direction (see Table 5)
Reserved
Operands
Function
Select Configuration Register 0
Select Configuration Register 1
Select Configuration Register 2
Select Configuration Register 3
Select Configuration Register 4
Select Configuration Register 5
Select Configuration Register 6
Select Configuration Register 7
000
001
010
011
100
Increment A→B FIFO Read Pointer (Port B)
Increment B→A FIFO Write Pointer (Port B)
Reserved
101
110
111
Reserved
2668 tbl 06
2668 tbl 05
Table 4. Select Configuration Register Functions.
Table 2. Functions Performed by Port A Commands
DMA DIRECTION COMMAND FUNCTIONS
Operands
XX0
Function
Write B→A FIFO
Read A→B FIFO
XX1
2668 tbl 07
Table 5. Set DMA Direction Command Functions. Command Only
Operates in Peripheral Interface Mode
5.32
8
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
STATE AFTER RESET
Software Reset
Internal
B→A and
Request
(100)
Hardware Reset
(RS asserted)
A→B(011)
B→A(001)
A→B(010)
All(111)
0000H
6420H
0000H
0000H
—
Configuration Registers 0-3
Configuration Register 4
Configuration Register 5
Configuration Register 6-7
Status Register format
0000H
6420H
0000H
0000H
0
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
B→A Read, Write, Rewrite Pointers
A→B Read, Write, Reread Pointers
DMA direction
0
0
0
—
—
0
0
—
—
0
—
—
—
B→A write
clear
DMA internal request
—
—
—
clear
clear
2668 tbl 08
Table 6. The BiFIFO State After a Reset Command
Table8. ConfigurationRegisters0-3containtheprogrammable
flagoffsetsfortheAlmost-EmptyandAlmost-Fullflags. These
offsets are set to 0 when a hardware reset or a software Reset
All is applied. Note that Table 8 shows that Configuration
Registers 0-3 are 10 bits wide to accommodate the 1024
locations in each FIFO memory of the IDT7252/520. Only 9
least significant bits are used for the 512 locations of the
IDT7251/510; the most significant bit, bit 9, must be set to 0.
Configuration Register 4 is used to assign the internal flags
to the external flag pins (FLGA-FLGD). Each external flag pin
is assigned an internal flag based on the four bit codes shown
in Table 9. The default condition for Configuration Register 4
is 6420H as shown in Table 6. The default flag assignments
are: FLGD is assigned B→A Full, FLGC is assigned B→A
Empty, FLGB is assigned A→B Full, FLGA is assigned A→B
Empty.
Six PIO pins can be programmed as an input or output
by the corresponding mask bits in Configuration Register 7.
The format of Configuration Register 7 is shown in Figure
5. Each bit of the register set the I/O direction independ-
ently. A logic 1 indicates that the corresponding PIO pin is
an output, while a logic 0 indicates that the PIO pin is an
input. This I/O mask register can be read or written.
A programmed output PIOi pin (i = 0, 1, . . . 5) displays the
datalatchedinBitiofConfigurationRegister6.Aprogrammed
input PIOi pin allows Port A bus to sample the data on DAi by
reading Configuration Register 6.
STATUS REGISTER FORMAT
Bit
0
Signal
Reserved
Configuration Register 5 is a general control register. The
format of Configuration Register 5 is shown in Table 10.
Bit0setstheIntel-styleinterface(RB, WB)orMotorola-style
interface(DSB, R/WB)forPortB. Bits2and3redefineFulland
Empty Flags for reread/rewrite data protection.
1
Reserved
2
Reserved
3
DMA Direction
4
A→B Empty Flag
Bits 4-9 control the DMA interface and are only applicable
in peripheral interface mode. In processor interface mode,
these bits are don’t care states. Bits 4 and 5 set the polarity of
the DMA control pins REQ and ACK respectively. An internal
clock controls all DMA operations. This internal clock is
derived from the external clock (CLK). Bit 9 determines the
internal clock frequency: the internal clock = CLK or the
internal clock = CLK divided by 2. Bit 8 sets whether RB, WB,
and DSB areassertedforeitheroneortwointernalclocks. Bits
6 and 7 set the number of internal clocks between REQ
assertion and ACK assertion. The timing can be from 2 to 5
cycles as shown in Figure 17.
Bit 10 controls Port B processor or peripheral interface
mode. In processor mode, the Port B control pins (RB, WB,
DSB, R/WB) are inputs and the DMA controls are ignored. In
peripheral mode, the Port B control pins are outputs and the
DMA controls are active.
5
6
7
A→B Almost-Empty Flag
B→A Full Flag
B→A Almost-Full Flag
Reserved
8
9
Reserved
10
11
12
Reserved
Reserved
A→B Full Flag
13
14
15
A→B Almost-Full Flag
B→A Empty Flag
B→A Almost-Empty Flag
2668 tbl 09
Table 7. The Status Register Format
5.32
9
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONFIGURATION REGISTER FORMATS
15
10
9
9
0
Config. Reg. 0
Config. Reg. 1
Config. Reg. 2
Config. Reg. 3
Config. Reg. 4
Config. Reg. 5
Config. Reg. 6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A→B FIFO Almost Empty Flag Offset
15
X
10
X
0
A→B FIFO Almost Full Flag Offset
0
15
10
9
9
X
X
B→A FIFO Almost Empty Flag Offset
15
10
0
X
X
X
X
B→A FIFO Almost Full Flag Offset
15
12
11
8
7
4
3
0
Flag D Pin Assignment
Flag C Pin Assignment
Flag B Pin Assignment
Flag A Pin Assignment
15
0
General Control
I/O Data
15
15
0
0
Config. Reg. 7
NOTE:
I/O Direction Control
2668 tbl 10
1. Bit 9 of Configuration Registers 0-3 must be set to 0 on the IDT72511.
Table 8. The BiFIFO Configuration Register Formats
EXTERNAL FLAG ASSIGNMENT CODES
Programmable Flags
Assignment
Code
The IDT BiFIFO has eight internal flags. Associated with
each FIFO memory array are four internal flags, Empty,
Almost-Empty, Almost-Full and Full, for the total of eight
internal flags. The Almost-Empty and Almost-Full offsets can
be set to any depth through the Configuration Registers 0-3
(see Table 8). The flags are asserted at the depths shown in
Table 11. After a hardware reset or a software Reset All, the
almost flag offsets are set to 0. Even though the offsets are
equivalent, the Empty and Almost-Empty flags have different
timingwhichmeansthattheflagsarenotcoincident.Similarly,
the Full and Almost-Full flags are not coincident after reset
because of timing.
These eight internal flags can be assigned to any of four
external flag pins (FLGA-FLGD) through Configuration Regis-
ter 4 (see Table 9). For the specific flag timings, see Figures
20-23.
The current state of all eight flags is available in the Status
Register.
Internal Flag Assigned to Flag Pin
A→B Empty
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A→B Almost-Empty
A→B Full
A→B Almost-Full
B→A Empty
B→A Almost-Empty
B→A Full
B→A Almost-Full
A→B Empty
A→B Almost-Empty
A→B Full
A→B Almost-Full
B→A Empty
B→A Almost-Empty
B→A Full
B→A Almost-Full
2668 tbl 11
Table 9. Configuration Register 4 Internal Flag Assignments to
External Flag Pins
5.32
10
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CONFIGURATION REGISTER 5 FORMAT
Bit
Function
Select Port B Interface
0
1
2
3
4
5
0
1
Pins are RB and WB (Intel-style interface)
RB and WB or DSB and R/WB
Pins are DSB and R/WB (Motorola-style interface)
Unused
Full Flag Definition
Empty Flag Definition
REQ Pin Polarity
ACK Pin Polarity
0
1
Write pointer meets read pointer
Write pointer meets reread pointer
0
Read pointer meets write pointer
1
Read pointer meets rewrite pointer
0
REQ pin active HIGH
1
REQ pin active LOW
0
ACK pin active LOW
1
ACK pin active HIGH
7-6
REQ / ACK Timing
00
01
10
11
0
2 internal clocks between REQ assertion and ACK assertion
3 internal clocks between REQ assertion and ACK assertion
4 internal clocks between REQ assertion and ACK assertion
5 internal clocks between REQ assertion and ACK assertion
RB, WB, and DSB are asserted for 1 internal clock
RB, WB, and DSB are asserted for 2 internal clocks
Internal clock = CLK
8
Port B Read & Write
Timing Control for Peripheral Mode
1
9
Internal Clock
0
Frequency Control
1
Internal clock = CLK divided by 2
10
Port B Interface
Mode Control
0
Processor interface mode (Port B controls are inputs)
Peripheral interface mode (Port B controls are outputs)
1
11
12
13
14
15
Unused
Unused
Unused
Unused
Unused
2668 tbl 12
Table 10. BiFIFO Configuration Register 5 Format
CONFIGURATION REGISTER 6 FORMAT
15
6
5
4
3
2
1
0
Unused
PIO5
PIO4
PIO3
PIO2
PIO1
PIO0
2668 tbl 13
Figure 4. BiFIFO Configuration Register 6 Format for Programmable I/O Data
CONFIGURATION REGISTER 7 FORMAT
15
6
5
4
3
2
1
0
Unused
MIO5
MIO4
MIO3
MIO2
MIO1
MIO0
2668 tbl 14
Figure 5. BiFIFO Configuration Register 7 Format for Programmable I/O Direction Mask
5.32
11
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Port B Interface
atthesametimethatACKisasserted.Oneinternalclocklater,
Port B has reread/rewrite and DMA functions. Port B can DSB is asserted. If the BiFIFO is in Intel-style interface mode,
be configured to interface to either Intel-style (RB, WB) or either RB or WB is asserted one internal clock after ACK
Motorola-style (DSB, R/WB) devices in Configuration Register assertion. These read/write controls stay asserted for 1 or 2
5 (see Table 10). Port B can also be configured to talk to a internal clocks, then ACK, DSB, RB andWB are made inactive.
processor or a peripheral device through Configuration Reg- This completes the transfer of one 9-bit word.
ister 5. In processor interface mode, the Port B interface
On the next rising edge of CLK, REQ is sampled. If REQ
controls are inputs. In peripheral interface mode, the Port B isstillasserted, anotherDMAtransferstartswiththeassertion
interface controls are outputs. After a hardware reset or a of ACK. Data transfers will continue as long as REQ is
software Reset All command, Port B defaults to an Intel-style asserted.
processor interface; the controls are inputs.
Intelligent Reread/Rewrite
DMA Control Interface
Intelligent reread/rewrite is a method the BiFIFO uses to
The BiFIFO has DMA control to simplify data transfers with help assure data integrity. Port B of the BiFIFO has two extra
peripherals. For the BiFIFO DMA controls (REQ, ACK and pointers, the Reread Pointer and the Rewrite Pointer.The
CLK) to operate, the BiFIFO must be in peripheral interface Reread Pointer is associated with the A->B FIFO Read
mode (Configuration Register 5, Table 10).
Pointer, while the Rewrite Pointer is associated with the B->A
DMA timing is controlled by the external clock input, CLK. FIFO Write Pointer. The Reread Pointer holds the start ad-
An internal clock is derived from this CLK signal to generate dress of a data block in the A->B FIFO RAM, and the Read
the RB, WB, DSB and R/WB output signals. The internal clock Pointer is the current address of the same FIFO RAM array.
also determines the timing between REQ assertion and ACK By loading the Read Pointer with the value held in the Reread
assertion.Bit9ofConfigurationRegister5determineswhether Pointer (RER asserted), reads will start over at the beginning
the internal clock is the same as CLK or whether the internal of the data block. In order to mark the beginning of a data
clock is CLK divided by 2.
block, the Reread Pointer should be loaded with the Read
Bit 8 of Configuration Register 5 set whether RB, WB and Pointer value (LDRER asserted) before the first read is
DSB are asserted for 1 or 2 internal clocks. Bits 6 and 7 of performed on this data block. Figure 6 shows a Reread
Configuration Register 5 set the number of clocks between operation.
REQ assertion and ACK assertion. The clocks between REQ
assertion and ACK assertion can be 2, 3, 4 or 5.
Similarly, the Rewrite Pointer holds the start address of a
data block in the B->A FIFO RAM, while the Write Pointer is
Bits 4 and 5 of Configuration Register 5 set the polarity of thecurrentaddresswithintheRAMarray. Theoperationofthe
the REQ and ACK pins respectively. REW and LDREW is identical to the RER and LDRER dis-
A DMA transfer command sets the Port B read/write cussed above. Figure 7 shows a Rewrite operation.
direction (see Table 5). The timing diagram for DMA transfers For the reread data protection, Bit 2 of Configuration
isshowninFigure17. ThebasicDMAtransferstartswithREQ Register 5 can be set to 1 to prevent the data block from being
assertion. After 2 to 5 internal clocks, ACK is asserted by the overwritten.Inthisway,theassertionofA->Bfullflagwilloccur
BiFIFO. ACK will not be asserted if a read is attempted on an when the write pointer meets the reread pointer instead of the
emptyA→BFIFOorifawriteisattemptedonafullB→AFIFO. read pointer as in the normal definition. For the rewrite data
If the BiFIFO is in Motorola-style interface mode, R/WB is set protection, Bit 3 of Configuration Register 5 can be set to 1 to
INTERNAL FLAG TRUTH TABLE
Number of Words in FIFO
From
0
To
Empty Flag
Asserted
Almost-Empty Flag
Asserted
Almost-Full Flag
Not Asserted
Not Asserted
Not Asserted
Asserted
Full Flag
Not Asserted
Not Asserted
Not Asserted
Not Asserted
Asserted
0
1
n
D – (m + 1)
D – 1
Not Asserted
Not Asserted
Not Asserted
Not Asserted
Asserted
n + 1
D – m
D
Not Asserted
Not Asserted
Not Asserted
D
Asserted
NOTE:
2668 tbl 15
1. BiFIFO flags must be assigned to external flag pins to be observed. D = FIFO depth (IDT72511 = 512, IDT72521 = 1024), n = Almost-Empty flag
offset, m = Almost-Full flag offset.
Table 11. Internal Flag Truth Table
5.32
12
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
prevent the data block from being read. In this case the ter 6. Figure 4 shows the format of Configuration Register 6.
assertion of B->A empty flag will occur when the read pointer This data is read or written by Port A on the data pins
meets the rewrite pointer instead of the write pointer.
(DA0- DA5). A programmed output PIOi pin (i = 0, 1, . . . , 5)
In conclusion, Bit 2 and 3 of Configuration Register 5 are displays the data latched in Bit i of Configuration Register 6.
used to redefine Full & Empty flags for data block partition. A programmed input PIOi pin allows Port A bus to sample its
Although it can serve the purpose of data protection, the dataonDAi byreadingConfigurationRegister6. Thereadand
setting of these 2 bits is independent of the functions caused write timing for the programmable I/O pins is shown in Figure
by RER/REW, or LDRER/LDREW assertions.
19. The direction of each programmable I/O pin can be set
independently by programming the mask in Configuration
Register 7. Each P10 pin has a corresponding input/output
Programmable Input/Output
The BiFlFO has six programmable I/0 pins (PlO0 - PIO5) direction mask bit in Configuration Register 7. Figure 5 shows
which are controlled by Port A through Configuration Regis- the format of Configuration Register 7. Setting a mask bit to a
ters 6 and 7. Data from the programmable I/O pins is mapped logic 1 makes the corresponding I/O pin an output. Mask bits
directly to the six least significant bits of Configuration Regis- set to logic 0 force the corresponding I/O pin to an input.
REREAD OPERATIONS (1,2)
REWRITE OPERATIONS (3,4)
Reread
Pointer
Read
Pointer
Reread
function
Write
Pointer
Write
Pointer
B→A
FIFO
A→B
FIFO
Load
Reread
function
Load Rewrite
function
Rewrite
Pointer
Read
Pointer
Rewrite
function
2668 drw 08
2668 drw 09
NOTES:
1. If bit 2 is set to 1,
NOTES:
1. If bit 3 is set to 1,
Empty flag asserted if Read = Write
Full flag asserted if Reread + FIFO size = Write
2. If bit 2 is set to 0,
Empty flag asserted if Read = Rewrite
Full flag asserted if Read + FIFO size = Write
2. If bit 3 is set to 0,
Empty flag asserted if Read = Write
Full flag asserted if Read + FIFO size = Write
Empty flag asserted if Read = Write
Full flag asserted if Read + FIFO size = Write
Figure 6. BiFIFO Reread Operations
Figure 7. BiFIFO Rewrite Operations
5.32
13
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter
Min.
Typ. Max. Unit
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
V
With Respect To
Ground
VCCM
VCCC
Military Supply
Voltage
4.5
5.0
5.5
V
T
T
T
A
Operating
Temperature
0 to +70
–55 to +125
°C
Commercial Supply
Voltage
4.5
5.0
5.5
V
BIAS
STG
Temperature
Under Bias
–55 to +125 –65 to +135
–55 to +125 –65 to +155
°C
GND
VIH
Supply Voltage
0
0
0
V
V
Input HIGH Voltage
Commercial
2.0
—
—
Storage
Temperature
°C
VIH
Input HIGH Voltage
Military
2.2
—
—
—
—
V
V
IOUT
DC Output
Current
50
50
mA
(1)
VIL
Input LOW Voltage
Commercial and
Military
0.8
NOTE:
2668 tbl 16
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
NOTE:
2668 tbl 17
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
IDT72511L
IDT72521L
Commercial
= 25, 35, 50ns
IDT72521L
Military
t
A
t
A
= 40, 50ns
Typ.
Symbol
Parameter
Min.
Typ.
Max.
Min.
–10
–10
2.4
—
Max.
Unit
(1)
IL
I
Input Leakage Current (Any Input)
Output Leakage Current
–1
–10
2.4
—
—
1
—
—
10
10
µ
A
A
(2)
I
OL
—
10
µ
V
OH
OL
Output Logic "1" Voltage IOUT = –1mA
Output Logic "0" Voltage IOUT = 4mA
Average VCC Power Supply Current
—
—
—
—
V
V
—
0.4
230
30
—
0.4
250
50
V
(3)(4)
(3)
I
CC1
CC2
—
150
16
—
180
24
mA
mA
I
Average Standby Current (R
B
= WB
= DS
A
=
—
—
VIH)
2668 tbl 18
NOTES:
1. Measurements with 0.4V ≤ VIN ≤ VCC, DSA = DSB ≥ VIH
2. Measurements with 0.4V ≤ VOUT ≤ VCC, DSA = DSB ≥ VIH
3. Measurements are made with outputs open.
+5V
AC TEST CONDITIONS
1.1 k
Ω
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
D.U.T.
1.5V
*
680
Ω
30 pF
1.5V
See Figure 8
2668 tbl 19
CAPACITANCE (TA = +25°C, f = 1.0MHz)
2668 drw 09
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions Max. Unit
or equivalent circuit
(2)
C
IN
V
IN = 0V
8
pF
Figure 8. Output Load
*Includes jig and scope capacitances
(1,2)
C
OUT
VOUT = 0V
12
pF
NOTES:
1. With output deselected.
2. Characterized values, not currently tested.
2668 tbl 20
5.32
14
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to + 125°C)
(2)
Commercial
Military
Com'l & Mil.
IDT72511L50
IDT72521L50
IDT72511L25
IDT72521L25
IDT72511L35
IDT72521L35
IDT72521L40
Timing
Figure
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
RESET TIMING (Port A and Port B)
t
t
t
t
t
RSC
Reset cycle time
Reset pulse width
Reset set-up time
Reset recovery time
Reset to flag time
35
25
25
10
—
—
—
—
—
35
45
35
35
10
—
—
—
—
—
45
50
40
40
10
—
—
—
—
—
50
65
50
50
15
—
—
—
—
—
65
ns
ns
ns
ns
ns
9
9
9
9
9
RS
RSS
RSR
RSF
PORT A TIMING
ta
A
Port A access time
—
5
25
—
—
5
35
—
—
5
40
—
—
5
50
—
ns
ns
12, 14, 15
12, 15, 16
taLZ
taHZ
taDV
Read or write pulse
LOW to data bus at
Low-Z
Read or write pulse
HIGH to data bus at
High- Z
—
5
15
—
—
5
20
—
—
5
25
—
—
5
30
—
ns
ns
12, 14, 15, 16
12, 14, 16
Data valid from read
pulse HIGH
taRC
taRPW
taRR
taS
Read cycle time
Read pulse width
Read recovery time
35
25
10
5
—
—
—
—
45
35
10
5
—
—
—
—
50
40
10
5
—
—
—
—
65
50
15
5
—
—
—
—
ns
ns
ns
ns
12
12, 14, 15
12
CSA
, A0
, A
1
, R/W
A
set-
10, 12, 16
up time
ta
H
CS , A
time
A
0
, A
1
, R/W
A
hold
5
—
5
—
5
—
5
—
ns
10, 12
taDS
taDH
Data set-up time
Data hold time
Write cycle time
15
0
—
—
—
—
—
—
18
2
—
—
—
—
—
—
20
5
—
—
—
—
—
—
30
5
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
11, 12, 14, 15
(1)
11, 12, 14, 15
taWC
35
25
10
25
45
35
10
35
50
40
10
40
65
50
15
50
12
11, 12, 14
12
taWPW
taWR
Write pulse width
Write recovery time
taWRCOM Write recovery time after
a command
11
2668 tbl 21
NOTE:
1. The minimum data hold time is 5ns (10ns for the 80ns speed grade) when writing to the Command or Configuration registers.
2. IDT72511 not available in military.
5.32
15
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to + 125°C)
Commercial
Military
Com'l & Mil.(1)
IDT72511L50
IDT72521L50
IDT72511L25
IDT72521L25
IDT72511L35
IDT72521L35
IDT72521L40
Timing
Figure
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
PORT B PROCESSOR INTERFACE TIMING
tbA
Port B access time
—
5
25
—
—
5
35
—
—
5
40
—
—
5
50
—
ns
ns
13, 14, 15
13, 14, 15
tbLZ
Read or write pulse
LOW to data bus at
Low-Z
tbHZ
tbDV
Read or write pulse
HIGH to data bus at
High-Z
—
5
15
—
—
5
20
—
—
5
25
—
—
5
30
—
ns
ns
14, 13, 15
Data valid from read
pulse HIGH
13, 14, 15, 16
tbRC
tbRPW
tbRR
tbS
Read cycle time
Read pulse width
Read recovery time
R/WB set-up time
R/WB hold time
Data set-up time
Data hold time
35
25
10
5
—
—
—
—
—
—
—
—
—
—
45
35
10
5
—
—
—
—
—
—
—
—
—
—
50
40
10
5
—
—
—
—
—
—
—
—
—
—
65
50
15
5
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
13
13
13
tbH
5
5
5
5
13
tbDS
tbDH
tbWC
tbWPW
tbWR
15
0
18
2
20
5
30
5
13, 14, 15
13, 14, 15
13
Write cycle time
Write pulse width
Write recovery time
35
25
10
45
35
10
50
40
10
65
50
15
13, 15
13
PORT B PERIPHERAL INTERFACE TIMING
tbA
Port B access time
Clock cycle time
—
15
6
25
—
—
—
—
—
15
—
20
6
40
—
—
—
—
—
18
—
20
8
45
—
—
—
—
—
20
—
25
10
10
10
5
55
—
—
—
—
—
25
ns
ns
ns
ns
ns
ns
ns
17
17
17
17
17
17
17
tbCKC
tbCKH
tbCKL
tbREQS
tbREQH
tbACKL
Clock pulse HIGH time
Clock pulse LOW time
Request set-up time
Request hold time
6
6
8
5
5
5
5
5
5
Delay from a rising clock
edge to ACK switching
—
—
—
—
NOTE:
2668 tbl 22
1. IDT72511 not available in military.
5.32
16
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to + 125°C)
Commercial
Military
Com'l & Mil.(4)
IDT72511L50
IDT72521L50
IDT72511L25
IDT72521L25
IDT72511L35
IDT72521L35
IDT72521L40
Timing
Figure
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
PORT B RETRANSMIT TIMING
tbDSBH
RER, REW, LDRER,
LDREW set-up and
recovery time
10
—
10
—
10
—
15
—
ns
9, 18
PROGRAMMABLE I/O TIMING
tPIOA
tPIOS
tPIOH
Programmable I/O
access time
—
8
20
—
—
—
10
10
25
—
—
—
10
10
25
—
—
—
15
15
30
—
—
ns
ns
ns
19
19
19
Programmable I/O set-
up time
Programmable I/O hold
time
8
BYPASS TIMING
t
BYA
BYD
Bypass access time
Bypass delay
—
—
15
18
10
—
—
—
15
20
15
—
—
—
15
25
20
—
—
—
15
30
20
—
ns
ns
ns
16
16
16
t
taBYDV
Bypass data valid time
from DS
A
(3)
tbBYDV
Bypass data valid time
from DS
3
—
3
—
3
—
3
—
ns
16
B
FLAG TIMING (1) (2)
t
t
t
t
t
REF
WEF
RFF
Read clock edge to
Empty Flag asserted
—
—
—
—
—
25
25
25
25
40
—
—
—
—
—
35
35
35
35
50
—
—
—
—
—
40
40
40
40
55
—
—
—
—
—
45
45
45
45
60
ns
ns
ns
ns
ns
14, 15, 20, 22
14, 15, 20, 22
14, 15, 21, 23
14, 15, 21, 23
20, 22
Write clock edge to
Empty Flag not asserted
Read clock edge to Full
Flag not asserted
WFF
RAEF
Write clock edge to Full
Flag asserted
Read clock edge to
Almost-Empty Flag
asserted
t
t
t
WAEF
RAFF
WAFF
Write clock edge to
Almost-Empty Flag not
asserted
—
—
—
40
40
40
—
—
—
50
50
50
—
—
—
55
55
55
—
—
—
60
60
60
ns
ns
ns
20, 22
21, 23
21, 23
2668 tbl 23
Read clock edge to
Almost-Full Flag not
asserted
Write clock edge to
Almost-Full Flag
asserted
NOTES:
1. Read and write are internal signals derived from DSA, R/WA, DSB, R/WB, RB, and WB.
2. Although the flags, Empty, Almost-Empty, Almost-Full, and Full Flags are internal flags, the timing given is for those assigned to external pins.
3. Values guaranteed by design, not currently tested.
4. IDT72511 not available in military.
5.32
17
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tRSC
tRS
RS
tRSR
tRSS
WB, RB
(or R/WB, DSB)
RER,
REW
LDRER,
LDREW
REQ
DSA
tRSR
tRSF
tRSF
FLGA,
FLGC
FLGB,
FLGD
2668 drw 10
Figure 9. Hardware Reset Timing
CSA
A0, A1
R/WA
DSA
ta
S
taH
2668 drw 11
Figure 10. Basic Port A Control Signal Timing (Applies to All Port A Timing)
5.32
18
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
R/WA
t
WPW
DSA
t
WRCOM
Opcode
DA8 - DA12
or
Operand
2668 drw 12
DA0 - DA12
taDS
taDH
Figure 11. Port A Command Timing (write).
WRITE
taWC
R/WA
taWPW
DSA
taS
taRR
taH
Input
DA0 - DA17
taDS
taDH
READ
R/WA
taRC
taRPW
DSA
taS
taRR
taH
Output
DA0 - DA17
taLZ
taA
taDV
taHZ
2668 drw 13
Figure 12. Read and Write Timing for Port A
5.32
19
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WRITE
tbWC
(R/WB)
WB
(or DSB)
tbWPW
tbWR
tbS
tbH
Input
DB0–DB8
tbDS
tbDH
NOTE:
1. RB = 1
READ
(R/WB)
tbRC
RB
(or DSB)
tbRPW
tbRR
tbH
tbS
Output
DB0–DB8
tbLZ
tbDV
tbA
tbHZ
2668 drw 14
NOTE:
1. WB = 1
Figure 13. Port B Read and Write Timing, Processor Interface Mode Only
5.32
20
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
A→B FIFO WRITE FLOW-THROUGH
taWPW
DSA
DA0 - DA17
DATA INPUTS
taDS
taDH
A→B
Full Flag(1)
tWFF
tRFF
RB (or DSB)
tbLZ
tbDV
DB0 - DB17
DATA OUT
tbA
tbHZ
NOTES:
1. Assume the flag pin is programmed active LOW.
2. R/WA = 0
B→A FIFO READ FLOW-THROUGH
taRPW
DSA
taLZ
taA
taDV
DATA OUTPUT
DA0 - DA17
taHZ
B→A
Empty Flag (1)
tWEF
tREF
WB (or DSB)
DB0 - DB17
DATA INPUT
tbDS
tbDH
2668 drw 15
NOTES:
1. Assume the flag pin is programmed active LOW.
2. R/WA = 1
Figure 14. Port A Read and Write Flow-Through Timing, Processor Interface Mode Only
5.32
21
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
A→B FIFO WRITE FLOW-THROUGH
DSA
taLZ
DA0–DA17
DATA OUT
tbA
taHZ
B→A
Full Flag(1)
-
tRFF
tWFF
RB = 1 (or R/WB = 0)
WB (or DSB)
tbWPW
DB0–DB8
DATA INPUT
NOTES:
tbDS
tbDH
1. Assume the flag pin is programmed active LOW.
2. R/WA = 1
A→B FIFO READ FLOW-THROUGH
DSA
DA0–DA17
DATA INPUT
taDS
taDH
A→B
(1)
Empty Flag
tWEF
tREF
WB = 1 (or R/WB = 1)
RB (or DSB)
taLZ
DB0–DB8
DATA OUT
tbA
tbRPW
tbDV
taHZ
2668 drw 16
NOTES:
1. Assume the flag pin is programmed active LOW.
2. R/WA = 0
Figure 15. Port B Read and Write Flow-Through Timing, Processor Interface Mode Only
5.32
22
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
B→A READ BYPASS
R/WA
taS
taH
DSA
taDV
taLZ
(1)
DA0–DA7,
DA16
BYTE 0
BYTE 1
BYTE 2
tBYA
taHZ
RB (or DSB)
tBYD
tBYD
(R/WB)
tBYD
tBYD
tBYD
(1)
DB0–DB8
NOTES:
BYTE 0
BYTE 1
BYTE 2
1. Once the bypass mode starts, any data change on Port B bus (Byte 0→Byte 1) will be passed to Port A bus.
2. WB = 1
A→B WRITE BYPASS
R/WA
taS
taH
DSA
tBYD
(1)
DA0–DA7,
BYTE 1
BYTE 0
BYTE 2
DA16
tBYD
WB (orDSB)
tBYD
tBYD
tBYD
tbBYDV
taBYDV
(R/WB)
tbLZ
(1)
BYTE 0
BYTE 1
DB0–DB8
BYTE 2
tBYA
tbHZ
NOTES:
1. Once the bypass mode starts, any data change on Port A bus (Byte 0→Byte 1) will be passed to Port B bus.
2. RB = 1
Figure 16. Bypass Path Timing, BiFIFO Must Be in Peripheral Interface Mode
5.32
23
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SINGLE WORD DMA TRANSFER
2 to 5 cycles
1 cycle
1 to 2 cycles
t
CKC
t
CKH
tCKL
CLK
REQ
t
REQS
t
REQH
ACK
WRITE
(R/WB)
t
ACKL
WB (orDSB)
taCKL
taCKL
Output
DB0-DB17
tbLZ
tb
tbDV
tbHZ
A
READ
(R/WB)
RB (orDSB)
t
ACKL
tACKL
Input
DB0-DB17
tbDS
tbDH
BLOCK DMA TRANSFER
1 to 2
1 to 2
cycles
cycles
2 to 5
2 to 5
cycles
cycles
CLK
REQ
ACK, R/W
B
RB
, W (orDSB)
B
2668 drw 18
Figure 17. Port B Read and Write DMA timing. Peripheral Interface Mode Only
5.32
24
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RB, WB
(or R/WB, DSB)
tbDSBH
tbWPW
tbDSBH
RER
REW
LDRER,
LDREW
2668 drw 19
Figure 18. Port B Reread and Rewrite Timing for Intelligent Reread/Rewrite
Port A → PIO WRITE
taWC
R/WA
DSA
taWPW
taWR
taS
taH
Input
DA0-DA5
taDS
taDH
Output
PIO0-PIO5
tPIOH
tPIOA
PIO → Port A READ
R/WA
taRC
DSA
taRPW
taRR
taH
taS
Output
DA0-DA5
taLZ
taDV
taA
taHZ
Input
PIO0-PIO5
tPIOH
tPIOS
2668 drw 20
Figure 19. Programmable I/O Timing
5.32
25
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Read
DSA
1
2
n + 1
Write
1
WB
(or R/WB = 0, DSB)
2
n + 1
tWEF
tREF
B→A Empty
Flag
tRAEF
tWAEF
B→A Almost-
Empty Flag
2668 drw 21
NOTES:
1. B→A FIFO is initially empty.
2. Assume the flag pins are programmed active LOW.
3. R/WA = 1.
Figure 20. Empty and Almost-Empty Flag Timing for B→A FIFO, (n = programmed offset)
Read
DSA
1
2
m + 1
WB
(or R/WB=1,
)
Write
1
2
m + 1
tWEF
tRAFF
(2)
B→A Almost-
Full Flag
tRFF
tWFF
(2)
B→A
Full Flag
2668 drw 22
NOTES:
1. B→A FIFO initially contains D – (M + 1) data words. D = 512 for IDT72511; D = 1024 for IDT72521.
2. Assume the flag pins are programmed active LOW.
3. R/WA = 1.
Figure 21. Full and Almost-Full Flag Timing for B→A FIFO, (m = programmed offset)
5.32
26
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Write
DSA
1
2
n + 1
RB
Read
(or R/WB=1, DSB)
1
2
n + 1
tWEF
tREF
A→B Empty(2)
Flag
tRAEF
tWAE
F
A→B Almost-(2)
Empty Flag
2668 drw 23
NOTES:
1. A→B FIFO is initially empty.
2. Assume the flag pins are programmed active LOW.
3. R/WA = 1.
Figure 22. Empty and Almost-Empty Flag Timing for A→B FIFO, (n = programmed offset)
Read
DSA
1
2
m + 1
WB
Write
1
(or R/WB=1, DSB)
2
m + 1
tWEF
tRAFF
(2)
B→A Almost-
Full Flag
tRFF
tWFF
(2)
B→A
Full Flag
2668 drw 24
NOTES:
1. B→A FIFO initially contains D – (M + 1) data words. D = 512 for IDT72511; D = 1024 for IDT72521.
2. Assume the flag pins are programmed active LOW.
3. R/WA = 1.
Figure 23. Full and Almost-Full Flag Timing for A→B FIFO, (m = programmed offset)
5.32
27
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXX
X
XXX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
G
J
68-pin PGA
68-pin PLCC
25
35
40
50
Commercial Only
Commercial Only
Military Only *
Access Time (tA)
in ns
Com'l & Mil. *
Low Power
L
72511 512 x 18 Parallel BiFIFO
72521 1024 x 18 Parallel BiFIFO
2668 drw 25
*
*
40 Military Only, IDT72521
50 Commercial and Military, IDT72511 available in commercial only
5.32
28
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明