IDT72605 [IDT]
CMOS SyncBiFIFOO 256 x 18 x 2 and 512 x 18 x 2; CMOS SyncBiFIFOO 256 ×18× 2和512 ×18× 2
| 型号： | IDT72605 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS SyncBiFIFOO 256 x 18 x 2 and 512 x 18 x 2 |
| 文件： | 总20页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
IDT72605
IDT72615
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Two independent FIFO memories for fully bidirectional
data transfers
• 256 x 18 x 2 organization (IDT 72605)
• 512 x 18 x 2 organization (IDT 72615)
• Synchronous interface for fast (20ns) read and write
cycle times
• Each data port has an independent clock and read/write
control
• Output enable is provided on each port as a three-state
control of the data bus
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Programmable flag offset can be set to any depth in the
FIFO
The IDT72605 and IDT72615 are very high-speed, low-
power bidirectional First-In, First-Out (FIFO) memories, with
synchronous interface for fast read and write cycle times. The
SyncBiFIFO
is a data buffer that can store or retrieve
information from two sources simultaneously. Two Dual-Port
FIFO memory arrays are contained in the SyncBiFIFO; one
data buffer for each direction.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Each Port has its own
independent clock. Data transfers to the I/O registers are
gated by the enable signals. The transfer direction for each
portiscontrolledindependentlybyaread/writesignal. Individ-
ual output enable signals control whether the SyncBiFIFO is
driving the data lines of a port or whether those data lines are
in a high-impedance state.
• The synchronous BiFIFO is packaged in a 64-pin TQFP
(Thin Quad Flatpack), 68-pin PGA and 68-pin PLCC
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
Bypass control allows data to be directly transferred from
input to output register in either direction.
The SyncBiFIFO has eight flags. The flag pins are full,
empty, almost-full, and almost-empty for both FIFO memo-
ries. The offset depths of the almost-full and almost-empty
flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT’s high-speed,
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
DA0-DA17
ENA
R/WA
HIGH
Z
CONTROL
OEA
INPUT REGISTER
OUTPUT REGISTER
MUX
CLKA
RESET
LOGIC
CSA
A2
RS
µP
A1
INTERFACE
A0
EFAB
PAEAB
PAFAB
FFAB
MEMORY
ARRAY
512 x 18
256 x 18
MEMORY
ARRAY
512 x 18
256 x 18
EFBA
FLAG
LOGIC
FLAG
LOGIC
PAEBA
PAFBA
FFBA
3
7
POWER
SUPPLY
MUX
VCC
GND
OUTPUT REGISTER
INPUT REGISTER
CLKB
HIGH
Z
CONTROL
OEB
R/WB
ENB
2704 drw 01
BYPB
DB0-DB17
SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
DECEMBER 1996
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
1996 Integrated Device Technology, Inc.
DSC-2704/5
5.18
1
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
11
D
B3
D
B4
D
B5
B6
D
D
B7
D
B9
D
B11
B12
D
D
B13 GND
B14 B15
V
CC
10
D
B1
DB2 GND
D
B8 GND
D
D
D
D
B16
B17
D
B10
09 RS
DB0
OEA
08 R/W
B
CLK
EN
B
PAEAB PAFAB
EFAB FFAB
07 OE
B
B
G68-1
06 GND BYP
B
05 PAEBA PAFBA
04 EFBA FFBA
A
A
2
0
VCC
A1
Pin 1 Designator
EN
A
CSA
03
02
01
D
D
A1
A2
D
D
D
A0
CLKA R/WA
A3 GND
D
A6
A7
D
D
A8 GND
D
A12
D
A14
DA16
DA17
D
D
A10
A11
A4
D
A5
D
A9
VCC
DA13 GND
DA15
A
B
C
D
E
F
H
J
K
L
G
2704 drw 02
PGA
Top View
9 8 7 6 5 4 3 2
686766656463 6261
1
DA16
DA17
CLK A
10
60
DA2
DA1
DA0
EFBA
FFBA
PAEBA
PAFBA
GND
BYPB
OEB
ENB
R/WB
CLKB
RS
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
R/WA
A
EN
CSA
A0
A1
A2
VCC
EFAB
AB
FF
PAEAB
AB
PAF
J68-1
OEA
DB17
DB16
DB0
DB1
DB2
2728293031323334353637383940414243
2704 drw 03
PLCC
Top View
5.18
2
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DA2
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DB3
2
DB4
DA3
DA4
DA5
DA6
DA7
DA8
DA9
3
GND
DB5
4
5
DB6
6
DB7
DB8
7
8
DB9
PN64-1
9
DB10
DB11
DB12
DB13
DB14
GND
DB15
DB16
GND
VCC
DA10
DA11
DA12
DA13
DA14
DA15
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2704 drw 04
TQFP
Top View
5.18
3
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
Name
I/O
Description
DA0-DA17 Data A
I/O Data inputs & outputs for the 18-bit Port A bus.
CSA
Chip Select A
I
I
Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH.
R/WA
Read/Write A
This pin controls the read or write direction of Port A. If R/WA is LOW, Data A input data is
written into Port A. If R/WA is HIGH, Data A output data is read from Port A. In bypass mode,
when R/WA is LOW, message is written into A→B output register. If R/WA is HIGH, message
is read from B→A output register.
CLKA
ENA
Clock A
I
I
I
CLKA is typically a free running clock. Data is read or written into Port A on the rising edge of
CLKA.
Enable A
When ENA is LOW, data can be read or written to Port A. When ENA is HIGH, no data
transfers occur.
OEA
Output Enable A
When R/WA is HIGH , Port A is an output bus and OEA controls the high-impedance state of
DA0-DA17. If OEA is HIGH, Port A is in a high-impedance state. If OEA is LOW while CSA is
LOW and R/WA is HIGH, Port A is in an active (low-impedance) state.
A0, A1, A2 Addresses
DB0-DB17 Data B
I
When CSA is asserted, A0, A1, A2 and R/WA are used to select one of six internal resources.
I/O Data inputs & outputs for the 18-bit Port B bus.
R/WB
Read/Write B
I
This pin controls the read or write direction of Port B. If R/WB is LOW, Data B input data is
written into Port B. If R/WB is HIGH, Data B output data is read from Port B. In bypass mode,
when R/WB is LOW, message is written into B→A output register. If R/WB is HIGH, message
is read from A→B output register.
CLKB
ENB
Clock B
I
I
I
Clock B is typically a free running clock. Data is read or written into Port B on the rising edge
of CLKB.
Enable B
When ENB is LOW, data can be read or written to Port B. When ENB is HIGH, no data
transfers occur.
OEB
Output Enable B
When R/WB is HIGH , Port B is an output bus and OEB controls the high-impedance state of
DB0-DB17. If OEB is HIGH, Port B is in a high-impedance state. If OEB is LOW while R/WB
is HIGH, Port B is in an active (low-impedance) state.
EFAB
A→B Empty Flag
O
O
O
O
When EFAB is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited.
When EFAB is HIGH, the FIFO is not empty. EFAB is synchronized to CLKB. In the bypass
mode, EFAB HIGH indicates that data DA0-DA17 is available for passing through. After the
data DB0-DB17 has been read, EFAB goes LOW.
PAEAB
PAFAB
FFAB
A→B
Programmable
Almost-Empty Flag
When PAEAB is LOW, the A→B FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into PAEAB Register. When PAEAB is HIGH, the
A→B FIFO contains more than offset in PAEAB Register. The default offset value for PAEAB
Register is 8. PAEAB is synchronized to CLKB.
A→B
Programmable
Almost-Full Flag
When PAFAB is LOW, the A→B FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into PAFAB Register. When PAFAB is HIGH,
the A→B FIFO contains less than or equal to the depth minus the offset in PAFAB Register.
The default offset value for PAFAB Register is 8. PAFAB is synchronized to CLKA.
A→B Full Flag
When FFAB is LOW, the A→B FIFO is full and further data writes into Port A are inhibited.
When FFAB is HIGH, the FIFO is not full. FFAB is synchronized to CLKA. In bypass mode,
FFAB tells Port A that a message is waiting in Port B’s output register. If FFAB is LOW, a
bypass message is in the register. If FFAB is HIGH, Port B has read the message and another
message can be written into Port A.
EFBA
B→A Empty Flag
O
O
O
When EFBA is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited.
When EFBA is HIGH, the FIFO is not empty. EFBA is synchronized to CLKA. In the bypass
mode, EFBA HIGH indicates that data DB0-DB17 is available for passing through. After the
data DA0-DA17 has been read, EFBA goes LOW on the following cycle.
PAEBA
PAFBA
B→A
Programmable
Almost-Empty Flag
When PAEBA is LOW, the B→A FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into PAEBA Register. When PAEBA is HIGH, the
B→A FIFO contains more than offset in PAEBA Register. The default offset value for PAEBA
Register is 8. PAEBA is synchronized to CLKA.
B→A
Programmable
Almost-Full Flag
When PAFBA is LOW, the B→A FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into PAFBA Register. When PAFBA is HIGH,
the B→A FIFO contains less than or equal to the depth minus the offset in PAFBA Register.
The default offset value for PAFBA Register is 8. PAFBA is synchronized to CLKB.
2704 tbl 01
5.18
4
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (Continued)
Symbol
Name
I/O
Description
FFBA
B→A Full Flag
O
When FFBA is LOW, the B→A FIFO is full and further data writes into Port B are inhibited.
When FFBA is HIGH, the FIFO is not full. FFBA is synchronized to CLKB. In bypass mode,
FFBA tells Port B that a message is waiting in Port A’s output register. If FFBA is LOW, a
bypass message is in the register. If FFBA is HIGH, Port A has read the message and another
message can be written into Port B.
BYPB
Port B Bypass
Flag
O
I
This flag informs Port B that the Synchronous BiFIFO is in bypass mode. When BYPB is
LOW, Port A has placed the FIFO into bypass mode. If BYPB is HIGH, the Synchronous
BiFIFO passes data into memory. BYPB is synchronized to CLKB.
RS
Reset
A LOW on this pin will perform a reset of all Synchronous BiFIFO functions.
VCC
GND
Power
Ground
There are three +5V power pins for the PLCC and PGA packages and two for the TQFP.
There are seven ground pins for the PLCC and PGA packages and four for the TQFP.
2704 tbl 02
RECOMMENDED DC
OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Com’l.
Mil.
Unit
Symbol
VCC
Parameter
Supply Voltage
Min. Typ. Max. Unit
VTERM Terminal Voltage
with Respect
–0.5 to +7.0 –0.5 to +7.0
V
4.5 5.0
5.5
0
V
V
V
V
GND
VIH
VIL(1)
Supply Voltage
0
0
to Ground
Input High Voltage
Input Low Voltage
2.0
—
—
—
—
0.8
TA
Operating
Temperature
0 to +70
–55 to +125 °C
NOTE:
2704 tbl 04
TBIAS
TSTG
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
1. 1.5V undershoots are allowed for 10ns once per cycle.
Storage
Temperature
IOUT
DC Output Current
50
50
mA
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
2704 tbl 03
Symbol
CIN(2)
Parameter
Conditions
VIN = 0V
Max. Unit
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
abovethoseindicatedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Input Capacitance
10
10
pF
COUT(1,2) Output Capacitance
NOTES:
1. With output deselected.
VOUT = 0V
pF
2704 tbl 05
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
IDT72615L
IDT72605L
Commercial
tCLK = 20, 25, 35, 50ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
(1)
IIL
Input Leakage Current (Any Input)
Output Leakage Current
–1
–10
2.4
—
—
—
—
—
—
1
µA
µA
V
(2)
IOL
10
VOH
VOL
Output Logic "1" Voltage IOUT = –2mA
Output Logic "0" Voltage IOUT = 8mA
Average VCC Power Supply Current
—
0.4
230
V
(3)
ICC
—
mA
2704 tbl 06
NOTES:
1. Measurements with 0.4V ≤ VIN ≤ VCC.
2. OEA, OEB ≥ VIH; 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open. Testing frequency f=20MHz
5.18
5
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
+5V
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.1KΩ
1.5V
1.5V
D.U.T.
See Figure 2
2704 tbl 07
680Ω
30pF*
2704 drw 05
or equivalent circuit
Figure 2. Output Load
* Includes jig and scope capacitances.
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V±10%, TA = 0°C to +70°C)
Commercial
72615L20
72605L20
72615L25
72605L25
72615L35
72605L35
72615L50
72605L50
Symbol
Parameter
Clock frequency
Min.
Max. Min. Max. Min. Max. Min.
Max. Unit
Timing Figures
fCLK
—
50
—
—
—
—
—
—
27
10
—
—
25
10
10
25
15
15
—
3
40
—
—
—
—
—
—
28
15
—
—
35
14
14
35
21
21
—
3
28
—
—
—
—
—
—
35
21
—
—
50
20
20
50
30
30
—
3
20 MHz
—
tCLK
tCLKH
tCLKL
tRS
Clock cycle time
20
8
—
—
—
—
—
—
50
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,5,6,7
Clock HIGH time
4,5,6,7,12,13,14,15
Clock LOW time
8
4,5,6,7,12,13,14,15
Reset pulse width
20
12
12
—
3
3
tRSS
tRSR
tRSF
tA
Reset set-up time
3
Reset recovery time
Reset to flags in intial state
Data access time
3
3
5,7,8,9,10,11
tCS
Control signal set-up time(1)
6
6
8
10
4,5,6,7,8,9,10,11,
12, 13,14,15
tCH
Control signal hold time(1)
1
—
1
—
1
—
1
—
ns
4,5,6,7,10,11,12,
13, 14,15
tDS
tDH
tOE
Data set-up time
Data hold time
6
1
3
—
—
10
6
1
3
—
—
13
8
1
3
—
—
20
10
1
—
—
28
ns
ns
ns
4,6,8,9,10,11
4,6
Output Enable LOW to
output data valid(2)
3
5,7,8,9,10,11
tOLZ
tOHZ
Output Enable LOW to data
bus at Low-Z(2)
0
3
—
0
3
—
0
3
—
0
3
—
ns
ns
5,7,8,9,10,11
5,7,10,11
Output Enable HIGH to data
bus at High-Z(2)
10
13
20
28
tFF
tEF
Clock to Full Flag time
—
—
—
10
10
12
—
—
—
15
15
15
—
—
—
21
21
21
—
—
—
30
30
30
ns
ns
ns
4,6,10,11
5,7,8,9,10,11
12,14
Clock to Empty Flag time
tPAE
Clock to Programmable
Almost Empty Flag time
tPAF
tSKEW1
tSKEW2
NOTES:
Clock to Programmable
Almost Full Flag time
—
10
17
12
—
—
—
12
19
15
—
—
—
17
25
21
—
—
—
20
34
30
—
—
ns
ns
ns
13,15
Skew between CLKA & CLKB
for Empty/Full Flags(2)
4,5,6,7,8,9,10,11
4, 7,12,13,14,15
Skew between CLKA & CLKB
for Programmable Flags(2)
2704 tbl 08
1. Control signals refer to CSA, R/WA, ENA, A2, A1, A0, R/WB, ENB.
2. Minimum values are guaranteed by design.
5.18
6
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
RESET
IDTs SyncBiFIFO is versatile for both multiprocessor and
Reset is accomplished whenever the Reset (RS) input is
peripheral applications. Data can be stored or retrieved from taken to a LOW state with CSA, ENA and ENB HIGH. During
two sources simultaneously. reset, both internal read and write pointers are set to the first
The SyncBiFIFO has registers on all inputs and outputs. location. A reset is required after power up before a write
Data is only transferred into the I/O registers on clock edges, operation can take place. The A→B and B→A FIFO Empty
hence the interfaces are synchronous. Two Dual-Port FIFO Flags (EFAB, EFBA) and Programmable Almost Empty Flags
memory arrays are contained in the SyncBiFIFO; one data (PAEAB, PAEBA) will be set to LOW after tRSF. The A→B and
buffer for each direction. Each port has its own independent B→AFIFOFullFlags(FFAB, FFBA)andProgrammableAlmost
clock. Data transfers to the I/O registers are gated by the Full Flags (PAFAB, PAFBA) will be set to HIGH after tRSF. After
enable signals. The transfer direction for each port is con- the reset, the offsets of the Almost-Empty Flags and Almost-
trolled independently by a read/write signal. Individual output Full Flags for the A→B and B→A FIFO offset default to 8.
enable signals control whether the SyncBiFIFO is driving the
data lines of a port or whether those data lines are in a high-
impedance state. The processor connected to Port A of the
PORT A INTERFACE
The SyncBiFIFO is straightforward to use in micro-pro-
BiFIFO can send or receive messages directly to the Port B
cessor-based systems because each port has a standard
device using the 18-bit bypass path.
microprocessor control set. Port A interfaces with micropro-
cessorthroughthethreeaddresspins(A2-A0)andaChipSelect
TheSyncBiFIFOcanbeusedinmultiplesof18-bits.Ina36-
to 36-bit configuration, two SyncBiFIFOs operate in parallel.
CSA pins. WhenCSA isasserted,A2,A1,A0 andR/WA areused
Both devices are programmed simultaneously, 18 data bits to
to select one of six internal resources (Table 1).
each device. This configuration can be extended to wider bus
With A2=0 and A1=0, A0 determines whether data can be
widths (54- to 54-bits, 72- to 72-bits, etc.) by adding more
read out of output register or be written into the FIFO (A0=0),
SyncBiFIFOs to the configuration. Figure 1 shows multiple
or the data can pass through the FIFO through the bypass
SyncBiFIFOs configured for multiprocessor communication.
path (A0=1).
The microprocessor or microcontroller connected to Port A
controls all operations of the SyncBiFIFO. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B interfaces with a second processor. The Port B control
With A2=1, four programmable flags (two A→B FIFO pro-
grammable flags and two B→A FIFO programmable flags)
can be selected: the A→B FIFO Almost-Empty Flag Offset
(A1=0,A0=0),A→BFIFOAlmost-FullFlagOffset(A1=0,A0=1),
pins are inputs driven by the second processor.
B→AFIFOAlmost-EmptyFlagOffset(A1=1,A0=0),B→AFIFO
Almost-Full Flag Offset (A1=1, A0=1).
Port A is disabled when CSA is deasserted and data A is in
high-impedance state.
IDT
SYNCBIFIFO
DATA A
CLK
DATA B
CLK
CLK
A
B
CLK
CONTROL A CONTROL B
MICROPROCESSOR
A
MICROPROCESSOR
B
DATA
DATA
IDT
SYNCBIFIFO
CONTROL
LOGIC
CONTROL
LOGIC
ADDR, I/0
ADDR, I/0
DATA A
CLK
CONTROL A CONTROL B
DATA B
A
CLK
B
RAM A
RAM B
SYSTEM
CLOCK A
SYSTEM
CLOCK B
2704 drw 06
NOTES:
1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.
2. Control A Consists of R/WA, ENA, OEA, CSA, A2, A1, A0. Control B consists of R/WB, ENB, OEB.
Figure 1. 36- to 36-bit Processor Interface Configuration.
5.18
7
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
Data A
I/O
A
CS
R/
A
W
A
EN
A
OE
Port A Operation
0
0
0
0
I
Data A is written on CLKA ≠. This write cycle immediately following
low-impedance cycle is prohibited. Note that even though OEA = 0, a
LOW logic level on R/WA, once qualified by a rising edge on CLKA, will
put Data A into a high-impedance state.
0
0
0
0
0
1
0
1
0
1
X
0
I
I
Data A is written on CLKA ≠
Data A is ignored
Data is read(1) from RAM array to output register on CLKA ≠,
O
Data A is low-impedance
0
1
0
1
O
Data is read(1) from RAM array to output register on CLKA ≠,
Data A is high-impedance
0
1
1
0
1
1
1
0
1
O
O
I
Output register does not change(2), Data A is low-impedance
Output register does not change(2), Data A is high-impedance
Data A is ignored(3)
0
1
1
X
X
X
X
O
Data A is high-impedance(3)
2704 tbl 09
NOTES:
1. When A2A1A0 = 000, the next B→A FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass path is
selected and bypass data from the Port B input register is read from the Port A output register. If A2A1A00 = 1XX, a flag offset register is selected
and its offset is read out through Port A output register.
2. Regardless of the condition of A2A1A0, the data in the Port A output register does not change and the B→A read pointer does not advance.
3. If CSA# is HIGH, then BYPB is HIGH. No bypass occur under this condition.
Table 1. Port A Operation Control Signals
BYPASS PATH
data is read into the Port B output register. OEB still controls
whetherPortBisinahigh-impedancestate. WhenOEBisLOW,
theoutputregisterdataappearsatDB0-DB17. EFABgoesLOW
following theCLKB rising edge for this read. FFAB goes HIGH
on the next CLKA rising edge, letting Port A know that another
word can be written through the bypass path.
BypassdatatransfersfromPortBtoPortAworkinasimilar
manner with EFBA and FFBA indicating the Port A output
register state.
When the Port A address changes from bypass mode
(A2A1A0=001)toFIFOmode(A2A1A0=000)ontherisingedge
of CLKA, the data held in the Port B output register may be
overwritten. Unless Port A monitors the BYPB pin and waits
forPortBtoclockoutthelastbypassword, datafromtheA→B
FIFOwilloverwritedatainthePortBoutputregister. BYPB will
go HIGH on the rising edge of CLKB signifying that Port B has
finished its last bypass operation. Port B must read any
bypass data in the output register on this last CLKB clock or it
is lost and the SyncBiFIFO returns to FIFO operations. It is
especially important to monitor BYPB when CLKB is much
slower than CLKA to avoid this condition. BYPB will also go
HIGH after CSA is brought HIGH; in this manner the Port B
bypass data may also be lost.
The bypass paths provide direct communication between
Port A and Port B. There are two full 18-bit bypass paths, one
in each direction. During a bypass operation, data is passed
directly between the input and output registers, and the FIFO
memory is undisturbed.
Port A initiates and terminates all bypass operations. The
bypass flag, BYPB, is asserted to inform Port B that a bypass
operation is beginning. The bypass flag state is controlled by
the Port A controls, although the BYPB signal is synchronized
to CLKB. So, BYPB is asserted on the next rising edge ofCLKB
when A2A1A0=001and CSA is LOW. When Port A returns to
normal FIFO mode (A2A1A0=000 or CSA is HIGH), BYPB is
deasserted on the next CLKB rising edge.
Once the SyncBiFIFO is in bypass mode, all data transfers
arecontrolledbythestandardPortA(R/WA, CLKA, ENA, OEA)
and Port B (R/WB, CLKB, ENB, OEB) interface pins. Each
bypass path can be considered as a one word deep FIFO.
Data is held in each input register until it is read. Since the
controls of each port operate independently, Port A can be
readingbypassdataatthesametimePortBisreadingbypass
data.
When R/WA and ENA is LOW, data on pins DA0-DA17 is
written into Port A input register. Following the rising edge of
CLKA for this write, the A→B Full Flag (FFAB) goes LOW.
Subsequent writes into Port A are blocked by internal logic
until FFAB goes HIGH again. On the next CLKB rising edge,
the A→B Empty Flag (EFAB) goes HIGH indicating to Port B
that data is available. Once R/WB is HIGH and ENB is LOW,
Since the Port A processor controls CSA and the bypass
mode,thisscenariocanbehandledforB→Abypassdata. The
Port A processor must be set up to read the last bypass word
before leaving bypass mode.
5.18
8
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLAGS
A
A2
0
A1
0
A0
0
Read
Write
CS
0
0
0
B→A FIFO A→B FIFO
TheIDTSyncBiFIFOhaseightflags:four flagsforA→BFIFO
(EFAB, PAEAB, PAFAB, FFAB), and four flags for B→A FIFO
(EFBA, PAEBA, PAFBA, FFBA). The Empty and Full flags are
fixed, while the Almost Empty and Almost Full offsets can be
set to any depth through the Flag Offset Registers (see Table
3). The flags are asserted at the depths shown in the Flag
Truth Table (Table 4). After reset, the programmable flag
offsets are set to 8. This means the Almost Empty flags are
asserted at Empty +8 words deep, and the Almost Full flags
are asserted at Full -8 words deep.
The PAEAB is synchronized to CLKB, while PAEAB is syn-
chronizedtoCLKA;andPAEBA issynchronizedtoCLKA, while
PAEBA is synchronized toCLKB. If the minimum time (tSKEW2)
between a rising CLKB and a rising CLKA is met, the flag will
change state on the current clock; otherwise, the flag may not
change state until the next clock rising edge. For the specific
flag timings, refer to Figures 12-15.
0
0
1
18-bit Bypass Path
1
0
0
A→B FIFO Almost-Empty
Flag Offset
0
0
0
1
1
1
1
X
0
1
1
X
1
0
1
X
A→B FIFO Almost-Full
Flag Offset
B→A FIFO Almost-Empty
Flag Offset
B→A FIFO Almost-Full
Flag Offset
Port A Disabled
2704 tbl 10
Table 2. Accessing Port A Resources Using
A, A2, A1, and A0.
CS
PORT A CONTROL SIGNALS
The Port A control signals pins dictate the various opera-
tions shown in Table 2. Port A is accessed whenCSA is LOW,
and is inactive if CSA is HIGH. R/WA and ENA lines determine
whenDataAcanbewrittenorread. IfR/WA andENAareLOW,
PORT B CONTROL SIGNALS
ThePortBcontrolsignalpinsdictatethevariousoperations
dataiswrittenintoinputregisterontheLOW-to-HIGHtransition shown in Table 5. Port B is independent of CSA. R/WB and
of CLKA. If R/WA is HIGH and OEA is LOW, data comes out ENB lines determine when Data can be written or read in Port
of bus and is read from output register into three-state buffer. B. IfR/WB andENB areLOW, dataiswrittenintoinputregister,
Refer to pin descriptions for more information.
and on LOW-to-HIGH transition of CLKB data is written into
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
8
8
8
8
7
6
5
4
3
2
1
0
0
0
PAEAB Register
PAFAB Register
PAEBA Register
X
A→B FIFO Almost-Empty Flag Offset
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
7
7
6
5
4
3
2
1
1
X
A→B FIFO Almost-Full Flag Offset
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
6
5
4
3
2
X
B→A FIFO Almost-Empty Flag Offset
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
7
6
5
4
3
2
1
0
PAFBA Register
X
B→A FIFO Almost-Full Flag Offset
2704 tbl 11
NOTE:
1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.
Table 3. Flag Offset Register Format.
Number of Words
in FIFO
From
To
EF
PAE
LOW
LOW
HIGH
HIGH
HIGH
PAF
HIGH
HIGH
HIGH
LOW
LOW
FF
0
0
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
1
n
D-(m+1)
D-1
n+1
D-m
D
D
NOTES:
2704 tbl 12
n = Programmable Empty Offset (PAEAB Register or PAEBA Register)
m = Programmable Full Offset (PAFAB Register or PAFBA Register)
D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)
Table 4. Internal Flag Truth Table.
5.18
9
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
inputregisterandtheFIFOmemory. IfR/WB isHIGHandOEB
isLOW, datacomesoutofbusandisreadfromoutputregister
into three-state buffer. In bypass mode, if R/WB is LOW,
bypass messages are transferred into B→A output register. If
R/WA is HIGH, bypass messages are transferred into A→B
outputregister. Refertopindescriptionsformoreinformation.
Data B
R/
B
W
B
EN
B
OE
I/O
Port B Operation
0
0
0
I
Data B is written on CLKB ↑. This write cycle immediately following output low-
impedance cycle is prohibited. Note that even though OEB = 0, a LOW logic level on
R/WB, once qualified by a rising edge on CLKB, will put Data B into a high-impedance
state.
0
0
1
0
1
0
1
X
0
I
I
Data B is written on CLKB ↑.
Data B is ignored
O
Data is read(1) from RAM array to output register on CLKB ≠, Data B is LOW
impedance
1
0
1
O
Data is read(1) from RAM array to output register on CLKB ≠, Data B is HIGH
impedance
1
1
1
1
0
1
O
O
Output register does not change(2), Data B is low-impedance
Output register does not change(2), Data B is high-impedance
2704 tbl 13
NOTES:
1. When A2A1A0 = 000 or 1XX, the next A→B FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass
path is selected and bypass data is read from the Port B output register.
2. Regardless of the condition of A2A1A0, the data in the Port B output register does not change and the A→B read pointer does not advance.
Table 5. Port B Operation Control Signals.
5.18
10
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
tRS
RS
tRSF
EFAB,
PAEAB,
EFBA,
PAEBA
tRSF
EFAB,
PAEAB,
EFBA,
PAEBA
tRSS
tRSR
CSA,
ENA,
EN B
2704 drw 07
Figure 3. Reset Timing
tCLK
tCLKH
tCLKL
CLKA
A0 , A1, A2,
R/WA
CSA
tCS
tCH
NO OPERATION
ENA
tFF
tFF
FFAB
DA0-DA17
CLKB
tDS
tDH
tSKEW1
DATA IN VALID
READ
NO READ
OPERATION
2704 drw 08
Figure 4. Port A (A→B) Write Timing
5.18
11
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKA
A0, A1, A2 ,
R/WA
CSA
tCS
tCH
tEF
tA
NO OPERATION
ENA
EFBA
tEF
DA0-DA17
VALID DATA
tOHZ
tOLZ
tOE
OEA
tSKEW1
CLKB
NO WRITE
WRITE
2704 drw 09
Figure 5. Port A (B→A) Read Timing
tCLK
tCLKH
tCLKL
CLKB
R/WB
tCS
tCH
NO OPERATION
ENB
tFF
tFF
FFBA
tDS
tDH
DB0-DB17
CLKA
tSKEW1
DATA IN VALID
READ
NO READ
OPERATION
2704 drw 10
Figure 6. Port B (B→A) Write Timing
5.18
12
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
R/WB
tCS
tCH
tEF
tA
NO OPERATION
ENB
EFAB
tEF
DB0-DB17
VALID DATA
tOHZ
tOLZ
tOE
OEB
tSKEW1
CLKA
NO WRITE
OPERATION
WRITE
2704 drw 11
Figure 7. Port B (A→B) Read Timing
5.18
13
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
A0, A1, A2 ,
R/WA
tCS
CSA , EN
A
tDS
DA0-DA17
D0 (First valid write)
D1
D2
D3
tFRL
(1)
tSKEW1
CLKB
R/WB
ENB
tCS
tEF
EFAB
tA
tA
DB0-DB17
D0
D1
tOLZ
tOE
OEB
2704 drw 12
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing applies only at the Empty Boundary (EF = LOW).
Figure 8. A→B First Data Word Latency after Reset for Simultaneous Read and Write
5.18
14
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
CLK
R/W
EN
B
B
B
t
CS
t
DS
DB0-DB17
D0
(First valid write)
D1
D2
D3
tFRL
tSKEW1
(1)
CLK
A
A0, A1 , A2,
R/WA
tCS
CSA , EN
A
t
EF
EFBA
t
A
tA
DA0-DA17
D0
D1
t
OLZ
t
OE
OE
A
2704 drw 13
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundary (EF = LOW).
Figure 9. B→A First Data Word Latency after Reset for Simultaneous Read and Write
5.18
15
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
A0, A1, A2 ,
R/WA
tCS
A2, A1 , A0 , = 001
tCH
CSA
tCS
tCH
ENA
tFF
tFF
tFF
BYPASS FLAG
FIFO FLAG
FFAB
tDS
DA0-DA17
DATA INPUT
tSKEW1
tSKEW1
tSKEW1
CLKB
R/WB
ENB
tCS
tEF
tEF
tEF
FIFO FLAG
BYPASS FLAG
FIFO FLAG
EFAB
BYPB
tA
DB0-DB17
DATA OUTPUT
tOLZ
tOE
tOHZ
OEB
2704 drw 14
NOTES:
1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA LOW-to-HIGH transition.
2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for
the next bypass operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be
forced back to FIFO mode.
Figure 10. A→B Bypass Timing
5.18
16
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
CLK
R/W
EN
B
B
B
tCS
tCH
FIFO FLAG
tFF
t
FF
t
FF
t
FF
FFBA
BYPASS FLAG
BYP
B
t
DS
DATA INPUT
D
B0-DB17
tSKEW1
tSKEW1
tSKEW1
tSKEW1
CLK
A
tCS
tCS
A
2
, A1 , A0 , = 001
A0
, A
1
, A2,
tCS
CS
A
A
A
R/W
EN
tCS
t
EF
tEF
tEF
tEF
FIFO FLAG
BYPASS FLAG
FIFO FLAG
EFBA
tA
DATA OUTPUT
D
A0-DA17
tOLZ
t
OE
tOHZ
OE
A
2704 drw 15
NOTES:
1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA going LOW-to-HIGH.
2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for
the next bypass operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be
forced back to FIFO mode.
Figure 11. B→A Bypass Timing
5.18
17
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
tCLKH
tCLKL
tCS
CLKA
tCH
ENA
(R/WA = 0)
n+1 words in FIFO
WRITE
n words in FIFO
PAEAB
CLKB
(1)
tSKEW2
tPAE
tPAE
(2)
tCS
tCH
ENA
(R/WB = 1)
2704 drw 16
READ
NOTES:
1. tSKEW2 the minimum time between a rising CLKA edge and a rising CLKB edge for PAEAB to change during that clock cycle. If the time between the
rising edge of CLKA and the rising edge of CLKB is less than tSKEW, then PAEAB may not go HIGH until the next CLKB rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes LOW.
Figure 12. A→B Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
tCS
(2)
CLKA
tCH
ENA
(R/W A = 0)
WRITE
Full - (m+1) words in FIFO
Full - m words in FIFO
PAFAB
CLKB
tPAF
tPAF
tCH
tCS
ENB
(R/W B = 1)
2704 drw 17
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFAB to change during that clock cycle. If the time between the
rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAFAB may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 13. A→B Programmable Almost-Full Flag Timing
5.18
18
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
t
CLKH
tCLKL
CLK
B
B
t
CS
tCH
EN
(R/W
A = 0)
WRITE
n words in FIFO
n+1 words in FIFO
PAEBA
(1)
tSKEW2
tPAE
tPAE
(2)
CLK
EN
A
A
t
CS
tCH
2704 drw 18
(R/WA = 1)
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAEBA to change during that clock cycle. If the time between the
rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAEBA may not go HIGH until the next CLKA rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
Figure 14. B→A Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
tCS
(2)
CLKB
tCH
ENB
(R/WA = 0)
WRITE
Full - (m+1) words in FIFO
Full - m words in FIFO
PAFBA
CLKA
(1)
tPAF
tSKEW2
tPAF
tCS
tCH
ENA
(R/WA = 1)
READ
2704 drw 19
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFBA to change during that clock cycle. If the time between the
rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAFBA may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 15. B→A Programmable Almost-Full Flag Timing
5.18
19
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXXX
Device Type Power Speed Package Process/
Temperature
Range
X
XX
X
X
BLANK Commercial (0°C to +70°C)
G
J
PF
68-pin PGA
68-pin PLCC
64-pin TQFP
20
25
35
50
Clock Cycle Time (t CLK) in ns
L
Low Power
72605
72615
256 x 18 Parallel Synchronous Bidirectional FIFO
512 x 18 Parallel Synchronous Bidirectional FIFO
2704 drw 20
5.18
20
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