IDT72615L20JG8 [IDT]
FIFO, 512X18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68;型号: | IDT72615L20JG8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | FIFO, 512X18, 10ns, Synchronous, CMOS, PQCC68, PLASTIC, LCC-68 先进先出芯片 |
文件: | 总17页 (文件大小:169K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CMOS SyncBiFIFOTM
256 x 18 x 2
512 x 18 x 2
IDT72605
IDT72615
readandwritecycletimes.TheSyncBiFIFO™is adatabufferthatcanstore
orretrieveinformationfromtwosourcessimultaneously.TwoDual-PortFIFO
memory arrays are contained in the SyncBiFIFO; one data buffer for each
direction.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. EachPorthasitsownindependentclock.Datatransferstothe
I/Oregisters aregatedbytheenablesignals.Thetransferdirectionforeach
portiscontrolledindependentlybyaread/writesignal. Individualoutputenable
signals control whether the SyncBiFIFO is driving the data lines of a port or
whetherthosedatalinesareinahigh-impedancestate.
FEATURES:
• Two independent FIFO memories for fully bidirectional data
transfers
• 256 x 18 x 2 organization (IDT72605)
• 512 x 18 x 2 organization (IDT72615)
• Synchronous interface for fast (20ns) read and write cycle times
• Each data port has an independent clock and read/write control
• Output enable is provided on each port as a three-state control
of the data bus
• Built-in bypass path for direct data transfer between two ports
• Two fixed flags, Empty and Full, for both the A-to-B and the B-
to-A FIFO
• Programmable flag offset can be set to any depth in the FIFO
• The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin
Quad Flatpack) and 68-pin PLCC
Bypass controlallows data tobe directlytransferredfrominputtooutput
registerineitherdirection.
TheSyncBiFIFOhaseightflags.TheflagpinsareFull,Empty,Almost-Full,
andAlmost-EmptyforbothFIFOmemories.TheoffsetdepthsoftheAlmost-Full
andAlmost-Emptyflagscanbeprogrammedtoanylocation.
TheSyncBiFIFOisfabricatedusingIDT’shigh-speed,submicronCMOS
technology.
• Industrial temperature range (–40°C to +85°C)
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-power bidirec-
tionalFirst-In,First-Out(FIFO)memories,withsynchronousinterfaceforfast
FUNCTIONAL BLOCK DIAGRAM
DA0-DA17
EN
A
R/WA
HIGH
Z
CONTROL
OEA
INPUT REGISTER
OUTPUT REGISTER
RESET
CLK
A
CS
A
A
A2
RS
LOGIC
µP
MUX
A1
0
INTERFACE
EFAB
PAEAB
PAFAB
FFAB
MEMORY
MEMORY
ARRAY
512 x 18
256 x 18
EFBA
FLAG
LOGIC
FLAG
LOGIC
ARRAY
512 x 18
256 x 18
PAEBA
PAFBA
FFBA
3
7
POWER
SUPPLY
V
GND
CC
MUX
OUTPUT REGISTER
INPUT REGISTER
CLKB
HIGH
Z
CONTROL
OE
R/W
EN
B
B
B
2704 drw 01
BYPB
DB0-DB17
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.TheSyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
APRIL 2003
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2704/8
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATIONS
9 8 7 6 5 4 3 2 68 67 66 6564 63 62 61
1
D
C
CLK
R/W
EN
CS
A16
A17
D
D
D
EFBA
FFBA
PAEBA
PAFBA
GND
BYP
OE
EN
R/W
CLK
RS
A2
A1
A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A
A
A
A
A0
A1
A2
CC
B
B
V
EFAB
FFAB
PAEAB
PAFAB
B
B
B
OE
A
D
D
D
B0
D
D
B17
B16
B1
B2
2728293031323334353637383940414243
2704 drw 02
PLCC (J68-1, order code: J)
TOP VIEW
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D
D
GND
B3
B4
D
D
D
D
D
D
D
D
A2
A3
A4
A5
A6
A7
A8
A9
D
D
D
D
D
D
D
D
D
D
B5
B6
B7
B8
B9
9
B10
B11
B12
B13
B14
GND
VCC
10
11
12
13
14
15
16
DA10
DA11
DA12
DA13
DA14
DA15
GND
DB15
DB16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2704 drw 03
TQFP (PN64-1, order code: PF)
TOP VIEW
2
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
PINDESCRIPTION
Symbol
Name
I/O
Description
DA0-DA17 Data A
I/O Data inputs &outputs for the 18-bitPortA bus.
CSA
R/WA
Chip Select A
I
I
Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH.
This pin controls the read or write direction of Port A. If R/W is LOW, Data A input data is written into Port A. If R/W
Data A output data is read from Port A. In bypass mode, when R/W is LOW, message is written into A B output register. If
R/W is HIGH, message is read from B A output register.
CLKA is typically a free running clock. Data is read or written into Port A on the rising edge of CLKA.
When EN is LOW, data can be read or written to Port A. When EN is HIGH, no data transfers occur.
Read/WriteA
A
A is HIGH,
A
→
A
→
CLKA
ENA
OEA
Clock A
I
I
I
Enable A
A
A
Output Enable A
When R/WA is HIGH, Port A is an output bus and OEA controls the high-impedance state of DA0-DA17. If OEA is HIGH, Port A is
in a high-impedance state. If OEA is LOW while CSA is LOW and R/WA is HIGH, Port A is in an active (low-impedance) state.
A0, A1, A2 Addresses
DB0-DB17 Data B
I
When CSA is asserted, A0, A1, A2 and R/WA are used to select one of six internal resources.
I/O Datainputs&outputsforthe18-bitPortBbus.
R/WB
Read/WriteB
I
This pin controls the read or write direction of Port B. If R/W
Data B output data is read from Port B. In bypass mode, when R/W
R/W is HIGH, message is read from A B output register.
Clock B is typically a free running clock. Data is read or written into Port B on the rising edge of CLK
When EN is LOW, data can be read or written to Port B. When EN is HIGH, no data transfers occur.
B
is LOW, Data B input data is written into Port B. If R/W
B is HIGH,
B
is LOW, message is written into B A output register. If
→
B
→
CLKB
ENB
OEB
Clock B
I
I
I
B.
Enable B
B
B
Output Enable B
When R/WB is HIGH, Port B is an output bus and OEB controls the high-impedance state of DB0-DB17. If OEB is HIGH, Port B is
in a high-impedance state. If OEB is LOW while R/WB is HIGH, Port B is in an active (low-impedance) state.
EFAB
A→B Empty
O
O
When EFAB is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited. When EFAB is HIGH, the FIFO is
not empty. EFAB is synchronized to CLKB. In the bypass mode, EFAB HIGH indicates that data DA0-DA17 is available for passing
through.AfterthedataDB0-DB17hasbeenread,EFABgoesLOW.
When PAEAB is LOW, the A→B FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset
programmed into PAEAB Register. When PAEAB is HIGH, the A→B FIFO contains more than offset in PAEAB Register. The
default offset value for PAEAB Register is 8. PAEAB is synchronized to CLKB.
Flag
PAEAB
A→B
Programmable
Almost-Empty
Flag
PAFAB
FFAB
A→B
O
O
WhenPAFAB is LOW, the A→BFIFOis almost-full. Analmost-fullFIFOcontains greaterthanthe FIFOdepthminus the offset
programmed into PAFAB Register. WhenPAFAB is HIGH, the A→B FIFO contains less than or equal to the depth minus the
offset inPAFAB Register. The default offset value for PAFAB Register is 8. PAFAB is synchronized to CLKA.
Programmable
Almost-Full
Flag
A→B Full Flag
When FFAB is LOW, the A
→B FIFO is full and further data writes into Port A are inhibited. When FFAB is HIGH, the FIFO is not
full. FFAB is synchronized to CLK
A
. In bypass mode, FFAB tells Port A that a message is waiting in Port B’s output register. If
FFAB is LOW, a bypass message is in the register. If FFAB is HIGH, Port B has read the message and another message can be
written into Port A.
EFBA
B→A Empty
O
O
When EFBA is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited. When EFBA is HIGH, the FIFO
is not empty. EFBA is synchronized to CLKA. In the bypass mode, EFBA HIGH indicates that data DB0-DB17 is available for
passingthrough.AfterthedataDA0-DA17 hasbeenread,EFBA goesLOWonthefollowingcycle.
When PAEBA is LOW, the B→A FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset
programmed into PAEBA Register. When PAEBA is HIGH, the B→A FIFO contains more than offset in PAEBA Register. The
default offset value for PAEBA Register is 8. PAEBA is synchronized to CLKA.
Flag
PAEBA
B→A
Programmable
Almost-Empty
Flag
PAFBA
FFBA
B→A
O
O
WhenPAFBA is LOW, the B→A FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset
programmed into PAFBA Register. When PAFBA is HIGH, the B→A FIFO contains less than or equal to the depth minus the
offset inPAFBA Register. The default offset value for PAFBA Register is 8. PAFBA is synchronized to CLKB.
Programmable
Almost-Full
Flag
B→A Full Flag
When FFBA is LOW, the B
→A FIFO is full and further data writes into Port B are inhibited. When FFBA is HIGH, the FIFO is
not full. FFBA is synchronized to CLK
B
. In bypass mode, FFBA tells Port B that a message is waiting in Port A’s output register. If
FFBA is LOW, a bypass message is in the register. If FFBA is HIGH, Port A has read the message and another message can be
written into Port B.
BYPB
Port B Bypass
Flag
O
I
This flag informs Port B that the synchronous BiFIFO is in bypass mode. When BYP
B
is LOW, Port A has placed the FIFO into
is synchronized to CLK
bypass mode. If BYP is HIGH, the synchronous BiFIFO passes data into memory. BYP
B
B
B.
RS
VCC
Reset
A LOW on this pin will perform a reset of all synchronous BiFIFO functions.
There are three +5V power pins for the PLCC and two for the TQFP.
There are seven groundpins forthe PLCCandfourforthe TQFP.
Power
Ground
GND
3
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol
Rating
Industrial
Unit
VTERM
TerminalVoltagewith
RespecttoGround
–0.5to+7.0
V
SYMBOL
VCC
PARAMETER
SupplyVoltage
MIN. TYP. MAX. UNIT
4.5
0
5.0
0
5.5
0
V
V
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55to+125
–50to+50
°C
GND
VIH
SupplyVoltage
mA
InputHighVoltage
InputLowVoltage
OperatingTemperature
2.0
—
-40
—
—
—
—
0.8
85
V
NOTE:
(1)
VIL
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TA
°C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)
IDT72615L
IDT72605L
Industrial
tCLK = 20, 25, 35, 50ns
Symbol
Parameter
Min.
–1
Typ.
—
Max.
1
Unit
(1)
ILI
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
µ A
µ A
V
(2)
ILO
–10
2.4
—
—
10
VOH
VOL
Output Logic "1" Voltage IOUT = –2mA
Output Logic "0" Voltage IOUT = 8mA
Active Power Supply Current
—
—
0.4
230
—
V
(3)
ICC
—
—
mA
NOTES:
1. Measurements with 0.4V ≤ VIN ≤ VCC.
2. OEA, OEB ≥ VIH; 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0). Testing frequency f=20MHz.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter
InputCapacitance
OutputCapacitance
Conditions
Max. Unit
(2)
CIN
VIN = 0V
10
10
pF
pF
(1,2)
COUT
VOUT = 0V
NOTES:
1. With output deselected.
2. Characterized values, not currently tested.
4
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
+5V
ACTESTCONDITIONS
In Pulse Levels
GND to 3.0V
3ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1.1KΩ
1.5V
D.U.T.
1.5V
30pF*
SeeFigure2
680Ω
2704 drw 04
orequivalentcircuit
Figure 2. Output Load
* Includes jig and scope capacitances.
ACELECTRICALCHARACTERISTICS
(Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)
Industrial
IDT72615L25 IDT72615L35
IDT72605L25 IDT72605L35
IDT72615L20
IDT72605L20
IDT72615L50
IDT72605L50
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Min.
Max. Unit
Timing Figures
fCLK
Clockfrequency
Clock cycle time
Clock HIGH time
Clock LOW time
Resetpulsewidth
Resetsetuptime
—
50
—
40
—
28
—
—
—
—
—
—
35
—
50
20
20
50
30
30
—
3
20
—
—
—
—
—
—
50
MHz
ns
—
tCLK
tCLKH
tCLKL
tRS
20
8
—
—
—
—
—
—
27
25
10
10
25
15
15
—
3
—
—
—
—
—
—
28
35
14
14
35
21
21
—
3
4,5,6,7
ns
4,5,6,7,12,13,14,15
8
ns
4,5,6,7,12,13,14,15
20
12
12
—
3
ns
3
tRSS
tRSR
tRSF
tA
ns
3
Resetrecoverytime
ns
3
Resettoflagsininitialstate
Dataaccesstime
ns
3
10
15
21
25
ns
5,7,8,9,10,11
tCS
Controlsignalsetuptime(1)
6
—
6
—
8
—
10
—
ns
4,5,6,7,8,9,10,11,
12,13,14,15
tCH
Controlsignalholdtime(1)
1
—
1
—
1
—
1
—
ns
4,5,6,7,10,11,12,
13,14,15
tDS
Datasetuptime
6
1
—
—
10
—
10
10
10
12
6
1
—
—
13
—
13
15
15
15
8
1
—
—
20
—
20
21
21
21
10
1
—
—
28
—
28
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
4,6,8,9,10,11
4,6
tDH
Dataholdtime
OutputEnableLOWtooutputdatavalid(2)
tOE
tOLZ
tOHZ
tFF
3
3
3
3
5,7,8,9,10,11
5,7,8,9,10,11
5,7,10,11
4,6,10,11
5,7,8,9,10,11
12,14
(2)
OutputEnableLOWtodatabusatLow-Z
0
0
0
0
(2)
OutputEnable HIGHtodata bus atHigh-Z
Clock to Full Flag time
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
tEF
Clock to Empty Flag time
tPAE
ClocktoProgrammable
Almost-EmptyFlagtime
tPAF
ClocktoProgrammable
Almost-FullFlagtime
—
10
17
12
—
—
—
12
19
15
—
—
—
17
25
21
—
—
—
20
34
30
—
—
ns
ns
ns
13,15
tSKEW1 Skew between CLKA & CLKB
forEmpty/FullFlags(2)
4,5,6,7,8,9,10,11
4,7,12,13,14,15
tSKEW2 Skew between CLKA & CLKB
forProgrammableFlags(2)
NOTES:
1. Control signals refer to CSA, R/WA, ENA, A2, A1, A0, R/WB, ENB.
2. Minimum values are guaranteed by design.
5
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
PORT A INTERFACE
FUNCTIONALDESCRIPTION
The SyncBiFIFO is straightforward to use in micro-processor-based
systemsbecauseeachporthasastandardmicroprocessorcontrolset.PortA
interfaceswithmicroprocessorthroughthethreeaddresspins(A2-A0)anda
ChipSelectCSA pins. WhenCSA is asserted,A2,A1,A0 andR/WA areused
toselectone ofsixinternalresources (Table 1).
WithA2=0andA1=0,A0determineswhetherdatacanbereadoutofoutput
registerorbe writtenintothe FIFO(A0=0), orthe data canpass throughthe
FIFO through the bypass path (A0=1).
WithA2=1,fourprogrammableflags(twoA→BFIFOprogrammableflags
and two B→A FIFO programmable flags) can be selected: the A→B FIFO
Almost-Empty flag Offset (A1=0, A0=0), A→B FIFO Almost-Full flag Offset
(A1=0,A0=1),B→AFIFOAlmost-EmptyflagOffset(A1=1,A0=0),B→AFIFO
Almost-FullflagOffset(A1=1,A0=1).
IDTs SyncBiFIFO is versatile for both multiprocessor and peripheral
applications. Datacanbestoredorretrievedfromtwosourcessimultaneously.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Two Dual-Port FIFO memory arrays are contained in the
SyncBiFIFO; one data buffer for each direction. Each port has its own
independentclock.DatatransferstotheI/Oregistersaregatedbytheenable
signals. The transferdirectionforeachportis controlledindependentlybya
read/writesignal. IndividualoutputenablesignalscontrolwhethertheSyncBiFIFO
is driving the data lines of a port or whether those data lines are in a high-
impedancestate.TheprocessorconnectedtoPortAoftheBiFIFOcansend
orreceivemessagesdirectlytothePortBdeviceusingthe18-bitbypasspath.
The SyncBiFIFO can be used in multiples of 18-bits. In a 36- to 36-bit
configuration, two SyncBiFIFOs operate in parallel. Both devices are pro-
grammedsimultaneously, 18databitstoeachdevice. Thisconfigurationcan
beextendedtowiderbuswidths(54-to54-bits,72-to72-bits,etc.)byadding
moreSyncBiFIFOstotheconfiguration.Figure1showsmultipleSyncBiFIFOs
configuredfor multiprocessorcommunication.
PortAisdisabledwhenCSAisdeassertedanddataAisinhigh-impedance
state.
BYPASSPATH
ThebypasspathsprovidedirectcommunicationbetweenPortAandPort
B.Therearetwofull18-bitbypasspaths,oneineachdirection.Duringabypass
operation,dataispasseddirectlybetweentheinputandoutputregisters,and
theFIFOmemoryisundisturbed.
PortAinitiatesandterminatesallbypassoperations. Thebypassflag,BYPB,
isassertedtoinformPortBthatabypassoperationisbeginning.Thebypass
flag state is controlled by the Port A controls, although the BYPB signal is
synchronizedtoCLKB.So,BYPBisassertedonthenextrisingedgeofCLKB
whenA2A1A0=001andCSAisLOW. WhenPortAreturnstonormalFIFOmode
(A2A1A0=000orCSA is HIGH),BYPB is deassertedonthe nextCLKB rising
edge.
The microprocessor or microcontroller connected to Port A controls all
operationsoftheSyncBiFIFO.Thus,allPortAinterfacepinsareinputsdriven
bythecontrollingprocessor. PortBinterfaceswithasecondprocessor.The
Port B control pins are inputs driven by the second processor.
RESET
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate
with CSA, ENA and ENB HIGH. During reset, both internal read and write
pointersaresettothefirstlocation.Aresetisrequiredafterpowerupbeforea
writeoperationcantakeplace.TheA→BandB→AFIFOEmptyFlags(EFAB,
EFBA)andProgrammableAlmost-Emptyflags(PAEAB,PAEBA)willbesetto
LOW after tRSF. The A→B and B→A FIFO Full Flags (FFAB, FFBA) and
ProgrammableAlmost-Fullflags(PAFAB,PAFBA)willbesettoHIGHaftertRSF.
Afterthereset,theoffsetsoftheAlmost-EmptyflagsandAlmost-Fullflagsforthe
A→BandB→AFIFOoffsetdefaultto8.
OncetheSyncBiFIFOisinbypassmode,alldatatransfersarecontrolled
by the standard Port A (R/WA, CLKA, ENA, OEA) and Port B (R/WB, CLKB,
ENB,OEB)interfacepins. Eachbypasspathcanbeconsideredasaoneword
deepFIFO.Dataisheldineachinputregisteruntilitisread. Sincethecontrols
IDT
SYNCBIFIFO
DATA A
DATA B
CLK CLK
A
B
CLK
CLK
MICROPROCESSOR
CONTROL A
CONTROL B
MICROPROCESSOR
A
B
DATA
DATA
IDT
SYNCBIFIFO
CONTROL
LOGIC
CONTROL
LOGIC
ADDR, I/0
ADDR, I/0
DATA A
DATA B
CLK CLK
CONTROL A CONTROL B
A
B
RAM A
RAM B
SYSTEM
CLOCK A
SYSTEM
CLOCK B
2704 drw 05
NOTES:
1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.
2. Control A consists of R/WA, ENA, OEA, CSA, A2, A1, A0. Control B consists of R/WB, ENB, OEB.
Figure 1. 36- to 36-bit Processor Interface Configuration
6
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
TABLE 1 PORT A OPERATION CONTROL SIGNALS
DataA
CSA
R/WA
ENA
OEA
I/O
Port A Operation
0
0
0
0
I
Data A is written on CLKA ≠. This write cycle immediately following low-impedance cycle is prohibited. Note
thateventhoughOEA=0, aLOWlogiclevelonR/WA,oncequalifiedbyarisingedgeonCLKA, will putDataAinto
ahigh-impedancestate.
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
0
1
1
X
X
1
X
0
1
0
1
X
X
I
I
Data A is written on CLKA ≠
DataAis ignored
O
O
O
O
I
Data is read(1) from RAM array to output register on CLKA ≠, Data A is low-impedance
Data is read(1) from RAM array to output register on CLKA ≠, Data A is high-impedance
Outputregisterdoesnotchange(2),DataAislow-impedance
Outputregisterdoesnotchange(2),DataAishigh-impedance
DataAis ignored(3)
O
DataAishigh-impedance(3)
NOTES:
1. When A2A1A0 = 000, the next B→A FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass path is selected and bypass
data from the Port B input register is read from the Port A output register. If A2A1A00 = 1XX, a flag offset register is selected and its offset is read out through Port A output
register.
2. Regardless of the condition of A2A1A0, the data in the Port A output register does not change and the B→A read pointer does not advance.
3. If CSA# is HIGH, then BYPB is HIGH. No bypass occur under this condition.
ofeachportoperateindependently,PortAcanbereadingbypassdataatthe
sametimePortBisreadingbypassdata.
TABLE 2 ACCESSING PORT A RE-
SOURCES USING CSA, A2, A1, AND A0
WhenR/WA andENA is LOW, data onpins DA0-DA17 is writtenintoPort
Ainputregister. FollowingtherisingedgeofCLKAforthiswrite,theA→BFull
Flag(FFAB)goesLOW. SubsequentwritesintoPortAareblockedbyinternal
logicuntilFFAB goes HIGHagain. OnthenextCLKBrisingedge,theA→B
EmptyFlag(EFAB)goesHIGHindicatingtoPortBthatdataisavailable. Once
R/WBisHIGHandENBisLOW,dataisreadintothePortBoutputregister. OEB
stillcontrolswhetherPortBisinahigh-impedancestate. WhenOEBisLOW,
theoutputregisterdataappearsatDB0-DB17. EFABgoesLOWfollowingthe
CLKBrisingedgeforthisread. FFABgoesHIGHonthenextCLKArisingedge,
lettingPortAknowthatanotherwordcanbewrittenthroughthebypasspath.
BypassdatatransfersfromPortBtoPortAworkinasimilarmannerwith
EFBA andFFBA indicatingthePortAoutputregisterstate.
CSA
0
0
A2
0
0
A1
0
0
A0
0
1
Read
Write
B→A FIFO
18-bitBypassPath
A→B FIFO Almost-Empty
A→B FIFO
0
1
0
0
FlagOffset
0
0
0
1
1
1
0
1
1
0
A→B FIFO Almost-Full
FlagOffset
B→A FIFO Almost-Empty
FlagOffset
1
1
1
B→A FIFO Almost-Full
FlagOffset
X
X
X
PortADisabled
When the Port A address changes from bypass mode (A2A1A0=001) to
FIFOmode(A2A1A0=000)ontherisingedgeofCLKA,thedataheldinthePort
Boutputregistermaybeoverwritten. UnlessPortAmonitorstheBYPBpinand
waitsforPortBtoclockoutthelastbypassword,datafromtheA→BFIFOwill
overwritedatainthePortBoutputregister. BYPB willgoHIGHontherising
edgeofCLKBsignifyingthatPortBhasfinisheditslastbypassoperation.Port
BmustreadanybypassdataintheoutputregisteronthislastCLKB clockor
itislostandtheSyncBiFIFOreturnstoFIFOoperations. Itisespeciallyimportant
tomonitorBYPBwhenCLKBismuchslowerthanCLKAtoavoidthiscondition.
BYPB willalsogoHIGHafterCSA isbroughtHIGH;inthismannerthePortB
bypass datamayalsobelost.
PROGRAMMABLEFLAGS
The IDT SyncBiFIFO has eight flags: four flags for A→B FIFO (EFAB,
PAEAB,PAFAB,FFAB),andfourflagsforB→AFIFO(EFBA,PAEBA,PAFBA,
FFBA). TheEmptyandFullflagsarefixed,whiletheAlmost-EmptyandAlmost-
FulloffsetscanbesettoanydepththroughtheFlagOffsetRegisters(seeTable
3).TheflagsareassertedatthedepthsshownintheFlagTruthTable(Table
4).Afterreset,theprogrammableflagoffsetsaresetto8.ThismeanstheAlmost-
EmptyflagsareassertedatEmpty+8wordsdeep,andtheAlmost-Fullflagsare
asserted at Full -8 words deep.
ThePAEABissynchronizedtoCLKB,whilePAEABissynchronizedtoCLKA;
andPAEBAissynchronizedtoCLKA,whilePAEBA issynchronizedtoCLKB.
Iftheminimumtime(tSKEW2)betweenarisingCLKBandarisingCLKAismet,
theflagwillchangestateonthecurrentclock;otherwise,theflagmaynotchange
stateuntilthenextclockrisingedge. Forthespecificflagtimings,refertoFigures
12-15.
SincethePortAprocessorcontrolsCSAandthebypassmode,thisscenario
canbehandledforB→Abypassdata. ThePortAprocessormustbesetup
to read the last bypass word before leaving bypass mode.
PORT A CONTROL SIGNALS
ThePortAcontrolsignalspinsdictatethevariousoperationsshowninTable
2. Port A is accessed when CSA is LOW, and is inactive if CSA is HIGH. R/
WAandENAlinesdeterminewhenDataAcanbewrittenorread. IfR/WAand
ENAareLOW,dataiswrittenintoinputregisterontheLOW-to-HIGHtransition
ofCLKA. IfR/WAisHIGHandOEAisLOW,datacomesoutofbusandisread
fromoutputregisterintothree-statebuffer. Refertopindescriptionsformore
information.
PORT B CONTROL SIGNALS
ThePortBcontrolsignalpinsdictatethevariousoperationsshowninTable
5. PortBis independentofCSA. R/WB andENB lines determine whenData
7
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
canbewrittenorreadinPortB.IfR/WBandENBareLOW,dataiswritteninto ifR/WBisLOW,bypassmessagesaretransferredintoB→Aoutputregister.
inputregister,andonLOW-to-HIGHtransitionofCLKBdataiswrittenintoinput IfR/WAisHIGH,bypassmessagesaretransferredintoA→Boutputregister.
registerandtheFIFOmemory. IfR/WBisHIGHandOEBisLOW,datacomes Refertopindescriptionsformoreinformation.
outofbusandisreadfromoutputregisterintothree-statebuffer.Inbypassmode,
TABLE 3 FLAG OFFSET REGISTER FORMAT
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
8
8
8
8
7
7
7
7
6
5
4
3
2
1
1
1
1
0
0
0
0
PAEAB Register
PAFAB Register
PAEBA Register
PAFBA Register
X
A→B FIFO Almost-Empty Flag Offset
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
6
5
4
3
2
X
A→B FIFO Almost-Full Flag Offset
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
6
5
4
3
2
X
B→A FIFO Almost-Empty Flag Offset
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
6
5
4
3
2
X
B→A FIFO Almost-Full Flag Offset
NOTE:
1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.
TABLE 4 INTERNAL FLAG TRUTH TABLE
Number of Words
in FIFO
From
0
1
n+1
D-m
D
To
0
n
D-(m+1)
D-1
EF
PAE
LOW
LOW
HIGH
HIGH
HIGH
PAF
FF
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
LOW
D
LOW
NOTE:
1. n = Programmable Empty Offset (PAEAB Register or PAEBA Register)
m = Programmable Full Offset (PAFAB Register or PAFBA Register)
D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)
TABLE 5 PORT B OPERATION CONTROL SIGNALS
DataB
R/WB
ENB
OEB
I/O
Port B Operation
Data B is written on CLKB ↑. This write cycle immediately following output low-impedance cycle is prohibited. Note
0
0
0
I
that even though OEB = 0, a LOW logic level on R/WB, once qualified by a rising edge on CLKB, will put Data B into a high-
impedancestate.
0
0
1
1
1
1
0
1
0
0
1
1
1
X
0
1
0
1
I
I
O
O
O
O
Data B is written on CLKB ↑.
DataBis ignored
Data is read(1) from RAM array to output register on CLKB ≠ Data B is low-impedance
Data is read(1) from RAM array to output register on CLKB ≠, Data B is high- impedance
Outputregisterdoesnotchange(2),DataBislow-impedance
Outputregisterdoesnotchange(2),DataBishigh-impedance
NOTES:
1. When A2A1A0 = 000 or 1XX, the next A→B FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass path is selected and
bypass data is read from the Port B output register.
2. Regardless of the condition of A2A1A0, the data in the Port B output register does not change and the A→B read pointer does not advance.
8
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
RS
t
RS
RSF
t
t
EFAB,
PAEAB,
EFBA,
PAEBA
RSF
EFAB,
PAEAB,
EFBA,
PAEBA
RSS
t
RSR
t
CSA,
ENA
ENB
,
2704 drw 06
Figure 3. Reset Timing
t
CLK
t
CLKH
t
CLKL
CLKA
A0, A1,
A2
R/WA
CS
A
A
t
CH
t
CS
EN
NO OPERATION
t
FF
t
FF
FFAB
t
DH
t
DS
DA0-DA17
tSKEW1
DATA IN VALID
CLKB
2704 drw 07
READ
NO READ OPERATION
Figure 4. Port A (A→B) Write Timing
9
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
A0, A1,
A2
R/WA
CS
A
A
tCH
tCS
NO OPERATION
EN
t
EF
tEF
EFBA
tA
VALID DATA
DA0-DA17
tOLZ
tOE
tOHZ
OEA
tSKEW1
CLKB
NO WRITE
WRITE
2704 drw 08
Figure 5. Port A (B→A) Read Timing
tCLK
tCLKH
tCLKL
CLKB
R/WB
tCH
tCS
ENB
NO OPERATION
t
FF
t
FF
FFBA
tDH
tDS
DB0-DB17
tSKEW1
DATA IN VALID
CLKA
2704 drw 09
READ
NO READ OPERATION
Figure 6. Port B (B→A) Write Timing
10
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
R/WB
tCH
tCS
ENB
NO OPERATION
t
EF
t
EF
EFBA
tA
VALID DATA
DB0-DB17
tOLZ
tOHZ
tOE
OEB
tSKEW1
CLKA
NO WRITE OPERATION
WRITE
2704 drw 10
Figure 7. Port B (A→B) Read Timing
CLKA
A0, A1, A2
R/WA
tCS
CS
A
, EN
A
tDS
D0
D1
D2
(First Valid Write)
D3
DA0-DA17
tFRL
(1)
tSKEW1
CLKB
R/WB
tCS
ENB
t
EF
EFAB
tA
tA
DB0-DB17
D1
D0
tOLZ
tOE
OEB
2704 drw 11
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing applies only at the Empty Boundary (EF = LOW).
Figure 8. A→B First Data Word Latency after Reset for Simultaneous Read and Write
11
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
CLKB
R/WB
tCS
ENB
tDS
D0
D1
D2
(First valid write)
D3
DB0-DB17
tFRL
tSKEW1
(1)
CLKA
A0, A1, A2
R/WA
tCS
CSA, EN
A
t
EF
EFBA
tA
tA
D0
D1
DA0-DA17
tOLZ
tOE
OEA
2704 drw 12
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundary (EF = LOW).
Figure 9. B→A First Data Word Latency after Reset for Simultaneous Read and Write
12
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
CLKA
tCS
A2, A1, A0 = 001
A0, A1, A2
R/WA
tCH
CS
A
A
tCS
tCH
EN
t
FF
t
FF
tFF
FIFO FLAG
FFAB
BYPASS FLAG
tDS
DA0-DA17
DATA INPUT
tSKEW1
tSKEW1
tSKEW1
CLKB
R/WB
tCS
ENB
t
EF
tEF
t
EF
FIFO FLAG
FIFO FLAG
BYPASS FLAG
EFAB
BYPB
tA
DB0-DB17
DATA OUTPUT
tOLZ
tOE
tOHZ
2704 drw 13
OEB
NOTES:
1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA LOW-to-HIGH transition.
2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for the next bypass
operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO
mode.
Figure 10. A→B Bypass Timing
13
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
CLKB
R/WB
tCH
tCS
ENB
t
FF
tFF
t
FF
t
FF
FFBA
BYPASS FLAG
FIFO FLAG
BYPB
tDS
DB0-DB17
DATA INPUT
tSKEW1
tSKEW1
tSKEW1
tSKEW1
CLKA
tCS
tCS
A2, A1, A0
= 001
A0
, A
1
, A
2
A
A
tCS
CS
R/
W
tCS
ENA
t
EF
t
EF
tEF
t
EF
EFBA
BYPASS FLAG
FIFO FLAG
FIFO FLAG
tA
DATA OUTPUT
DA0-DA17
tOLZ
tOHZ
tOE
2704 drw 14
OEA
NOTES:
1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA going LOW-to-HIGH.
2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO
mode.
Figure 11. B→A Bypass Timing
14
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
tCLKH
tCLKL
CLKA
tCH
tCS
EN
A
= 0)
(R/W
A
WRITE
n+1 words in FIFO
PAEAB
n words in FIFO
(1)
t
PAE
tSKEW2
t
PAE
(2)
CLKB
tCH
tCS
EN
A
= 1)
2704 drw 15
(R/W
B
READ
NOTES:
1. tSKEW2 the minimum time between a rising CLKA edge and a rising CLKB edge for PAEAB to change during that clock cycle. If the time between the rising edge of CLKA and
the rising edge of CLKB is less than tSKEW, then PAEAB may not go HIGH until the next CLKB rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes LOW.
Figure 12. A→B Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
(2)
CLKA
tCH
tCS
EN
A
(R/WA = 0)
WRITE
Full - (m+1) words in FIFO
PAFAB
Full - m words in FIFO
t
PAF
t
PAF
CLKB
tCH
tCS
EN
B
= 1)
2704 drw 16
(R/W
B
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFAB to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAFAB may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 13. A→B Programmable Almost-Full Flag Timing
15
IDT72605/72615CMOSSYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIALTEMPERATURERANGE
tCLKH
tCLKL
CLKB
tCH
tCS
EN
B
= 0)
(R/W
A
WRITE
PAEBA
n+1 words in FIFO
n words in FIFO
(1)
tSKEW2
t
PAE
tPAE
(2)
CLKA
tCH
tCS
2704 drw 17
EN
A
(R/WA = 1)
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAEBA to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAEBA may not go HIGH until the next CLKA rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
Figure 14. B→A Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
(2)
CLKB
tCH
tCS
EN
B
(R/WA = 0)
WRITE
Full - (m+1) words in FIFO
PAFBA
Full - m words in FIFO
(1)
tSKEW2
t
PAF
tPAF
CLKA
tCH
tCS
EN
A
= 1)
(R/W
A
2704 drw 18
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFBA to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAFBA may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 15. B→A Programmable Almost-Full Flag Timing
16
ORDERINGINFORMATION
X
IDT
XXXXX
Device Type Power Speed Package Process/
Temperature
Range
XX
X
X
Blank
Industrial (-40°C to +85°C)
J
PF
Plastic Leaded Chip Carrier (PLCC, J68-1)
Thin Quad Flat Pack (TQFP, PN64-1)
20
25
35
50
Clock Cycle Time (tCLK
in Nanoseconds
)
L
Low Power
72605
72615
256 x 18 Parallel SyncBiFIFO
512 x 18 Parallel SyncBiFIFO
2704 drw19
DATASHEETDOCUMENTHISTORY
11/02/2000
04/08/2003
pgs. 1, 2, 3, 4, 16
pg. 17.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
17
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