IDT72T20108L10BBI [IDT]
2.5 VOLT HIGH-SPEED TeraSync? DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION; 2.5 VOLT HIGH -SPEED TeraSync ™ DDR / SDR FIFO 20位/ 10位配置
| 型号： | IDT72T20108L10BBI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2.5 VOLT HIGH-SPEED TeraSync? DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION |
| 文件： | 总51页 (文件大小：478K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5VOLTHIGH-SPEEDTeraSync™DDR/SDRFIFO20-BIT/10-BITCONFIGURATION
32,768 x 20/65,536 x 10, 65,536 x 20/131,072 x 10
131,072 x 20/262,144 x 10, 262,144 x 20/524,288 x 10
IDT72T2098, IDT72T20108
IDT72T20118, IDT72T20128
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of four preselected offsets
• Dedicated serial clock input for serial programming of flag offsets
• User selectable input and output port bus sizing
-x20 in to x20 out
-x20 in to x10 out
-x10 in to x20 out
-x10 in to x10 out
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
FEATURES:
• Choose among the following memory organizations:
IDT72T2098
IDT72T20108
IDT72T20118
IDT72T20128
32,768 x 20/65,536 x 10
65,536 x 20/131,072 x 10
131,072 x 20/262,144 x 10
262,144 x 20/524,288 x 10
• Up to 250MHz Operation of Clocks
-4ns read/write cycle time, 3.2ns access time
• Users selectable input port to output port data rates, 500Mb/s
Data Rate
• Partial Reset clears data, but retains programmable settings
• Empty and Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into High-Impedance state
• JTAG port, provided for Boundary Scan function
• 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
• User selectable HSTL or LVTTL I/Os
• Read Enable & Read Clock Echo outputs aid high speed operation
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input enables/disables Write
Operations
• Read Chip Select (RCS) synchronous to RCLK
FUNCTIONALBLOCKDIAGRAM
D0 -Dn (x20, x10)
SREN SEN
SCLK
WCLK
WSDR
WEN
WCS
SI
SO
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
WRITE CONTROL
LOGIC
FLAG
LOGIC
FWFT
FSEL0
FSEL1
RAM ARRAY
WRITE POINTER
32,768 x 20 or 65,536 x 10
65,536 x 20 or 131,072 x 10
131,072 x 20 or 262,144 x 10
262,144 x 20 or 524,288 x 10
READ POINTER
BUS
IW
OW
CONFIGURATION
RT
READ
CONTROL
LOGIC
MARK
RSDR
MRS
PRS
OUTPUT REGISTER
RESET
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
RCLK
REN
RCS
TDI
Vref
HSTL I/0
CONTROL
EREN
OE
5996 drw01
HSTL
Q0 -Qn (x20, x10)
ERCLK
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheTeraSyncisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DECEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5996/8
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATIONS
A1 BALL PAD CORNER
A
V
CC
V
CC
DNC
DNC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
GND
GND
GND
GND
GND
Q1
Q0
Q3
Q2
Q5
Q4
Q7
Q6
Q9
V
DDQ
VDDQ
B
C
D
E
F
DNC
DNC
DNC
DNC
DNC
DNC
HSTL GND
Q8
DNC
DNC
DNC
DNC
DNC
DNC
VCC
VCC
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
DNC
DNC
DNC
VCC
VCC
VCC
VCC
V
DDQ
VDDQ
VDDQ
VDDQ
TRST
TDO
PAF
DNC
TCK
TDI
GND
VDDQ MARK
DNC
DNC
RCS
RT
REN
TMS
VDDQ
VDDQ
G
H
J
OE
WCLK
WEN
MRS
FWFT
WCS
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDQ
RCLK
FF/IR
VDDQ
VDDQ
SCLK
SI
SEN
SREN
FSEL1 FSEL0 GND
VDDQ
K
L
PRS
EREN
IW
DNC
V
CC
GND
GND
GND
GND
GND
GND
V
DDQ
SO
WSDR RSDR
PAE
DNC
DNC
DNC
DNC
OW
VCC
V
DDQ
ERCLK
DNC
M
N
P
R
T
EF
/
OR
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
VCC
VDDQ
DNC
D18
D19
VCC
V
CC
V
CC
VCC
GND
GND
GND
GND
8
GND
GND
GND
GND
9
VDDQ
V
DDQ
V
DDQ
VDDQ
DNC
DNC
Q11
Q10
14
DNC
DNC
DNC
GND
D16
D17
4
V
CC
D14
D15
5
V
CC
D12
D13
6
VCC
VDDQ
V
DDQ
V
DDQ
Q15
Q14
12
VDDQ
D10
D11
7
Q19
Q18
10
Q17
Q13
Q12
13
VCC
VCC
Q16
VDDQ
VDDQ
VREF
1
2
3
11
15
16
5996 drw02
NOTE:
1. DNC - Do Not Connect.
PBGA: 1mm pitch, 17mm x 17mm (BB208-1, order code: BB)
TOP VIEW
2
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
Boththeinputandoutputport canbeselectedforeither2.5V LVTTL orHSTL
operation. ThiscanbeachievedbytyingtheHSTLsignalLOWforLVTTLor
HIGHforHSTLvoltageoperation. WhenthereadportissetupforHSTLmode,
theReadChipSelect(RCS)inputalsohasthebenefitofdisablingthereadport
inputs,providingadditionalpowersavings.
DESCRIPTION:
TheIDT72T2098/72T20108/72T20118/72T20128areexceptionallydeep,
extremelyhighspeed,CMOSFirst-In-First-Out(FIFO)memorieswiththeability
toreadandwritedataonbothrisingandfallingedgesofclock. Thedevicehas
aflexiblex20/x10Bus-MatchingmodeandtheoptiontoselectSingleorDouble
Dataclockratesforinputandoutputports. TheseFIFOsofferseveralkeyuser
benefits:
• Flexible x20/x10 Bus-Matching on both read and write ports
• Abilitytoreadandwrite onbothrisingandfallingedges ofa clock
• UserselectableSingleorDoubleDataRateofinputandoutputports
• AuserselectableMARKlocationforretransmit
• User selectable I/O structure for HSTL or LVTTL
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittento
an empty FIFO to the time it can be read, is fixed and short.
• Highdensityofferingsupto5Mbit
• High speed operation of up to 250MHz
Thereistheoptionofselectingdifferentdataratesontheinputandoutputports
ofthedevice. Thereareatotaloffourcombinationstochoosefrom,DoubleData
Rate toDouble Data Rate (DDRtoDDR), DDRtoSingle Data Rate (DDRto
SDR), SDRtoDDR, andSDRtoSDR. The clockingcanbe setupusingthe
WSDRandRSDRpins. Forexample,tosetuptheinputtooutputcombination
ofDDRtoSDR,WSDRwillbeHIGHandRSDRwillbeLOW. Readandwrite
operations are initiatedonthe risingedge ofRCLKandWCLKrespectively,
neveronthefallingedge. IfRENorWENisassertedafterarisingedgeofclock,
noreadorwriteoperationswillbepossibleonthefallingedgeofthatsamepulse.
AnOutputEnable(OE)inputisprovidedforhigh-impedancecontrolofthe
outputs. A read Chip Select (RCS) input is also provided for synchronous
enable/disableofthereadportcontrolinput,REN.TheRCSinputissynchro-
nizedtothereadclock,andalsoprovideshigh-impedancecontrolstotheQn
dataoutputs. WhenRCSisdisabled,RENwillbedisabledinternallyandthe
data outputs willbe inHigh-Impedance. Unlike the ReadChipSelectsignal
however,OEisnotsynchronoustoRCLK.Outputsarehigh-impedanceshortly
afteradelaytimewhentheOEtransitionsfromLOWtoHIGH.
The Echo Read Enable (EREN) and Echo Read Clock (ERCLK) outputs
areusedtoprovidetightersynchronizationbetweenthedatabeingtransmitted
fromthe Qnoutputs andthe data beingreceivedbythe inputdevice. These
outputsignalsfromthereadportarerequiredforhigh-speeddatacommuni-
cations. Datareadfromthereadportisavailableontheoutputbuswithrespect
toERENandERCLK,whichis usefulwhendatais beingreadathigh-speed
operationswheresynchronizationisimportant.
ThefrequenciesofboththeRCLKandWCLKsignalsmayvaryfrom0tofMAX
withcompleteindependence. Therearenorestrictionsonthefrequencyofone
clockinputwithrespecttoanother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed. Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines. Beawarethat
in Double Data Rate (DDR) mode only the IDT Standard mode is available.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectlyto
thedataoutputlinesafterthreetransitionsofRCLK. Areadoperationdoesnot
have tobe performedtoaccess the firstwordwrittentothe FIFO. However,
subsequentwords writtentotheFIFOdorequireaLOWonRENforaccess.
ThestateoftheFWFTinputduringMasterResetdeterminesthetimingmode
inuse.
Bus-Matching Double Data Rate FIFOs are particularly appropriate for
network,video,telecommunications,datacommunicationsandotherapplica-
tionsthatrequirefastdatatransferonbothrisingandfallingedgesoftheclock.
Thisisagreatalternativetoincreasingdataratewithoutextendingthewidthof
thebusorthespeedofthedevice.Theyarealsoeffectiveinapplicationsthat
needtobufferlargeamountsofdataandmatchbussesofunequalsizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
whichcanassumeeithera20-bitora10-bitwidthasdeterminedbythestate
ofexternalcontrolpinsInputWidth(IW),OutputWidth(OW)duringtheMaster
Resetcycle.
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input. DatapresentontheDndatainputscanbewrittenintotheFIFO
on every rising and falling edge of WCLK when WEN is asserted and Write
SingleDataRate(WSDR)pinheldHIGH. Datacanbeselectedtowriteonly
ontherisingedgesofWCLKifWSDRisasserted.Toguaranteefunctionality
ofthedevice,WENmustbeacontrolledsignalandnottiedtoground.Thisis
importantbecauseWENmustbeHIGHduringthetimewhentheMasterReset
(MRS)pulse is LOW. Inaddition, the WSDR pinmustbe tiedHIGHorLOW.
Itis nota controlledsignalandcannotbe changedduringFIFOoperation.
WriteoperationscanbeselectedforeitherSingleorDoubleDataRatemode.
ForSingleDataRateoperation,writingintotheFIFOrequirestheWriteSingle
DataRate(WSDR)pintobeasserted. DatawillbewrittenintotheFIFOonthe
risingedgeofWCLKwhentheWriteEnable(WEN)is asserted. ForDouble
DataRateoperations,writingintotheFIFOrequiresWSDRtobedeasserted.
DatawillbewrittenintotheFIFOonbothrisingandfallingedgeofWCLKwhen
WENisasserted.
The output port is controlled by a Read Clock (RCLK) input and a Read
Enable(REN)input. DataisreadfromtheFIFOoneveryrisingandfallingedge
ofRCLKwhenRENisassertedandReadSingleDataRate(RSDR)pinheld
HIGH. DatacanbeselectedtoreadonlyontherisingedgesofRCLKifRSDR
isasserted. Toguaranteefunctionalityofthedevice,RENmustbeacontrolled
signalandnottiedtoground. This is importantbecause REN mustbe HIGH
duringthetimewhentheMasterReset(MRS)pulseis LOW.Inaddition,the
RSDRpinmustbetiedHIGHorLOW. Itisnotacontrolledsignalandcannot
be changed during FIFO operation.
ReadoperationscanbeselectedforeitherSingleorDoubleDataRatemode.
Similartothewriteoperations,readingfromtheFIFOinsingledataraterequires
theReadSingleDataRate(RSDR)pintobeasserted. Datawillbereadfrom
theFIFOontherisingedgeofRCLKwhentheReadEnable(REN)isasserted.
ForDoubleDataRateoperations,readingintotheFIFOrequiresRSDRtobe
deasserted. DatawillbereadoutoftheFIFOonbothrisingandfallingedge
of RCLK when and REN is asserted.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan
provide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
TheseFIFOshavefourflagpins,EF/OR(EmptyFlagorOutputReady),FF/
IR (FullFlagorInputReady), PAE (ProgrammableAlmost-Emptyflag),and
PAF(ProgrammableAlmost-Fullflag).TheEFandFFfunctionsareselected
inIDTStandardmode.TheIRandORfunctionsareselectedinFWFTmode.
PAE andPAF are always available foruse, irrespective oftimingmode.
PAEandPAFflagscanbeprogrammedindependentlytoswitchatanypoint
inmemory. Programmableoffsetsmarkthelocationwithintheinternalmemory
thatactivatesthePAEandPAFflagsandcanonlybeprogrammedserially. To
programtheoffsets,setSENactiveanddatacanbeloadedviatheSerialInput
3
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol
inputs,MARKandRT(Retransmit). IftheMARKinputisenabledwithrespect
totheRCLK,thememorylocationbeingreadatthepointwillbemarked. Any
subsequent retransmit operation (when RT goes LOW), will reset the read
pointertothis“marked”location.
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas
previouslystated. Theseratesare:x20tox20,x20tox10,x10tox20andx10
to x10.
DESCRIPTION(CONTINUED)
(SI)pinattherisingedgeofSCLK. Toreadouttheoffsetregistersserially,set
SRENactiveanddatacanbereadoutviatheSerialOutput(SO)pinattherising
edgeofSCLK. Fourdefaultoffsetsettingsarealsoprovided,sothatPAEcan
bemarkedatapredefinednumberoflocationsfromtheemptyboundaryand
thePAFthresholdcanalsobemarkedatsimilarpredefinedvaluesfromthefull
boundary. ThedefaultoffsetvaluesaresetduringMasterResetbythestate
of the FSEL0 and FSEL1 pins.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown. Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
AJTAGtestportis provided, here the FIFOhas fullyfunctionalboundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
BoundaryScanArchitecture.
TheDoubleDataRateFIFOhasthecapabilityofoperatingineitherLVTTL
orHSTLmode. HSTLmodecanbeselectedbyenablingtheHSTLpin. Both
inputandoutputportswilloperateineitherHSTLorLVTTLmode,butcannot
beselectedindependentofoneanother.
DuringMasterReset(MRS),thefollowingeventsoccur:thereadandwrite
pointersaresettothefirstlocationoftheinternalFIFOmemory,theFWFTpin
selectsIDTStandardmodeorFWFTmode,thebuswidthconfigurationofthe
readandwriteportisdeterminedbythestateofIWandOW,andthedefaultoffset
valuesfortheprogrammableflagsareset.
The Partial Reset (PRS) also sets the read and write pointers to the first
locationofthememory. However,thetimingmodeandthevaluesstoredinthe
programmableoffsetregistersbeforePartialResetremainunchanged. The
flagsareupdatedaccordingtothetimingmodeandoffsetsineffect. PRSisuseful
forresettingadeviceinmid-operation,whenreprogrammingprogrammable
flagswouldbeundesirable.
The IDT72T2098/72T20108/72T20118/72T20128 are fabricated using
IDT’shigh-speedsubmicronCMOStechnology.
The timing of thePAE and PAF flags are synchronous to RCLK and WCLK,
respectively. The PAE flag is asserted upon the rising edge of RCLK only and
not WCLK. Similarly the PAF is asserted and updated on the rising edge of
WCLK only and not RCLK.
4
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE ENABLE (WEN)
WRITE CHIP SELECT (WCS)
IDT
READ CHIP SELECT (RCS)
72T2098
72T20108
72T20118
72T20128
WRITE SINGLE DATA RATE (WSDR)
READ SINGLE DATA RATE (RSDR)
(x20, x10) DATA IN (D
0
- Dn)
(x20, x10) DATA OUT (Q0 - Qn)
RCLK ECHO (ERCLK)
REN ECHO (EREN)
MARK
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
SERIAL READ ENABLE(SREN)
FIRST WORD FALL THROUGH (FWFT)
SERIAL INPUT (SI)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
SERIAL OUTPUT (SO)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
5996 drw03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
Figure 1. Single Device Configuration Signal Flow Diagram
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IW
OW
Write Port Width
Read Port Width
L
L
L
H
L
x20
x20
x10
x10
x20
x10
x20
x10
H
H
H
NOTE:
1. Pin status during Master Reset.
TABLE 2 — DATA RATE-MATCHING CONFIGURATION MODES
WSDR
RSDR
Write Port Width
Read Port Width
H
H
L
L
H
L
H
L
DoubleDataRate
DoubleDataRate
SingleDataRate
SingleDataRate
DoubleDataRate
SingleDataRate
DoubleDataRate
SingleDataRate
NOTE:
1. Pin status during Master Reset.
2. Data Rate Matching can be used in conjunction with Bus-Matching modes.
5
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION
Symbol &
Pin No.
Name
I/OTYPE
Description
D0-D19
DataInputs
HSTL-LVTTL Data inputs fora 20-, or10-bitbus. Whenusing10-bitmode, the unusedinputpins are ina don’tcare
(See Pin No.
tablefordetails)
INPUT
state.ThedatabusissampledonbothrisingandfallingedgesofWCLKwhenWENisenabledandDDR
Mode is enabled or on the rising edges of WCLK only in SDR Mode.
EF/OR
(M14)
EmptyFlag/
OutputReady
HSTL-LVTTL IntheIDTStandardmode,theEFfunctionisselected.EFindicateswhetherornottheFIFOmemoryis
OUTPUT empty.InFWFTmode,theORfunctionisselected.ORindicateswhetherornotthereisvaliddataavailable
attheoutputs.
ERCLK
(L16)
Echo Read
Clock
HSTL-LVTTL ReadClockEchooutput,mustbeequaltoorfasterthantheQndataoutputs.
OUTPUT
EREN
(K16)
Echo Read
Enable
HSTL-LVTTL ReadEnableEchooutput,usedinconjunctionwithERCLK.
OUTPUT
FF/IR
(H3)
Full Flag/
Input Ready
HSTL-LVTTL IntheIDTStandardmode,theFFfunctionisselected. FFindicateswhetherornottheFIFOmemoryis
OUTPUT empty. InFWFTmode,theIRfunctionisselected. IRindicateswhetherornotthereisspaceavailable
forwritingtotheFIFOmemory.
FSEL0(1)
(J3)
FSEL1(1)
(J2)
FlagSelectBit0
Flag Select Bit 1
LVTTL
INPUT
DuringMasterReset,thisinputalongwithFSEL1willselectthedefaultoffsetvaluesfortheprogrammable
flags PAEandPAF. There are fourpossible settings available.
LVTTL
INPUT
DuringMasterReset, thisinputalongwithFSEL0willselectthedefaultoffsetvaluesfortheprogrammable
flags PAE and PAF. There are four possible settings available.
FWFT
(G2)
FirstWordFall
Through
LVTTL
INPUT
DuringMasterreset, selects FirstWordFallThroughorIDTStandardmode. FWFTis notavailable in
DDR mode. In SDR mode, the first word will always fall through on the rising edge.
(1)
HSTL
(B7)
HSTLSelect
LVTTL
INPUT
ThisinputpinisusedtoselectHSTLor2.5VLVTTLdeviceoperation. IfHSTLinputsarerequired,this
inputmustbetiedHIGH,otherwiseitshouldbetiedLOW.
(1)
IW
InputWidth
LVTTL
DuringMasterReset,this pin,alongwithOWselects thebus widthofthereadandwriteport.
INPUT
(K1)
MARK
(E14)
Mark Read
Pointerfor
Retransmit
HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked. AnysubsequentRetransmit
INPUT
operationwillresetthereadpointertothisposition. Thereisanunlimitednumbertotimestosetthemark
location,butonlythemostrecentlocationmarkedwillbeacknowledged.
MRS
(J1)
MasterReset
HSTL-LVTTL MRSinitializesthereadandwritepointerstozeroandsetstheoutputregisterstoallzeros. DuringMaster
INPUT
Reset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,
programmableflagdefaultsettings,andsingleordoubledataclockmode.
OE
OutputEnable
OutputWidth
HSTL-LVTTL WhenHIGH,dataoutputsQ0-Q19areinhighimpedance. WhenLOW,thedataoutputsQ0-Q19areenabled.
(G15)
INPUT
NootheroutputsareaffectedbyOE.
(1)
OW
(L3)
LVTTL
INPUT
DuringMasterReset,this pinalongwithIWselects thebus widthofthereadandwriteport.
PAE
(L15)
Programmable HSTL-LVTTL PAEgoesHIGHifthenumberofwordsintheFIFOmemoryisgreaterthanorequaltooffsetn,whichis
Almost-Empty
Flag
OUTPUT storedintheEmptyOffsetregister. PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthan
offsetn.
PAF
Programmable HSTL-LVTTL PAFgoesHIGHifthenumberoffreelocationsintheFIFOmemoryismorethanoffsetm,whichisstored
(G3)
Almost-FullFlag
PartialReset
DataOutputs
OUTPUT intheFullOffsetregister.PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthan
or equal to m.
PRS
(K3)
HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregisterstoallzeros. DuringPartial
INPUT
Reset,theexistingmode(IDTstandardorFWFT)andprogrammableflagsettingsarenotaffected.
Q0-Q19
(See Pin No.
tablefordetails)
HSTL-LVTTL Dataoutputsfora20-,or10-bitbus. Whenin10-bitmode,theunusedoutputpinsshouldnotbeconnected.
OUTPUT TheoutputdataisclockedonbothrisingandfallingedgesofRCLKwhenRENisenabledandDDRMode
is enabled or on the rising edges of RCLK only in SDR Mode.
RCLK
(G16)
ReadClock
HSTL-LVTTL InputclockwhenusedinconjunctionwithRENforreadingdatafromtheFIFOmemoryandoutput
INPUT
register.
6
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
RCS
(F14)
Read Chip
Select
HSTL-LVTTL RCSprovidessynchronousenable/disablecontrolof thereadportandHigh-Impedancecontrolofthe
INPUT
Qndataoutputs,synchronoustoRCLK. WhenusingRCS theOEpinmustbetiedLOW. DuringMaster
orPartialResettheRCSinputisdon’tcare,ifOEisLOWthedataoutputswillbeLow-Impedanceregardless
ofRCS.
REN
(F16)
ReadEnable
HSTL-LVTTL WhenLOWandinDDRmode,RENalongwitharisingandfallingedgeofRCLKwillsenddatainFIFO
INPUT
memorytothe outputregisterandreadthe currentdata inoutputregister. InSDRmode data willonly
be read on the rising edge of RCLK only.
(1)
RSDR
(L2)
ReadSingle
DataRate
LVTTL
INPUT
WhenLOW,thisinputpinsetsthereadporttoSingleDataClockmode. WhenHIGH,thereadportwill
operateinDoubleDataClockmode.ThispinmustbetiedeitherHIGHorLOWandcannottoggleduring
operation.
RT
(F15)
Retransmit
HSTL-LVTTL RTassertedontherisingedgeofRCLKinitializesthereadpointertothefirstlocationinmemory.EFflag
INPUT
issettoLOW(ORtoHIGHinFWFTmode).Thewritepointer,offsetregisters,andflagsettingsarenot
affected.IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwillinitializetothemarklocation
when RT is asserted.
SCLK
(H15)
SerialClock
LVTTL
INPUT
ArisingedgeofSCLKwillclocktheserialdatapresentontheSIinputintotheoffsetregistersprovided
thatSENisenabled.ArisingedgeofSCLKwillalsoreaddataoutoftheoffsetregistersprovidedthatSREN
isenabled.
SEN
(J15)
SerialInput
Enable
HSTL-LVTTL SENusedinconjunctionwithSIandSCLKenablesserialloadingoftheprogrammableflagoffsets.
INPUT
SREN
(J16)
Serial Read
Enable
HSTL-LVTTL SRENusedinconjunctionwithSOandSCLKenablesserialreadingoftheprogrammableflagoffsets.
INPUT
SI
(H16)
SerialInput
SerialOutput
JTAGClock
HSTL-LVTTL Thisinputpinisusedtoloadserialdataintotheprogrammableflagoffsets.UsedinconjunctionwithSEN
INPUT
and SCLK.
SO
(K15)
HSTL-LVTTL Thisoutputpinisusedtoreaddatafromtheprogrammableflagoffsets.UsedinconjunctionwithSREN
OUTPUT and SCLK.
(2)
TCK
HSTL-LVTTL ClockinputforJTAGfunction.Oneoffourterminals requiredbyIEEEStandard1149.1-1990.Test
(F1)
INPUT
operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge
ofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneeds
tobe tiedtoGND.
(2)
TDI
JTAGTestData HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
(E2)
Input
INPUT
operation,testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,
IDRegisterandBypass Register.Aninternalpull-upresistorforces TDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
(F3)
Output
OUTPUT
operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstruction
Register,IDRegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whilein
SHIFT-DR and SHIFT-IR controller states.
TMS(2)
(F2)
JTAGMode
Select
HSTL-LVTTL TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthe
INPUT thedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
(2)
TRST
JTAGReset
(E3)
INPUT
automaticallyresetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGH
forfiveTCKcycles.IftheTAPcontrollerisnotproperlyresetthentheFIFOoutputswillalwaysbeinhigh-
impedance.IftheJTAGfunctionisusedbuttheuserdoesnotwanttouseTRST,thenTRSTcanbetied
withMRStoensureproperFIFOoperation.IftheJTAGfunctionisnotusedthenthissignalneedstobe
tiedtoGND.Aninternalpull-upresistorforcesTRSTHIGHifleftunconnected.
WCLK
(G1)
WriteClock
HSTL-LVTTL InputclockwhenusedinconjunctionwithWENforwritingdataintotheFIFOmemory.
INPUT
WCS
(H2)
WriteChipSelect HSTL-LVTTL The WCS pin an be regarded as a second WEN input, enabling/disabling write operations.
INPUT
WEN
(H1)
WriteEnable
HSTL-LVTTL WhenLOWandinDDRmode,WENalongwitharisingandfallingedgeofWCLKwillwritedataintothe
INPUT
FIFO memory. In SDR mode data will only be read on the rising edge of RCLK only.
7
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION(CONTINUED)
Symbol &
Pin No.
Name
I/OTYPE
Description
(1)
WSDR
(L1)
WriteSingleData
Rate
LVTTL
INPUT
WhenLOW,thisinputpinsetsthewriteporttoSingleDataClockmode. WhenHIGH,thewriteportwill
operateinDoubleDataClockmode. ThispinmustbetiedeitherHIGHorLOWandcannottoggleduring
operation.
VCC
(See below)
+2.5VSupply
O/PRailVoltage
GroundPin
INPUT
INPUT
INPUT
INPUT
There are VCC supply inputs and must be connected to the 2.5V supply rail.
VDDQ
(See below)
Thispinshouldbetiedtothedesiredvoltagerailforprovidingpowertotheoutputdrivers. Nominally1.5V
or 1.8V for HSTL, 2.5V for LVTTL.
GND
(See below)
These are Ground pins are for the core device and must be connected to the GND rail.
Vref
(T3)
Reference
Voltage
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedintheRecommended
DC OperatingConditionssection. ThisprovidesthereferencevoltagewhenusingHSTLclassinputs.
IfHSTLclassinputsarenotbeingused,thispincanbeleftfloating.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 24-27 and Figures 5-7.
PIN NUMBER TABLE
Symbol
Name
I/OTYPE
HSTL-LVTTL D0-C3, D1-A4, D2-B4, D3-C4, D4-A5, D5-B5, D6-C5, D7-A6, D8-B6, D9-A7, D10-R7, D11-T7,
INPUT D12-R6, D13-T6, D14-R5, D15-T5, D16-R4, D17-T4, D18-P3, D19-R3
Pin Number
D0-19
DataInputs
Q0-19
DataOutputs
HSTL-LVTTL Q0-B10, Q1-A10, Q2-B11, Q3-A11, Q4-B12, Q5-A12, Q6-B13, Q7-A13, Q8-B14, Q9-A14, Q10-T14
OUTPUT Q11-R14, Q12-T13, Q13-R13, Q14-T12, Q15-R12, Q16-T11, Q17-R11, Q18-T10, Q19-R10
VCC
+2.5VSupply
INPUT
INPUT
A(1,2), C(6,7), D(4-7), K4, L4, M4, N(4-7), P(5-7), T(1,2)
VDDQ
O/PRailVoltage
A(15,16), C(10-13), D(10-13), E13, F(4,13), G(4,14), H(4,14), J14, K14, L14, M13, N(10-13),
P(10-13), T(15,16)
GND
DNC
GroundPin
INPUT
—
A(8,9), B(8,9), C(8,9), D(8,9), E4, G(7-10,13), H(7-10,13), J(4,7-10,13), K(7-10,13), L13, N(8,9),
P(4,8,9), R(8,9), T(8,9)
DoNotConnect
A3,B(1-3,15,16),C(1,2,14-16),D(1-3,14-16),E(1,15,16),K2,M(1-3,15,16),N(1-3,14-16),P(1,2,14-16),
R(1,2,15,16)
8
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions
Max.
Unit
Symbol
Rating
Commercial
–0.5to+3.6(2)
Unit
Symbol
VTERM
TerminalVoltage
with respect to GND
V
CIN
Input
Capacitance
VIN = 0V
10(3)
pF
(2,3)
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
(1,2)
COUT
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
RECOMMENDEDDCOPERATINGCONDITIONS
Symbol
VCC
Parameter
Min.
2.375
0
Typ.
2.5
0
Max.
2.625
0
Unit
V
SupplyVoltage
SupplyVoltage
GND
V
VIH
InputHighVoltage
LVTTL
eHSTL
HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
—
—
V
V
V
VIL
InputLowVoltage
LVTTL
eHSTL
HSTL
-0.3
—
—
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
VREF
(HSTL only)
VoltageReferenceInput eHSTL
HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
TA
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
0
—
—
70
85
°C
°C
TA
-40
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
ILI
Parameter
Min.
–10
–10
Max.
10
Unit
InputLeakageCurrent
OutputLeakageCurrent
µA
µA
V
V
V
ILO
10
(5)
VOH
OutputLogic“1”Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
VDDQ-0.4
VDDQ-0.4
VDDQ-0.4
—
—
—
IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
VOL
OutputLogic“0”Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL)
—
—
—
0.4V
0.4V
0.4V
V
V
V
IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL)
ICC1(1,2)
ICC2(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
20
60
60
mA
mA
mA
Standby VCC Current (VCC = 2.5V) I/O = LVTTL
—
—
—
10
50
50
mA
mA
mA
I/O = HSTL
I/O = eHSTL
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.
2. Typical ICC1 calculation: for LVTTL I/O ICC1 (mA) = 0.6mA x fs, fs = WCLK frequency = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 38mA + (0.7mA x fs), fs = WCLK frequency = RCLK frequency (in MHz)
3. Typical IDDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.15mA x fs
With Data Outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x 2N)/2000
fs = WCLK frequency = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching.
tA = 25°C, CL = capacitive load (pf)
4. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].
5. Outputs are not 3.3V tolerant.
9
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Commercial
Commercial
Com’l & Ind’l(2)
Commercial
IDT72T2098L4
IDT72T2098L5
IDT72T2098L6-7 IDT72T2098L10
IDT72T20108L4 IDT72T20108L5 IDT72T20108L6-7 IDT72T20108L10
IDT72T20118L4 IDT72T20118L5 IDT72T20118L6-7 IDT72T20118L10
IDT72T20128L4 IDT72T20128L5 IDT72T20128L6-7 IDT72T20128L10
0
0
0
Symbol
fS1
Parameter
Clock Cycle Frequency SDR
Clock Cycle Frequency DDR
DataAccessTime
Min.
—
—
0.6
0.6
4
Max.
250
150
3.2
3.2
—
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
—
0.6
0.6
5
Max.
200
150
3.6
3.6
—
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
—
0.6
0.6
6.7
6.7
2.8
2.8
2.8
2.8
2.0
0.5
2.0
0.5
2.0
0.5
—
100
45
45
15
5
Max.
150
150
3.8
3.8
—
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
—
0.6
0.6
10
10
4.5
4.5
4.5
4.5
3.0
0.5
3.0
0.5
3.0
0.5
—
100
45
45
15
5
Max.
100
100
4.5
4.5
—
—
—
—
—
—
—
—
—
—
—
—
10
Unit
MHz
MHz
ns
fS2
Unit
MHz
ns
tA
tASO
DataAccessSerialOutputTime
Clock Cycle Time SDR
Clock Cycle Time DDR
Clock High Time SDR
Clock High Time DDR
Clock Low Time SDR
Clock Low Time DDR
DataSetupTime
ns
tCLK1
tCLK2
tCLKH1
tCLKH2
tCLKL1
tCLKL2
tDS
ns
ns
6.7
1.8
2.8
1.8
2.8
1.2
0.5
1.2
0.5
1.2
0.5
—
100
45
6.7
2.3
2.8
2.3
2.8
1.5
0.5
1.5
0.5
1.5
0.5
—
100
45
45
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
DataHoldTime
ns
ns
tENS
EnableSetupTime
ns
ns
tENH
EnableHoldTime
ns
ns
tWCSS
tWCSH
fC
WCSsetuptime
WCSholdtime
Clock Cycle Frequency (SCLK)
ns
MHz
ns
ns
MHz
ns
ns
tSCLK
tSCKH
tSCKL
tSDS
Serial Clock Cycle
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
15
ns
Serial Clock High
ns
ns
Serial Clock Low
45
ns
ns
SerialDataInSetup
Serial Data In Hold
15
ns
ns
tSDH
5
ns
ns
tSENS
tSENH
tRS
SerialEnableSetup
5
5
5
5
ns
ns
SerialEnableHold
ResetPulseWidth(3)
5
5
5
5
ns
ns
30
30
15
4
30
15
4
30
15
4
ns
µs
ns
tRSS
ResetSetupTime
15
ns
tHRSS
tRSR
HSTLResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
4
µs
ns
ns
10
10
—
0
10
—
0
10
—
0
ns
tRSF
—
0
ns
ns
(4)
tOLZ
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid
—
3.2
3.2
3.2
3.2
3.2
3.2
3.6
3.2
3.2
3.2
—
—
—
—
3.6
3.6
3.6
3.6
3.6
3.6
4
—
3.8
3.8
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
—
—
—
—
4.5
4.5
4.5
4.5
4.5
4.5
5
ns
ns
tOE
—
—
—
—
—
—
—
—
—
—
3.5
3.5
4
—
—
—
—
—
—
—
—
—
—
4
—
—
—
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
—
—
—
7
ns
ns
(4)
tOHZ
OutputEnabletoOutputinHighZ
ns
ns
tWFF
tREF
Write Clock to FF or IR
Read Clock to EF or OR
WriteClocktoProgrammableAlmost-FullFlag
ReadClocktoProgrammableAlmost-EmptyFlag
RCLK to Echo RCLK output
ns
ns
ns
ns
tPAFS
tPAES
tERCLK
tCLKEN
tRCSLZ
tRCSHZ
tSKEW1
tSKEW2
tSKEW3
NOTES:
ns
ns
ns
ns
ns
ns
RCLK to Echo REN output
RCLK to Active from High-Z
3.6
3.6
3.6
—
—
—
4.5
4.5
4.5
—
—
—
ns
ns
ns
ns
(4)
RCLK to High-Z
ns
ns
Skew time between RCLK and WCLK for EF/OR and FF/IR
SkewtimebetweenRCLK&WCLKforEF/OR &FF/IR inDDRmode
Skew time between RCLK and WCLK for PAE and PAF
ns
4
5
7
ns
ns
5
6
8
ns
1. All AC timings apply to both IDT Standard mode and First Word Fall Through mode.
2. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
10
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
HSTL
AC TEST LOADS
1.5V AC TEST CONDITIONS
VDDQ/2
InputPulseLevels
0.25to1.25V
0.4ns
50
Ω
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.75
Z0 = 50Ω
I/O
VDDQ/2
5996 drw04
NOTE:
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDEDHSTL
1.8V AC TEST CONDITIONS
6
5
4
3
2
1
InputPulseLevels
0.4 to 1.4V
0.4ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.9
VDDQ/2
NOTE:
1. VDDQ = 1.8V±.
20 30 50 80 100
Capacitance (pF)
200
5996 drw04a
Figure 2b. Lumped Capacitive Load, Typical Derating
2.5VLVTTL
2.5V AC TEST CONDITIONS
InputPulseLevels
GND to 2.5V
1ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
VCC/2
VDDQ/2
NOTE:
1. For LVTTL VCC = VDDQ.
11
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
V
IH
OE
VIL
tOE &
tOLZ
tOHZ
Output
Normally
LOW
V
2
CC
V
2
CC
100mV
100mV
100mV
V
OL
V
OH
CC
Output
Normally
HIGH
VCC
100mV
V
2
2
5996 drw04b
NOTES:
1. REN is HIGH.
2. RCS is LOW.
READ CHIP SELECT ENABLE & DISABLE TIMING
V
IH
tENH
RCS
VIL
tENS
RCLK
tRCSHZ
tRCSLZ
Output
Normally
LOW
V
2
CC
V
2
CC
100mV
100mV
100mV
V
OL
V
OH
CC
Output
Normally
HIGH
VCC
100mV
V
2
2
5996 drw04c
NOTES:
1. REN is HIGH.
2. OE is LOW.
12
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF to go HIGH at the conditions
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.IDTStandardmodeisavailablewhenthedeviceis
configuredinbothSingleDataRatemodeandDoubleDataRatemode.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
10, 11, 12, 13, 14, 15, 16, 17, 18 and 23.
(FWFT) MODE
TheIDT72T2098/72T20108/72T20118/72T20128supporttwodifferent
timing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT)mode.Theselectionofwhichmodewilloperateisdeterminedduring
MasterReset,bythestateoftheFWFTinput.
If,atthetimeofMasterReset,FWFTisLOW,thenIDTStandardmodewill
be selected. This mode uses the EmptyFlag(EF)toindicate whetherornot
thereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction(FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standardmode, everywordreadfromthe FIFO, includingthe first, mustbe
requested using the Read Enable (REN) and RCLK.
FIRST WORD FALL THROUGH MODE (FWFT)
Inthismode,thestatusflags,IR,PAF,PAE,andORoperateinthemanner
outlined in Table 5. To write data into the FIFO, WEN must be LOW. Data
presentedtothe DATAINlines willbe clockedintothe FIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern+2words havebeenloadedintotheFIFO,wherenis theempty
offsetvalue.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2.Thisparameterisalsouserprogrammable.SeesectiononProgrammable
FlagOffsetLoading.
If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,REN=LOWisnotnecessary.Subsequentwordsmustbeaccessed
using the Read Enable (REN) and RCLK.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
Again, ifnoreads are performed, the PAF willgoLOWafter(D-m)writes
totheFIFO.Ifx20Inputorx20OutputbusWidthisselected,(D-m) = (32,769-m)
writesfortheIDT72T2098,(65,537-m)writesfortheIDT72T20108,(131,073-m)
writes fortheIDT72T20118and(262,145-m)writes fortheIDT72T20128.If
bothx10Inputandx10Outputbus Widths areselected,(D-m)=(65,537-m)
writes for the IDT72T2098, (131,073-m) writes for the IDT72T20108,
(262,145-m) writes for the IDT72T20118 and (524,289-m) writes for the
IDT72T20128.Theoffsetmisthefulloffsetvalue.Thedefaultsettingforthese
values arestatedinthefootnoteofTable3.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations.Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
DwritestotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,D = 32,769
writesfortheIDT72T2098,65,537writesfortheIDT72T20108,131,073writes
fortheIDT72T20118and262,145writesfortheIDT72T20128.Ifbothx10Input
andx10OutputbusWidthsareselected,D=65,537writesfortheIDT72T2098,
131,073writesfortheIDT72T20108,262,145writesfortheIDT72T20118and
524,289writesfortheIDT72T20128,respectively.Notethattheadditionalword
inFWFTmodeisduetothecapacityofthememoryplusoutputregister.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
SubsequentreadoperationswillcausethePAFtogoHIGHattheconditions
describedinTable5.Iffurtherreadoperationsoccur,withoutwriteoperations,
thePAEwillgoLOWwhentherearen+1wordsintheFIFO,wherenistheempty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
Whenthelastwordhas beenreadfromtheFIFO,OR willgoHIGHinhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered,andtheIRflagoutputisdoubleregister-buffered.FWFTmodeisonly
available whenthe device is configuredinSingle Data Rate mode.
Relevanttimingdiagrams forFWFTmodecanbefoundinFigure19,20,
21, 22, and 24.
IDT STANDARD MODE
Inthismode,thestatusflags,FF,PAF,PAE,andEFoperateinthemanner
outlinedinTable4.TowritedataintototheFIFO,WriteEnable(WEN)must
beLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFOon
subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarelistedinTable2.Thisparameter
isalsouserprogrammable.SeesectiononProgrammableFlagOffsetLoading.
ContinuingtowritedataintotheFIFOwillcausetheProgrammableAlmost-
Fullflag(PAF)togoLOW. Again, ifnoreads are performed, the PAF willgo
LOW after (D-m) writes to the FIFO. If x20 Input or x20 Output bus Width is
selected,(D-m) = (32,768-m)writesfortheIDT72T2098,(65,536-m)writes
for the IDT72T20108, (131,072-m) writes for the IDT72T20118 and
(262,144-m)writesfortheIDT72T20128.Ifbothx10Inputandx10Outputbus
Widthsareselected,(D-m) = (65,536-m)writesfortheIDT72T2098,(131,072-m)
writes for the IDT72T20108, (262,144-m) writes for the IDT72T20118 and
(524,288-m)writesfortheIDT72T20128.Theoffset“m”isthefulloffsetvalue.
ThedefaultsettingforthesevaluesarelistedinTable3.Thisparameterisalso
userprogrammable.SeethesectiononProgrammableFlagOffsetLoading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
tothe FIFO. Ifthe x20Inputorx20Outputbus Widthis selected, D=32,768
writesfortheIDT72T2098,65,536writesfortheIDT72T20108,131,072writes
for the IDT72T20118 and 262,144 writes for the IDT72T20128. If both x10
Input and x10 Output bus Widths are selected, D = 65,536 writes for the
IDT72T2098, 131,072 writes for the IDT72T20108, 262,144 writes for the
IDT72T20118 and 524,288 writes for the IDT72T20128, respectively.
13
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
willloaddatafromtheSIinputintotheoffsetregisters.SCLKrunsatanominal
speedof10MHzatthemaximum.Theprogrammingsequencestartswithone
bitforeachSCLKrisingedge,startingwiththeEmptyOffsetLSBandending
withtheFullOffsetMSB.ThetotalnumberofbitsperdeviceislistedinFigure
3, Programmable Flag Offset Programming Sequence. See Figure 25,
LoadingofProgrammableFlagRegisters,forthetimingdiagramforthismode.
ThePAEandPAFcanshowavalidstatusonlyafterthecompletesetofbits(for
alloffsetregisters)hasbeenentered.Theregisterscanbereprogrammedas
longasthecompletesetofnewoffsetbitsisentered.
TABLE 3 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
IDT72T2098, 72T20108, 72T20118, 72T20128
FSEL1
FSEL0
Offsets n,m
H
L
H
L
H
H
L
L
255
127
63
7
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
thecurrentoffsetvalues.Similartoloadingoffsetvalues,setSRENLOWand
therisingedgeofSCLKwillsenddatafromtheoffsetregistersouttotheSOoutput
port.Wheninitializingareadtotheoffsetregisters,datawillbereadstartingfrom
thefirstlocationintheregister,regardlessofwhereitwaslastread.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summarizes
thecontrolpinsandsequenceforprogrammingoffsetregistersandreadingand
writingintotheFIFO.
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72T2098/
72T20108/72T20118/72T20128 have internal registers for these offsets.
TherearefourselectabledefaultoffsetvaluesduringMasterReset.Theseoffset
valuesareshowninTable3.Theoffsetvaluescanalsobeprogrammedserially
intotheFIFO.Toloadoffsetvalues,setSENLOWandtherisingedgeofSCLK
The offset registers may be programmed (and reprogrammed) any time
after Master Reset. Valid programming ranges are from 0 to D-1.
TABLE 4 STATUS FLAGS FOR IDT STANDARD MODE
IW = OW = x10
IDT72T2098
IDT72T20108
IDT72T20118
IDT72T20118
IDT72T20128
IDT72T20128
IW OW or
≠
IDT72T20108
FF PAF PAE EF
IDT72T2098
IW = OW = x20
0
0
0
0
0
H
H
H
H
L
H
H
H
L
L
L
L
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
H
H
H
H
Number of
Words in
FIFO
(32,769) to (65,536-(m+1))
(16,385) to (32,768-(m+1))
(65,537) to (131,072-(m+1)) (131,073) to (262,144-(m+1))
(262,145) to (524,288-(m+1))
(524,288-m) to 524,287
524,288
H
H
H
(262,144-m) to 262,143
(131,072-m) to 131,071
(32,768-m) to 32,767
32,768
(65,536-m) to 65,535
65,536
131,072
262,144
L
NOTE:
1. See table 3 for values for n, m.
TABLE 5 STATUS FLAGS FOR FWFT MODE
IW = OW = x10
IDT72T2098
IDT72T20108
IDT72T20118
IDT72T20118
IDT72T20128
IDT72T20128
IW OW or
≠
IDT72T20108
IR PAF PAE OR
IDT72T2098
IW = OW = x20
0
0
0
0
0
L
L
L
H
H
H
L
L
H
L
1 to n(1)
1 to n(1)
(32,770) to (65,537-(m+1))
(65,537-m) to 65,536
65,537
1 to n(1)
1 to n(1)
1 to n(1)
Number of
Words in
FIFO
(16,386) to (32,764-(m+1))
(65,538) to (131,073-(m+1)) (131,074) to (262,145-(m+1)) (262,146) to (524,289-(m+1))
H
H
H
L
(32,764-m) to 32,768
32,769
(131,073-m) to 131,072
131,073
(262,145-m) to 262,144
262,145
(524,289-m) to 524,288
524,289
L
L
L
L
L
H
5996 drw05
NOTE:
1. See table 3 for values for n, m.
2. Number of Words in FIFO = FIFO Depth + Output Register.
3. FWFT mode available only in Single Data Rate mode.
14
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72T2098
IDT72T20108
IDT72T20118
IDT72T20128
SCLK
WSDR RSDR WEN
X X 1
REN
SEN
SREN
WCLK RCLK
x10 to x10 Mode
All Other Modes
X
X
1
0
1
Serial Write to registers:
In SDR Mode:
Serial Write to registers:
In SDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
32 bits for the IDT72T2098
34 bits for the IDT72T20108
36 bits for the IDT72T20118
38 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Write to registers:
In DDR Mode:
Serial Write to registers:
In DDR Mode:
28 bits for the IDT72T2098
30 bits for the IDT72T20108
32 bits for the IDT72T20118
34 bits for the IDT72T20128
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
x10 to x10 Mode
All Other Modes
X
X
1
1
1
0
X
X
Serial Read from registers:
In SDR Mode:
Serial Read From registers:
In SDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
32 bits for the IDT72T2098
34 bits for the IDT72T20108
36 bits for the IDT72T20118
38 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial Read from registers:
In DDR Mode:
Serial Read from registers:
In DDR Mode:
30 bits for the IDT72T2098
32 bits for the IDT72T20108
34 bits for the IDT72T20118
36 bits for the IDT72T20128
28 bits for the IDT72T2098
30 bits for the IDT72T20108
32 bits for the IDT72T20118
34 bits for the IDT72T20128
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Write Memory (DDR)
Write Memory (SDR)
Read Memory (DDR)
1
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read Memory (SDR)
No Operation
X
X
1
1
X
X
X
X
X
5996 drw06
NOTES:
1. The programming sequence applies to both IDT Standard and FWFT modes.
2. When the input or output ports are in DDR mode, the depth is reduced by half but the overall density remains the same. For example, the IDT72T2098 in SDR mode is
32,768 x 20/65,536 x 10 = 655,360, in DDR mode the configuration becomes 16,384 x 40/32,768 x 20 = 655,360. In both cases, the total density are the same.
Figure 3. Programmable Flag Offset Programming Sequence
15
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
RETRANSMIT FROM MARK OPERATION
23,RetransmitfromMarkinDoubleDataRateMode,fortherelevanttiming
The Retransmit from Mark feature allows FIFO data to be read repeatedly diagram.
starting at a user-selected position. The FIFO is first put into retransmit mode
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
that will “mark” a beginning word and also set a pointer that will prevent edge when the MARK input is HIGH and OR is LOW. The rising RCLK edge
ongoing FIFO write operations from over-writing retransmit data. The retrans- marks the data present in the FIFO output register as the first retransmit data.
mit data can be read repeatedly any number of times from the “marked” The data is marked in pairs. The FIFO remains in retransmit mode until a
position. The FIFO can be taken out of retransmit mode at any time to allow rising RCLK edge occurs while MARK is LOW.
normal device operation. The “mark” position can be selected any number of
times, each selection over-writing the previous mark location.
Once a marked location has been set, a retransmit can be initiated by a
rising RCLK edge while the Retransmit input (RT) is LOW. REN must be
In Double Data Rate, data is always marked in pairs. That is, the unit of data HIGH (reads disabled) before bringing RT LOW. The device indicates the
read on the rising and falling edge of WCLK. If the data marked was read on start of retransmit setup by setting OR HIGH, preventing read operations.
the falling edge of RCLK, then the marked data will be the unit of data read from
When OR goes LOW, retransmit setup is complete and on the next rising
the rising and falling edge of that particular RCLK edge. Refer to Figure 23, RCLK edge (RT goes HIGH), the contents of the first retransmit location are
Retransmit from Mark in Double Data Rate Mode, for the timing diagram in loaded onto the output register. Since FWFTmode is selected, the first word
this mode. Retransmit operation is available in both IDT standard and FWFT appears on the outputs regardless of REN, a LOW on REN is not required for
modes.
the first word. Reading all subsequent words requires a LOW on REN to
During IDT standard mode the FIFO is put into retransmit mode by a Low- enable the rising RCLK edge. See Figure 24, Retransmit from Mark (FWFT
to-High transition on RCLK when the MARK input is HIGH and EF is HIGH. mode) for the relevant timing diagram.
The rising RCLK edge marks the data present in the FIFO output register as
Before a retransmit can be performed, there must be at least 1280 bits (or
the first retransmit data. Again, the data is marked in pairs. Thus if the data 160 bytes) of data between the write pointer and mark location.That is, 20 bits
marked was read on the falling edge of RCLK, the first part of retransmit will x64 for the x20 mode and 10 bits x128 for the x10 mode. Also, once the Mark
read out the data read on the rising edge of RCLK, followed by the data on the is set, the write pointer will not increment past the marked location, preventing
falling edge (the marked data). The FIFO remains in retransmit mode until a overwrites of retransmit data.
rising edge on RCLK occurs while MARK is LOW.
Once a marked location has been set, a retransmit can be initiated by a HSTL/LVTTL I/O
rising edge on RCLK while the Retransmit input (RT) is LOW. REN must be
This device supports both LVTTL and HSTL logic levels on the input and
HIGH (reads disabled) before bringing RT LOW. The device indicates the start outputsignals.IfLVTTLisdesired,aLOWontheHSTLpinwillsettheinputs
of retransmit setup by setting EF LOW, also preventing reads. WhenEF goes andoutputstoLVTTLmode.IfHSTLisdesired,aHIGHontheHSTLpinwill
HIGH, retransmit setup is complete and read operations may begin starting settheinputsandoutputstoHSTLmode.VREFistheinputvoltagereference
with the first unit of data at the MARK location. Since IDT standard mode is usedinHSTLmode.TypicallyalogicHIGHinHSTLwouldbeVref+0.2Vand
selected, every word read including the first “marked” word following a re- alogicLOWwouldbeVREF–0.2V.Table6illustrateswhichpinsareandare
transmit setup requires a LOW on REN.
notassociatedwiththisfeature.Notethatall“StaticPins”mustbetiedtoVccor
Note,writeoperationsmaycontinueasnormalduringallretransmitfunctions, GND. These pins are LVTTL only and are purely device configuration pins.
howeverwriteoperationstothe“marked”locationwillbeprevented.SeeFigure
TABLE 6 — I/O CONFIGURATION
HSTL SELECT
STATIC PINS
HIGH = HSTL
LOW = LVTTL
LVTTL ONLY
Write Port
Read Port
Signal Pins
Static Pins
Dn (I/P)
Qn (O/P)
RCLK (I/P)
REN (I/P)
RCS (I/P)
MARK (I/P)
OE (I/P)
EF/OR (O/P)
PAF (O/P)
SCLK (I/P)
SI (I/P)
TRST (I/P)
IW (I/P)
OW (I/P)
WCLK (I/P)
WEN (I/P)
WCS (I/P)
TDI (I/P)
PAE (O/P)
SO (O/P)
MRS (I/P)
PRS (I/P)
TCK (I/P)
TMS (I/P)
TDO (O/P)
SEN (I/P)
SREN (I/P)
HSTL (I/P)
FSEL1 (I/P)
FSEL0 (I/P)
FWFT (I/P)
WSDR (I/P)
RSDR (I/P)
FF/IR (O/P)
ERCLK (O/P)
EREN (O/P)
RT (I/P)
16
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
If FWFT mode has been selected, the OR flag will go HIGH on the rising
edge of RCLK that retransmit was initiated. OR will return LOW on the next
rising edge of RCLK, which signifies that retransmit setup is complete. Under
FWFT mode, the contents in the marked memory location will be loaded onto
the output register on the next rising edge of RCLK.To access all subsequent
data, a read operation will be required.
Subsequent retransmit operations may be performed, each time the read
pointer returning to the “marked” location. See Figure 24, Retransmit from
Mark (FWFT Mode) for the relevant timing diagram.
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 – Dn)
Data inputs for 20-bit wide data, (D0 – D19), or data inputs for 10-bit wide
data (D0 – D9).
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever theMRS input is taken to a LOW
state. Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
of the RAM array. PAE will go LOW and PAF will go HIGH.
If FWFT is LOW during Master Reset then IDT Standard mode along with
EF and FF are selected. EF will go LOW and FF will go HIGH, If FWFT is
HIGH, then the First Word Fall Through (FWFT) mode, along with IR and OR
are selected. OR will go HIGH and IR will go LOW.
MARK
The MARK input is used to select Retransmit mode of operation. On a rising
edge of RCLK while MARK is HIGH will mark the memory location of the data
currently present on the output register, in addition placing the device in
retransmit mode. Note, there must be a minimum of 1280 bits (or 160 bytes) of
data between the write pointer and mark location. That is, 20 bits x64 for the
x20 mode and 10 bits x128 for the x10 mode. Also, once the MARK is set, the
write pointer will not increment past the “marked” location until the MARK is
deasserted. This prevents “overwriting” of retransmit data.
All control settings such as OW, IW, WSDR, RSDR, FSEL0 and FSEL1 are
defined during the Master Reset cycle.
During a Master Reset the output register is initialized to all zeros. A Master
Reset is required after power up before a write operation can take place. MRS
is asynchronous.
The MARK input must remain HIGH during the whole period of retransmit
mode, a falling edge of RCLK while MARK is LOW will take the device out of
retransmit mode and into normal mode. Any number of MARK locations can
be set during FIFO operation, only the last marked location taking effect. Once
a mark location has been set the write pointer cannot be incremented past this
marked location. During retransmit mode write operations to the device may
continue without hindrance.
See Figure 8, Master Reset Timing, for the relevant timing diagram.
PARTIALRESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array. PAE goes LOW and PAF goes
HIGH.
Whichever mode was active at the time of Partial Reset will remain active
after Partial Reset. If IDT Standard Mode is active, then FF will go HIGH and
EF will go LOW. If the First Word FallThrough mode is active, thenOR will go
HIGH and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain un-
changed. The output register is initialized to all zeroes. PRS is asynchronous.
Partial Reset is useful for resetting the read and write pointers to zero without
affectingthevaluesoftheprogrammableflagoffsetsandthetimingmodeofthe
FIFO.
FIRST WORD FALL THROUGH (FWFT)
During Master Reset, the state of the FWFT input determines whether the
device will operate in IDT Standard mode or First Word Fall Through (FWFT)
mode.
If, at the time of Master Reset, FWFTis LOW, then IDT Standard mode will
be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO memory. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the outputs (Qn) to be read. It also uses Input Ready (IR) to
indicate whether or not the FIFO memory has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn after
three RCLK rising edges, bringing REN LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK. Note that
FWFT mode can only be used when the device is configured to Single Data
Rate (SDR) mode.
See Figure 9, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT (RT)
The Retransmit (RT) input is used in conjunction with the MARK input.
Together they provide a means by which data previously read out of the FIFO
can be reread any number of times. When the retransmit operation is selected
(i.e. after data has been marked), a rising edge on RCLK while RT is LOW will
reset the read pointer back to the memory location set by the user via the
MARK input.
If IDT Standard mode has been selected, the EF flag will go LOW on the
rising edge of RCLK that retransmit was initiated (i.e. rising edge of RCLK
while RT is LOW). EF will go back to HIGH on the next rising edge of RCLK,
which signifies that retransmit setup is complete. The next read operation will
access data from the “marked” memory location.
Subsequent retransmit operations may be performed, each time the read
pointer returning to the “marked” location. See Figure 23, Retransmit from
Mark in Double Data Rate Mode (IDT Standard Mode) for the relevant timing
diagram.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising and/or falling edge of the WCLK input.
If the Write Single Data Rate (WSDR) pin is selected, data will be written only
on the rising edge of WCLK, provided that WEN and WCS are LOW. If the
WSDR is not selected, data will be written on both the rising and falling edge of
WCLK, provided that WEN and WCS are LOW. Data setup and hold times
must be met with respect to the LOW-to-HIGH transition of the WCLK. It is
permissible to stop the WCLK. Note that while WCLK is idle, the FF, IR, and
17
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PAF flags will not be updated. The write and read clocks can either be Word to fall through to the output register.All subsequent words require that a
independent or coincident.
read operation to be executed using REN and RCS. The LOW-to-HIGH
transition of RCLK after the last word has been read from the FIFO will make
Output Ready (OR) go HIGH with a true read (RCLK with REN and RCS
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO RAM array LOW), inhibiting further read operations. REN is ignored when the FIFO is
on the rising edge of every WCLK cycle if the device is not full. Data is stored empty.
in the RAM array sequentially and independently of any ongoing read opera-
tion.
When WEN is HIGH, no new data is written in the RAM array on each
WCLK cycle.
READ SINGLE DATARATE (RSDR)
When the Read Single Data Rate pin is LOW, the read port will be set to
Single Data Rate mode. In this mode, all read operations are based only on
To prevent data overflow in the IDT Standard mode, FF will go LOW, the rising edge of RCLK, provided that REN and RCS are LOW. When RSDR
inhibiting further write operations. Upon the completion of a valid read cycle, is HIGH, the read port will be set to Double Data Rate mode. In this mode, all
FF will go HIGH, allowing a write to occur. The FF is updated by two WCLK read operations are based on both the rising and falling edge of RCLK,
cycles + tSKEW after the RCLK cycle.
provided that REN and RCS are LOW, on the rising edge of RCLK.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle, IR will go SERIAL CLOCK (SCLK)
LOW, allowing a write to occur. The IR flag is updated by two WCLK cycles +
The serial clock is used to load and read data in the programmable offset
registers. Data from the Serial Input (SI) can be loaded into the offset registers
tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either IDT Standard mode or on the rising edge of SCLK provided that SEN is LOW. Data can be read from
FWFT.
the offset registers via the Serial Output (SO) on the rising edge of SCLK
provided that SREN is LOW. The serial clock can operate at a maximum
frequency of 10MHz and its parameters are different than the FIFO system
WRITE SINGLE DATA RATE (WSDR)
When the Write Single Data Rate pin is LOW, the write port will be set to clock.
Single Data Rate mode. In this mode, all write operations are based only on
the rising edge of WCLK, provided that WEN and WCS are LOW. When SERIAL ENABLE (SEN)
WSDR is HIGH, the read port will be set to Double Data Rate mode. In this
The SEN input is an enable used for serial programming of the program-
mode, all write operations are based on both the rising and falling edge of mable offset registers. It is used in conjunction with SI and SCLK when pro-
WCLK, provided that WEN and WCS are LOW, on the rising edge of WCLK. gramming the offset registers. When SEN is LOW, data at the Serial In (SI)
input can be loaded into the offset register, one bit for each LOW-to-HIGH
READ CLOCK (RCLK)
transition of SCLK.
A read cycle is initiated on the rising and/or falling edge of the RCLK input.
When SEN is HIGH, the offset registers retain the previous settings and no
If the Read Single Data Rate (RSDR) pin is selected, data will be read only on offsets are loaded. SEN functions the same way in both IDT Standard and
the rising edge of RCLK, provided that REN and RCS are LOW. If the RSDR FWFT modes.
is not selected, data will be read on both the rising and falling edge of WCLK,
provided thatREN andRCS are LOW, on the rising edge of RCLK. Setup and SERIAL READ ENABLE (SREN)
hold times must be met with respect to the LOW-to-HIGH transition of the
The SREN output is an enable used for reading the value of the program-
RCLK. It is permissible to stop the RCLK. Note that while RCLK is idle, theEF/ mable offset registers. It is used in conjunction with SI and SCLK when reading
OR and PAE flags will not be updated. Write and Read Clocks can be inde- fromtheoffsetregisters. WhenSRENisLOW, datacanbereadoutoftheoffset
pendent or coincident.
register from the SO output, one bit for each LOW-to-HIGH transition of SCLK.
When SREN is HIGH, the reading of the offset registers will stop. When-
ever SREN is activated values in the offset registers are read starting from the
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM array into the first location in the offset registers and not from where the last offset value was
output register on the rising edge of every RCLK cycle if the device is not read. SREN functions the same way in both IDT Standard and FWFT modes.
empty.
When the REN input is HIGH, the output register holds the previous data SERIAL IN (SI)
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
This pin acts as a serial input for loading PAE and PAF offsets into the
programmable offset registers. It is used in conjunction with the Serial Clock
In IDT Standard mode, every word accessed at Qn, including the first word (SCLK) and the Serial Enable (SEN). Data from this input can be loaded into
written to an empty FIFO, must be requested using REN provided that the the offset register, one bit for each LOW-to-HIGH transition of SCLK provided
Read Chip Select (RCS) is LOW. When the last word has been read from the thatSEN is LOW.
FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations.
REN is ignored when the FIFO is empty. Once a write is performed, EF will go SERIAL OUT (SO)
HIGH allowing a read to occur. Both RCS and REN must be active LOW for
data to be read out on the rising edge of RCLK.
This pin acts as a serial output for reading the values of the PAE and PAF
offsets in the programmable offset registers. It is used in conjunction with the
In FWFT mode, the first word written to an empty FIFO automatically goes Serial Clock (SCLK) and the Serial Enable Output (SREN). Data from the
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW offset register can be read out using this pin, one-bit for each LOW-to-HIGH
after the first write. REN and RCS do not need to be asserted LOW for the First transition of SCLK provided that SREN is LOW.
18
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
OUTPUT ENABLE (OE)
OUTPUTS:
When Output Enable is LOW, the parallel output buffers receive data from
the output register. When OE is HIGH, the output data bus (Qn) goes into a
high-impedance state. During Master or Partial Reset the OE is the only input
that can place the output data bus into high-impedance. During reset the RCS
input can be HIGH or LOW and has no effect on the output data bus.
DATA OUT (Q0-Q19)
(Q0 – Q19) are data outputs for 20-bit wide data, or (Q0 – Q9) are data
outputs for 10-bit wide data.
FULL FLAG (FF/IR)
Thisisadualpurposepin.InIDTStandardmode,theFullFlag(FF)function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFF is HIGH, the FIFOis notfull. Ifnoreads are performed
afterareset(eitherMRS orPRS), FF willgoLOWafterDwrites totheFIFO.
Ifx20Inputorx20Outputbuswidthisselected,D=32,768fortheIDT72T2098,
65,536fortheIDT72T20108,131,072fortheIDT72T20118and262,144for
theIDT72T20128.Ifbothx10Inputandx10Outputbuswidthsareselected,
D = 65,536forthe IDT72T2098, 131,072forthe IDT72T20108, 262,144for
the IDT72T20118 and 524,288 for the IDT72T20128. See Figure 10, Write
Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing
information.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
whenmemoryspace is available forwritingindata. Whenthere is nolonger
anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations.Ifnoreads
areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writes
totheFIFO.Ifx20Inputorx20OutputbusWidthisselected,D = 32,769forthe
IDT72T2098,65,537fortheIDT72T20108,131,073fortheIDT72T20118and
262,145fortheIDT72T20128.Ifbothx10Inputandx10OutputbusWidthsare
selected, D = 65,537 for the IDT72T2098, 131,073 for the IDT72T20108,
262,145fortheIDT72T20118and524,289fortheIDT72T20128.SeeFigure
19,WriteTiming(FWFTMode),fortherelevanttiminginformation.
The IR status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFTmode, the
total number of writes necessary to deassert IR is one greater than needed to
assert FF in IDT Standard mode.
READ CHIP SELECT (RCS)
The Read Chip Select input provides synchronous control of the Read
output port. When RCS goes LOW, the next rising edge of RCLK causes the
Qn outputs to go to the low-impedance state. WhenRCS goes HIGH, the next
RCLK rising edge causes the Qn outputs to return to high-impedance. During
a Master or Partial Reset theRCS input has no effect on the Qn output bus, OE
is the only input that provides high-impedance control of the Qn outputs. IfOE
is LOW, the Qn data outputs will be low-impedance regardless of RCS until the
first rising edge of RCLK after a reset is complete. Then if RCS is HIGH the
data outputs will go to high-impedance.
The RCS input does not effect the operation of the flags. For example, when
the first word is written to an empty FIFO, theEF will still go from LOW to HIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of RCS. For this reason the user should pay extra
attention when a data word is written to an empty FIFO in FWFT mode. If RCS
is HIGH when an empty FIFO is written into, the first word will fall through to the
output register but will not be available on the Qn outputs because they are in
high-impedance. TheusermusttakeRCS activeLOWtoaccessthisfirstword,
placing the output bus in low-impedance. REN must remain HIGH for at least
one cycle after RCS has gone LOW. A rising edge of RCLK with RCS and
REN LOW will read out the next word. Care must be taken so as not to lose the
first word written to an empty FIFO when RCS is HIGH. Refer to Figure 22,
RCS and REN Read Operation (FWFT Mode). The RCS pin must also be
active (LOW) in order to perform a Retransmit. See Figure 18 for Read Cycle
and Read Chip Select Timing (IDT Standard Mode). See Figure 21 for Read
Cycle and Read Chip Select Timing (FWFT Mode).
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
writepointertothe“marked”location.Thisdiffersfromnormalmodewherethis
flagis acomparisonofthewritepointertothereadpointer.
WRITE CHIP SELECT (WCS)
The WCS disables all Write Port inputs (data only) if it is held HIGH. To
perform normal operations on the write port, the WCS must be enabled.
EMPTY FLAG (EF/OR)
Thisisadual-purposepin.IntheIDTStandardmode,theEmptyFlag(EF)
functionisselected.WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
readoperations.WhenEFisHIGH,theFIFOisnotempty.SeeFigure12,Read
Cycle, EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for
therelevanttiminginformation.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs.ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
lastwordfromtheFIFOmemorytotheoutputs.ORgoesHIGHonlywithatrue
read(RCLKwithREN=LOW).Thepreviousdatastaysattheoutputs,indicating
the last word was read. Further data reads are inhibited untilOR goes LOW
again. See Figure 20, Read Timing (FWFT Mode), for the relevant timing
information.
HSTL SELECT (HSTL)
The inputs that were listed in Table 6 can be setup to be either HSTL or
LVTTL. If HSTL is HIGH, then HSTL operation of those signals will be se-
lected. If HSTLis LOW , then LVTTLwill be selected.
BUS-MATCHING (IW, OW)
The pins IW, and OW are used to define the input and output bus widths.
DuringMasterReset, thestateofthesepinsisusedtoconfigurethedevicebus
sizes. See Table 1 for control settings.All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Table 7 for Bus-
Matching Write to Read Ratio.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode,ORisatripleregister-bufferedoutput.
FLAG SELECT BITS (FSEL0 and FSEL1)
Thesepinswillselectthefourdefaultoffsetvaluesforthe PAE and PAFflags
during Master Reset. The four possible settings are listed onTable 3. Note that
the status of these inputs should not change after Master Reset.
19
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
See Figure 30, Programmable Almost-EmptyFlagTiming(IDTStandard
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO andFWFTMode),fortherelevanttiminginformation.
reaches the almost-full condition. In IDT Standard mode, if no reads are
performedafterreset(MRS),PAFwillgoLOWafter(D-m)wordsarewritten ECHO READ CLOCK (ERCLK)
totheFIFO.Ifx20Inputorx20Outputbuswidthisselected,PAFwillgoLOW
The Echo Read Clock output is provided in both HSTLand LVTTLmode,
after (32,768-m) writes for the IDT72T2098, (65,536-m) writes for the selectable via HSTL. The ERCLK is a free-running clock output, it will always
IDT72T20108, (131,072-m) writes for the IDT72T20118 and (262,144-m) follow the RCLK input regardless of REN and RCS.
writes fortheIDT72T20128.Ifbothx10Inputandx10Outputbus widths are
The ERCLK output follows the RCLK input with an associated delay. This
selected, PAF will go LOW after (65,536-m) writes for the IDT72T2098, delay provides the user with a more effective read clock source when reading
(131,072-m) writes for the IDT72T20108, (262,144-m) writes for the data from the Qn outputs. This is especially helpful at high speeds when
IDT72T20118 and (524,288-m) writes for the IDT72T20128, respectively. variables within the device may cause changes in the data access times.
Theoffset“m”isthefulloffsetvalue.Thedefaultsettingforthisvalueislistedin These variations in access time maybe caused by ambient temperature, sup-
Table 3.
ply voltage, or device characteristics. The ERCLK output also compensates
InFWFTmode, ifx20Inputorx20Outputbuswidthisselected,PAFwillgo for any trace length delays between the Qn data outputs and receiving de-
LOW after (32,769-m) writes for the IDT72T2098, (65,537-m) writes for the vices inputs.
IDT72T20108, (131,073-m) writes for the IDT72T20118 and (262,145-m)
Any variations effecting the data access time will also have a corresponding
writes fortheIDT72T20128.Ifbothx10Inputandx10Outputbus widths are effect on the ERCLK output produced by the FIFO device, therefore the
selected, PAF will go LOW after (65,537-m) writes for the IDT72T2098, ERCLK output level transitions should always be at the same position in time
(131,073-m) writes for the IDT72T20108, (262,145-m) writes for the relative to the data outputs. Note, that ERCLK is guaranteed by design to be
IDT72T20118 and (524,289-m) writes for the IDT72T20128, respectively. slower than the slowest Qn, data output. Refer to Figure 4, Echo Read Clock
Theoffset misthefulloffsetvalue.Thedefaultsettingforthisvalueislistedin and Data Output Relationship, Figure 27, Echo Read Clock & Read Enable
Table 3.
SeeFigure29,ProgrammableAlmost-FullFlagTiming(IDTStandardand REN Operation for timing information.
FWFTMode),fortherelevanttiminginformation.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe ECHO READ ENABLE (EREN)
Operation in Double Data Rate Mode and Figure 28, Echo RCLK & Echo
writepointertothe“marked”location.Thisdiffersfromnormalmodewherethis
flagis acomparisonofthewritepointertothereadpointer.
TheEchoReadEnableoutputisprovidedinbothHSTLandLVTTLmode,
selectableviaHSTL.
The EREN output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO reading data from the Qn output port at high speeds. The EREN output is
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW controlled by internal logic that behaves as follows: The EREN output is active
whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset LOW for the RCLK cycle that a new word is read out of the FIFO. That is, a
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable3.
InFWFTmode, the PAE willgoLOWwhenthere are n+1words orless in are active, LOW and the FIFO is NOTempty.
theFIFO.Thedefaultsettingforthis valueis statedinTable3.
rising edge of RCLK will causeEREN to go active, LOW if both REN and RCS
RCLK
tERCLK
tERCLK
ERCLK
t
A
t
D
tD
t
A
Q
SLOWEST(3)
5996 drw07
NOTES:
1. REN is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
5. REN = RCS = OE = 0.
Figure 4. Echo Read Clock and Data Output Relationship
20
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
TABLE 7 — BUS-MATCHING WRITE TO READ RATIO
ONE WRITE TO ONE READ (1:1)
x20 DDR Input to x20 DDR Output
x20 SDR Input to x20 SDR Output
Configuration
Configuration
WSDR
H
RSDR
H
IW
L
OW
L
WSDR
L
RSDR
L
IW
L
OW
L
SDR Write Clock x20 Data In
SDR Read Clock x20 Data Out
DDR Write Clock x20 Data In
DDR Read Clock x20 Data Out
Positive Edge 1 D[19:0] <= W1 Positive Edge 1 Q[19:0] <= W1
Positive Edge 1 D[19:0] <= W1 Positive Edge 1 Q[19:0] <= W1
Negative Edge 1 D[19:0] <= W2 Negative Edge 1 Q[19:0] <= W2
x20 SDR Input to x10 DDR Output
x10 DDR Input to x20 SDR Output
Configuration
Configuration
WSDR
L
RSDR
H
IW
L
OW
H
WSDR
H
RSDR
L
IW
H
OW
L
DDR Write Clock x10 Data In
SDR Read Clock x20 Data Out
SDR Write Clock x20 Data In
DDR Read Clock x10 Data Out
Positive Edge 1 D[9:0] <= B1
Negative Edge 1 D[9:0] <= B2
Positive Edge 1 Q[19:10] <= B1
Positive Edge 1 Q[9:0] <= B2
Positive Edge 1 D[19:10] <= B1 Positive Edge 1 Q[9:0] <= B1
Positive Edge 1 D[9:0] <= B2
Negative Edge 1 Q[9:0] <= B2
x10 SDR Input to x10 SDR Output
x10 DDR Input to x10 DDR Output
Configuration
Configuration
WSDR
L
RSDR
L
IW
H
OW
H
WSDR RSDR
IW
H
OW
H
H
H
DDR Write Clock x10 Data In
DDR Read Clock x10 Data Out
SDR Write Clock x10 Data In
SDR Read Clock x10 Data Out
Positive Edge 1 D[9:0] <= B1
Negative Edge 1 D[9:0] <= B2
Positive Edge 1 Q[9:0] <= B1
Negative Edge 1 Q[9:0] <= B2
Positive Edge 1 D[9:0] <= B1 Positive Edge 1 Q[9:0] <= B1
ONE WRITE TO TWO READ (1:2)
x20 DDR Input to x20 SDR Output
x20 SDR Input to x10 SDR Output
Configuration
Configuration
WSDR
L
RSDR
L
IW
L
OW
H
WSDR RSDR
IW
L
OW
L
H
L
DDR Write Clock x20 Data In
SDR Read Clock x20 Data Out
SDR Write Clock x20 Data In
SDR Read Clock x10 Data Out
Positive Edge 1 D[19:0] <= W1
Negative Edge 1 D[19:0] <= W2
Positive Edge 1 Q[19:0] <= W1
Positive Edge 2 Q[19:0] <= W2
Positive Edge 1 D[19:10] <= B1 Positive Edge 1 Q[9:0] <= B1
Positive Edge 1 D[9:0] <= B2
Positive Edge 2 Q[9:0] <= B2
x20 DDR Input to x10 DDR Output
Configuration
x10 DDR Input to x10 SDR Output
WSDR RSDR
IW
L
OW
H
Configuration
H
H
WSDR
H
RSDR
L
IW
H
OW
H
DDR Write Clock x20 Data In
DDR Read Clock x10 Data Out
Positive Edge 1 D[19:10] <= B1 Positive Edge 1 Q[9:0] <= B1
Positive Edge 1 D[9:0] <= B2 Negative Edge 1 Q[9:0] <= B2
Negative Edge 1 D[19:10] <= B3 Positive Edge 2 Q[9:0] <= B3
Negative Edge 1 D[9:0] <= B4 Negative Edge 2 Q[9:0] <= B4
DDR Write Clock x10 Data In
SDR Read Clock x10 Data Out
Positive Edge 1 D[19:10] <= B1 Positive Edge 1 Q[9:0] <= B1
Negative Edge 1 D[9:0] <= B2 Positive Edge 2 Q[9:0] <= B2
21
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
TABLE 7 — BUS-MATCHING WRITE TO READ RATIO (CONTINUED)
ONE WRITE TO FOUR READ (1:4)
x20 DDR Input to x10 SDR Output
Configuration
WSDR
H
RSDR
L
IW
L
OW
L
DDR Write Clock x20 Data In
SDR Read Clock x10 Data Out
Positive Edge 1 D[19:10] <= B1 Positive Edge 1 Q[9:0] <= B1
Positive Edge 1 D[9:0] <= B2 Positive Edge 2 Q[9:0] <= B2
Negative Edge 1 D[19:10] <= B3 Positive Edge 3 Q[9:0] <= B3
Negative Edge 1 D[9:0] <= B4 Positive Edge 4 Q[9:0] <= B4
TWO WRITE TO ONE READ (2:1)
x20 SDR Input to x20 DDR Output
x10 DDR Input to x20 DDR Output
Configuration
Configuration
WSDR
L
RSDR
H
IW
L
OW
L
WSDR
H
RSDR
H
IW
H
OW
L
DDR Write Clock x10 Data In
DDR Read Clock x20 Data Out
SDR Write Clock x20 Data In
DDR Read Clock x20 Data Out
Positive Edge 1 D[9:0] <= B1 Positive Edge 1 Q[19:10] <= B1
Negative Edge 1 D[9:0] <= B2 Postive Edge 1 Q[9:0] <= B2
Positive Edge 1 D[19:0] <=W1 Positive Edge 1 Q[19:0] <= W1
Positive Edge 2 D[19:0] <=W2 Negative Edge 1 Q[19:0] <= W2
Positive Edge 2 D[9:0] <= B3 Negative Edge 1 Q[19:10] <= B3
Negative Edge 2 D[9:0] <= B4 Negative Edge 1 Q[9:0] <= B4
x10 SDR Input to x20 SDR Output
x10 SDR Input to x10 DDR Output
Configuration
Configuration
WSDR
L
RSDR
L
IW
H
OW
L
WSDR
L
RSDR
H
IW
H
OW
H
DDR Write Clock x10 Data In
SDR Read Clock x10 Data Out
SDR Write Clock x10 Data In
SDR Read Clock x20 Data Out
Positive Edge 1 D[9:0] <= B1 Positive Edge 1 Q[9:0] <= B1
Positive Edge 2 D[9:0] <= B3 Negative Edge 1 Q[9:0] <= B3
Positive Edge 1 D[19:10] <= B1 Positive Edge 1 Q[19:10] <= B1
Positive Edge 2 D[9:0] <= B2
Positive Edge 1 Q[9:0] <= B2
FOUR WRITE TO ONE READ (4:1)
x10 SDR Input to x20 DDR Output
Configuration
WSDR
L
RSDR
H
IW
H
OW
L
SDR Write Clock x10 Data In
DDR Read Clock x20 Data Out
Positive Edge 1 D[9:0] <= B1
Positive Edge 2 D[9:0] <= B2
Positive Edge 3 D[9:0] <= B3
Positive Edge 4 D[9:0] <= B4
Positive Edge 1 Q[19:10] <= B1
Positive Edge 1 Q[9:0] <= B2
Negative Edge 1 Q[19:0] <= B3
Negative Edge 1 Q[9:0] <= B4
22
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
TABLE 8 — TSKEW MEASUREMENT
Data Port
Status Flags
TSKEW Measurement
Configuration
DDR Input
to
EF & PAE
Negative Edge WCLK to
Positive Edge RCLK
DDR Output
FF & PAF
EF & PAE
Negative Edge RCLK to
Positive Edge WCLK
DDR Input
to
Negative Edge WCLK to
Positive Edge RCLK
SDR Output
FF & PAF
EF & PAE
Positive Edge RCLK to
Positive Edge WCLK
SDR Input
to
Positive Edge WCLK to
Positive Edge RCLK
DDR Output
FF & PAF
EF & PAE
Negative Edge RCLK to
Positive Edge WCLK
SDR Input
to
Positive Edge WCLK to
Positive Edge RCLK
SDR Output
FF & PAF
Positive Edge RCLK to
Positive Edge WCLK
23
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
JTAGTIMINGSPECIFICATION
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5996 drw08
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 5. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
SYSTEMINTERFACEPARAMETERS
Min. Max. Units
IDT72T2098
IDT72T20108
IDT72T20118
IDT72T20128
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
24
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T2098/72T20108/
72T20118/72T20128incorporatesthenecessarytapcontrollerandmodified
padcellstoimplementtheJTAG facility.
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The Figure belowshows the standardBoundary-ScanArchitecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5996 drw09
Figure 6. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
25
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-DR
Pause-IR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
5996 drw10
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 7. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overtheFIFOmemoryandmustberesetafterpowerupofthedevice. See
TRSTdescriptionformoredetailsonTAPcontrollerreset.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe
normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch
awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset
statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This
is the reason why the Test Reset (TRST) pin is optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
26
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
THE INSTRUCTION REGISTER
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
•
TheInstructionRegisterisa4bitfield(i.e.IR3,IR2,IR1,IR0)todecode16
differentpossibleinstructions. Instructionsaredecodedasfollows.
Hex
Value
Instruction
Function
TESTDATAREGISTER
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
0x02
0x01
0x03
0x0F
IDCODE
SelectChipIdentificationdataregister
SelectBoundaryScanRegister
JTAG
SAMPLE/PRELOAD
HI-IMPEDANCE
BYPASS
SelectBypassRegister
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
Table 8. JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
IDCODE
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe
TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
SAMPLE/PRELOAD
THE DEVICE IDENTIFICATION REGISTER
TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
entering and leaving the IC.
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
FortheIDT72T2098/72T20108/72T20118/72T20128,thePartNumber
fieldcontainsthefollowingvalues:
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand
selects the one-bit bypass register to be connected between TDI and TDO.
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI
toTDOwithoutaffectingtheconditionoftheICoutputs.
Device
Part# Field
04AB
IDT72T2098
IDT72T20108
IDT72T20118
IDT72T20128
04AA
04A9
04A8
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
theIC.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
IDT72T2098/108/118/128JTAGDeviceIdentificationRegister
27
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
MRS
REN
t
RSR
RSR
t
RSS
RSS
t
t
WEN
t
RSS
RSS
RSS
tRSR
FWFT(2)
t
FSEL0(2)
FSEL1
,
t
OW, IW(2)
tHRSS
HSTL(2
t
RSS
t
RSR
RSR
WSDR(2)
tRSS
t
RSDR(2)
t
RSS
RSS
RT
t
SEN
tRSS
SREN
EF/OR
FF/IR
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
t
RSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
RSF
PAE
PAF
t
tRSF
OE = HIGH
OE = LOW
Q0 - Qn
5996 drw11
NOTE:
1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
2. The status of these pins are latched in when the Master Reset pulse is LOW.
Figure 8. Master Reset Timing
28
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
t
RSS
RSS
SEN
t
SREN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
PAF
t
RSF
t
RSF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
5995 drw12
NOTE:
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 9. Partial Reset Timing
29
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK1
tCLKH1
NO WRITE
tCLKL1
NO WRITE
2
WCLK
1
1
(1)
2
(1)
tSKEW1
tDH
tSKEW1
tDS
tDH
tDS
DX+1
DX
D0
- D19
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
tENH
tENH
REN
RCS
tENS
t
A
tA
Q0
- Q19
NEXT DATA READ
DATA READ
5996 drw13
tRCSLZ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. OE = LOW, EF = HIGH.
3. WCS = LOW.
4. WCLK must be free running for FF to update.
Figure 10. Write Cycle and Full Flag Timing (IDT Standard Mode)
30
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
31
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK1
tCLKH1
tCLKL1
1
2
RCLK
REN
EF
tENS
tENS
tENH
tENH
tENS
t
ENH
NO OPERATION
NO OPERATION
tREF
tREF
tREF
t
A
tA
tA
D0
LAST WORD
D1
LAST WORD
Q
0
- Q19
tOLZ
tOHZ
tOLZ
tOE
OE
WCLK
WEN
(1)
SKEW1
t
tENS
tENH
tENH
tENS
tWCSS
tWCSH
WCS
tDS
tDH
tDH
tDS
D0
D1
D0 - D19
5996 drw15
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. First data word latency = tSKEW1 + 1*TRCLK + tREF.
3. RCS is LOW.
4. RCLK must be free running for EF to update.
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
32
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
33
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
34
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
35
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
36
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
37
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
2
1
RCLK
tENS
REN
RCS
tENS
tENS
tENS
tENH
tREF
tREF
EF
tRCSHZ
tRCSHZ
tA
tA
tRCSLZ
tRCSLZ
LAST DATA-1
LAST DATA
Q0 - Qn
t
SKEW1(1)
WCLK
tENS
tENH
WEN
tDS
tDH
Dn
Dx
5996 drw21
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. First data word latency = tSKEW1 + 1*TRCLK + tREF.
3. OE is LOW.
4. RCLK must be free running for EF to update.
Figure 18. Read Cycle and Read Chip Select (IDT Standard Mode)
38
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
39
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
40
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
41
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ERN
CRS
42
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
43
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
44
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
t
SCLK
tSCKH
t
SCKL
SENS
SCLK
tSENH
t
tENH
SEN
tSDH
t
SDS
BIT X(1)
BIT 1
BIT 1
BIT X(1)
SI
5996 drw28
EMPTY OFFSET
FULL OFFSET
NOTE:
1. In SDR mode, X = 16 for the IDT72T2098, X = 17 for the IDT72T20108, X = 18 for the IDT72T20118, X = 19 for the IDT72T20128 for X10 mode. X = 15 for the IDT72T2098,
X = 16 for the IDT72T20108, X = 17 for the IDT72T20118, X = 18 for the IDT72T20128 for all other modes.
2. In DDR mode, X = 15 for the IDT72T2098, X = 16 for the IDT72T20108, X = 17 for the IDT72T20118, X = 18 for the IDT72T20128 for X10 to X10 mode. X = 14 for the IDT72T2098,
X = 15 for the IDT72T20108, X = 16 for the IDT72T20118, X = 17 for the IDT 72T20128 for all other modes.
Figure 25. Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
SCLK
tSCKH
t
SCKL
SENS
SCLK
tSENH
t
tENH
SREN
t
SOA
t
SOA
BIT X(1)
BIT X(1)
BIT 0
BIT 0
SO
EMPTY OFFSET
FULL OFFSET
5996 drw29
NOTE:
1. In SDR mode, X = 15 for the IDT72T2098, X = 17 for the IDT72T20108, X = 18 for the IDT72T20118, X = 19 for the IDT72T20128 for X10 mode. X = 15 for the IDT72T2098,
X = 16 for the IDT72T20108, X = 17 for the IDT20118, X = 18 for the IDT72T20128 for all other modes.
2. In DDR mode, X = 15 for the IDT72T2098, X = 16 for the IDT72T20108, X = 17 for the IDT72T20118, X = 18 for the IDT20128, for X10 to X10 mode. X = 14 for the IDT72T72098,
X = 15 for the IDT72T20108, X = 16 for the IDT72T20118, X = 17 for the IDT72T20128 for all other modes.
3. Offset register values are always read starting from the first location in the offset register upon initiating SREN.
Figure 26. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes)
45
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
46
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
WCLK
tENS
tENH
WEN
tDS
t
DH
tDS
t
DH
tDS
tDH
Wn+1
Wn+2
Wn+3
D0 - Dn
tSKEW1
1
2
RCLK
b
e
h
a
d
g
c
i
f
tERCLK
ERCLK
tENS
tENH
REN
RCS
tENS
tCLKEN
tCLKEN
tCLKEN
tCLKEN
EREN
Qn
tA
tA
t
RCSLZ
HIGH-Z
Wn+1
Wn+2
Wn+3
tREF
tREF
OR
tA
tA
tA
O/P
Reg.
Wn
Last Word
Wn+1
Wn+2
Wn+3
5996 drw31
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in High-
Impedance state.
2. OE is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c.
Word Wn+1 falls through to the output register, OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
EREN goes HIGH, no new word has been placed on the output register on this cycle.
No Operation.
RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
d.
e.
f.
g.
h.
i.
REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
3. OE is LOW.
4. The truth table for EREN is shown below:
RCLK
OR
RCS
REN
EREN
↑
↑
↑
↑
↑
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
0
1
1
1
1
Figure 28. Echo RCLK and Echo REN Operation (FWFT Mode Only)
47
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLKL1
tCLKL1
WCLK
WEN
PAF
1
2
2
1
tENS
tENH
tPAFS
tPAFS
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
D - (m +1) words in FIFO(2)
t
SKEW3(3)
RCLK
tENH
tENS
5996 drw32
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard mode: if x20 Input or x20 Output bus Width is selected, D = 32,768 for the IDT72T2098, 65,536 for the IDT72T20108, 131,072 for the IDT72T20118, 262,144 for
the IDT72T20128. If both x10 Input and x10 Output bus Widths are selected, D = 65,536 for the IDT72T2098, 131,072 for the IDT72T20108, 262,144 for the IDT72T20118, 524,288
for the IDT72T20128.
In FWFT mode: if x20 Input or x20 Output bus Width is selected, D = 32,769 for the IDT72T2098, 65,537 for the IDT72T20108, 131,073 for the IDT72T20118, 262,145 for the IDT72T20128.
If both x10 Input and x10 Output bus Widths are selected, D = 65,537 for the IDT72T2098, 131,073 for the IDT72T20108, 262,145 for the IDT72T20118, 524,289 for the IDT72T20128.
3. PAF is asserted and updated on the rising edge of WCLK only.
4. tSKEW3 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW3, then the PAF deassertion time may be delayed one extra WCLK cycle.
5. RCS = LOW.
Figure 29. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH1
tCLKL1
WCLK
tENS
tENH
WEN
PAE
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n
words in FIFO(2)
n + 1 words in FIFO(3)
SKEW3(4)
,
n + 1 words in FIFO(2)
n + 2 words in FIFO(3)
,
tPAES
tPAES
t
1
2
1
2
RCLK
tENS
tENH
5996 drw33
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted and updated on the rising edge of RCLK only.
5. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then the PAE deassertion may be delayed one extra RCLK cycle.
6. RCS = LOW.
Figure 30. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
48
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
avoidedbycreatingcomposite flags, thatis, ANDingEF ofeveryFIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can
be created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
Figure 31 demonstrates a width expansion using two IDT72T2098/
72T20108/72T20118/72T20128devices. D0 -D19 fromeachdevice forma
40-bitwideinputbusandQ0-Q19fromeachdeviceforma40-bitwideoutput
bus. Any word width can be attained by adding additional IDT72T2098/
72T20108/72T20118/72T20128devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH
(FWFT)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
WRITE ENABLE (WEN)
IDT
IDT
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
72T2098
72T20108
72T20118
72T20128
72T2098
72T20108
72T20118
72T20128
#1
FULL FLAG/INPUT READY (FF/IR)
(1)
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
PROGRAMMABLE (PAF)
FIFO
#1
FIFO
#2
m + n
n
Qm+1 - Qn
DATA OUT
m
5996 drw34
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 31. Block Diagram of Width Expansion
For the x20 Input or x20 Output bus Width: 32,768 x 20, 65,536 x 20, 131,072 x 20 and 262,144 x 20
For both x10 Input and x10 Output bus Widths: 65,536 x 10, 131,072 x 10, 262,144 x 10 and 524,288 x 10
49
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
FWFT
TRANSFER CLOCK
FWFT
FWFT
WRITE CLOCK
WRITE ENABLE
READ CLOCK
RCLK
WCLK
WEN
IR
RCLK
WCLK
IDT
IDT
READ CHIP SELECT
RCS
OR
WEN
72T2098
72T20108
72T20118
72T20128
72T2098
72T20108
72T20118
72T20128
READ ENABLE
REN
INPUT READY
REN
RCS
OUTPUT READY
IR
OR
OUTPUT ENABLE
OE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
5996 drw35
Figure 32. Block Diagram of Depth Expansion in Single Data Rate Mode
For the x20 Input or x20 Output bus Width: 65,536 x 20, 131,072 x 20, 262,144 x 20 and 524,288 x 20
For both x10 Input and x10 Output bus Widths: 131,072 x 10, 262,144 x 10, 524,288 x 10 and 1,048,576 x 10
DEPTH EXPANSION CONFIGURATION IN SINGLE DATA RATE
(FWFT MODE ONLY)
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
The IDT72T2098 can easily be adapted to applications requiring depths
greaterthan32,768whenthe x20Inputorx20Outputbus widthis selected,
65,536fortheIDT72T20108,131,072fortheIDT72T20118and262,144for
the IDT72T20128. When both x10 Input and x10 Output bus widths are
selected, depths greater than 65,536 can be adapted for the IDT72T2098,
131,072fortheIDT72T20108,262,144fortheIDT72T20118and524,288for
theIDT72T20128.InFWFTmode,theFIFOscanbeconnectedinseries(the
dataoutputsofoneFIFOconnectedtothedatainputsofthenext)withnoexternal
logicnecessary.Theresultingconfigurationprovidesatotaldepthequivalent
tothesumofthedepthsassociatedwitheachsingleFIFO.Figure32showsa
depth expansion using two IDT72T2098/72T20108/72T20118/72T20128
devices.
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW1
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towrite a wordtofillit.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
inthedepthexpansionconfiguration.Also,thedevices mustbeoperatingin
SingleDataRatemodesincethatistheonlymodeavailableinFWFT.Thefirst
wordwrittentoanemptyconfigurationwillpassfromoneFIFOtothenext("ripple
down")untilitfinallyappearsattheoutputsofthelastFIFOinthechain–noread
operationisnecessarybuttheRCLKofeachFIFOmustbefree-running. Each
timethedatawordappearsattheoutputsofoneFIFO,thatdevice'sORlinegoes
LOW, enabling a write to the next FIFO in line.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
50
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BLANK
I(1)
Plastic Ball Grid Array (PBGA, BB208-1)
BB
Commercial Only
Commercial Only
4
5
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Commercial and Industrial
Commercial Only
6-7
10
L
Low Power
72T2098
32,768 x 20/65,536 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
72T20108 65,536 x 20/131,072 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
72T20118 131,072 x 20/262,144 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
72T20128 262,144 x 20/524,288 x 10 2.5V High-Speed TeraSyncTM DDR/SDR FIFO
5996 drw36
NOTE:
1. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order.
DATASHEETDOCUMENTHISTORY
03/01/2002
04/08/2002
04/24/2002
05/24/2002
11/21/2002
02/11/2003
03/20/2003
12/17/2003
pgs. 1, 4, 6, 8, 9, and 22.
pgs. 1, 8, 9, 11, 32-35, 41, 45-47, and 50.
pgs. 19, and 27.
pgs. 2, 6-9, and 12.
pgs. 1, and 10.
pgs. 7, 8, and 26.
pgs. 24, 26, 27, and 43.
pgs. 10, 30-33, 35-37, 43, and 48.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
51
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