IDT72T51243L7-5BBI [IDT]
FIFO, 64KX18, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256;
| 型号： | IDT72T51243L7-5BBI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 64KX18, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 先进先出芯片 |
| 文件： | 总11页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
IDT72T51233
2.5V MULTI-QUEUE FIFO (4 QUEUES)
18 BIT WIDE CONFIGURATION
589,824 bits, 1,179,648 bits and
2,359,296 bits
IDT72T51243
IDT72T51253
•
•
•
4 bit parallel flag status on both read and write ports
FEATURES:
Provides continuous PAE and PAF status of up to 4 Queues
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
- x18in to x18out
- x9in to x18out
- x18in to x9out
- x9in to x9out
FWFT mode of operation on read port
Packet Ready mode of operation
Partial Reset, clears data in single Queue
Expansion of up to 8 Multi-Queue devices in parallel is available
Power Down Input provides additional power savings in HSTL
and eHSTL modes.
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
•
Choose from among the following memory density options:
IDT72T51233
IDT72T51243
IDT72T51253
Total Available Memory = 589,824 bits
Total Available Memory = 1,179,648 bits
Total Available Memory = 2,359,296 bits
•
•
•
Configurable from 1 to 4 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
Independent Read and Write access per queue
User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL
User programmable via serial port
•
•
•
•
•
•
•
•
•
Default Multi-Queue device configurations
-IDT72T51233: 8,192 x 18 x 4Q
-IDT72T51243: 16,384 x 18 x 4Q
-IDT72T51253: 32,768 x 18 x 4Q
•
•
•
•
•
•
•
•
•
100% Bus Utilization, Read and Write on every clock cycle
200 MHz High speed operation (5ns cycle time)
3.6ns access time
Echo Read Enable & Echo Read Clock Outputs
Individual, Active queue flags (OV, FF, PAE, PAF, PR)
DATA PATH FLOW DIAGRAM
MULTI-QUEUE FIFO
RADEN
ESTR
WADEN
FSTR
RDADD
6
WRADD
Q0
REN
5
RCLK
EREN
WEN
WCLK
ERCLK
OE
Q
D
in
out
x9, x18
x9, x18
DATA OUT
DATA IN
OV
FF
Qmax
PAF
PAE
PAFn
PAEn
4
4
6115 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
OCTOBER 2, 2001
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6115/-
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFIFO(4QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
IftheuserdoesnotwishtoprogramtheMulti-Queuedevice,adefaultoptionis
availablethatconfiguresthedeviceinapredeterminedmanner.
BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster
Reset latches in all configuration setup pins and must be performed before
programmingofthedevicecantakeplace.APartialResetwillresetthereadand
writepointersofanindividualFIFOqueue,providedthatthequeueisselected
onboththe write portandreadportatthe time ofpartialreset.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided.TheseareoutputsfromthereadportoftheFIFOthatarerequiredfor
highspeeddatacommunication,toprovidetightersynchronizationbetweenthe
databeingtransmittedfromtheQnoutputsandthedatabeingreceivedbythe
input device. Data read from the read port is available on the output bus with
respecttoERENandERCLK,thisisveryusefulwhendataisbeingreadathigh
speed.
The Multi-Queue FIFO has the capability of operating its IO in either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the
IOSELinput.Thecoresupplyvoltage(VCC)totheMulti-Queueisalways2.5V,
howevertheoutputlevelscanbesetindependentlyviaaseparatesupply,VDDQ.
ThedevicesalsoprovideadditionalpowersavingsviaaPowerDownInput.
This input disables the write port data inputs when no write operations are
required.
DESCRIPTION:
The IDT72T51233/72T51243/72T51253Multi-Queue FIFOdevice is a
single chipwithinwhichanywhere between1and4discrete FIFOqueues
canbe setup.Allqueues withinthe device have a commondata inputbus,
(writeport)andacommondataoutputbus,(readport).Datawrittenintothe
write port is directed to a respective queue via an internal de-multiplex
operation,addressedbytheuser.Datareadfromthereadportisaccessed
froma respective queue via aninternalmultiplexoperation,addressedby
the user. Data writes and reads can be performed at high speeds up to
200MHz,withaccesstimesof3.6ns.Datawriteandreadoperationsaretotally
independent of each other, a queue maybe selected on the write port and
adifferentqueueonthereadportorbothportsmayselectthesamequeue
simultaneously.
The device provides FullflagandOutputValidflagstatus forthe queue
selectedforwriteandreadoperations respectively.AlsoaProgrammable
AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.
Two 4 bit programmable flag busses are available, providing status of all
queues,includingqueuesnotselectedforwriteorreadoperations,theseflag
busses provide an individual flag per queue.
BusMatchingisavailableonthisdevice,eitherportcanbe9bitsor18bits
wide.WhenBusMatchingisusedthedeviceensuresthelogicaltransferof
datathroughputinaLittleEndianmanner.
Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable
toprogramthetotalnumberofqueuesbetween1and4,theindividualqueue
depthsbeingindependentofeachother.Theprogrammableflagpositionsare
alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.
AJTAGtestportisprovided,heretheMulti-QueueFIFOhasafullyfunctional
BoundaryScanfeature,compliantwithIEEE1449.1StandardTestAccessPort
andBoundaryScanArchitecture.
SeeFigure1,Multi-QueueFIFOBlockDiagramforanoutlineofthefunctional
blockswithinthedevice.
2
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFIFO(4QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
D
in
x9, x18
D
- D
17
0
WCLK
WEN
INPUT
DEMUX
TMS
TDI
5
WRADD
WADEN
Write Control
Logic
JTAG
Logic
TDO
TCK
TRST
Write Pointers
PAF
General Flag
Monitor
FSTR
PAFn
4
FSYNC
Upto 4
FIFO
Queues
FXO
FXI
OV
Active Q
Flags
PAE
0.5 Mbit
1.1 Mbit
2.3 Mbit
Dual Port
Memory
Active Q
Flags
FF
PAF
PAE
General Flag
Monitor
4
SI
SO
SCLK
PAEn
ESTR
ESYNC
EXI
Serial
Multi-Queue
Programming
SENI
SENO
EXO
Read Pointers
FM
IW
6
Reset
Logic
RDADD
RADEN
NULL-Q
Read Control
Logic
OW
MAST
REN
RCLK
ID0
ID1
ID2
DF
Device ID
3 Bit
OUTPUT
MUX
PAE/ PAF
Offset
DFM
OUTPUT
REGISTER
EREN
PRS
MRS
ERCLK
6115 drw02
IOSEL
Vref
IO Level Control
&
Power Down
OE
Q
- Q
17
0
PD
Q
x9, x18
out
Figure 1. Multi-Queue Block Diagram
3
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFIFO(4QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINCONFIGURATION
A1 BALL PAD CORNER
A
D14
D15
D17
D13
D16
GND
D12
D11
GND
D10
D9
D7
D6
D5
D4
D3
D2
D1
TCK
TMS
TDO
TDI
ID1
ID0
Q0
Q3
Q2
Q6
Q5
Q4
Q9
Q8
Q12
Q11
Q14
Q13
Q15
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
FM
B
C
D
E
F
D0
TRST
D8
IOSEL
VDD
ID2
Q1
Q7
Q10
Q16
DNC
Q17
DNC
DNC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDQ
GND
GND
GND
GND
GND
GND
VDDQ VDDQ
VDD
VDD
VDD
GND
VDD
VDD
VDDQ
VDD
GND
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDD
GND
VDDQ
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
DNC
DNC
DNC
GND
DNC
DNC
DNC
DNC
G
H
J
VDD
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
GND
VDD
VDD
GND
GND
VDD
GND
GND
PD
GND
Null Q
GND
GND
GND
GND
GND
VDD
K
L
VREF
GND MASTER
SI
GND
DFM
DF
SO
VDD
VDD
IW
OW
M
N
P
R
SENO
SENI
OE
VDDQ
VDDQ
VDDQ
RDADD0 RDADD1
PRELIMINARY
WRADD1 WRADD0
SCLK
VDDQ
VDDQ VDDQ
VDD
DNC
DNC
VDD
FF
VDD
OV
VDD
VDDQ
VDDQ
DNC
DNC
DNC
VDDQ RDADD2 GND
GND
GND
GND
WRADD2 WADEN
RDADD5 RDADD6 RDADD7
PAE
PAF3
PAF2
PAF1
5
DNC
DNC
PAE3
PAE2
PAE1
13
WRADD6 WRADD5 FSYNC
FSTR
PAF0
4
DNC
ESTR
ESYNC
EXI
PAF
PRS
PR
EREN
ERCLK
RADEN
T
WRADD7
FXI
FXO
RCLK
PAE0
EXO
WEN
MRS
REN
WCLK
1
2
3
6
7
8
9
10
11
12
14
15
16
6115 drw03
PBGA (BB256-1, order code: BB)
TOP VIEW
NOTE:
1. DNC - Do Not Connect.
4
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFIFO(4QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
providesauserprogrammablealmostfullflagforall4FIFOqueuesandwhen
arespectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
for that queue. Conversely, the read port has an output valid flag, providing
statusofthedatabeingreadfromthequeueselectedonthereadport.Aswell
astheoutputvalidflagthedeviceprovidesadedicatedalmostemptyflag.This
almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.
The device provides a user programmable almost empty flag for all 4 FIFO
queuesandwhenarespectivequeueisselectedonthereadport,thealmost
emptyflagprovidesstatusforthatqueue.
DETAILEDDESCRIPTION
MULTI-QUEUE STRUCTURE
TheIDTMulti-QueueFIFOhasasingledatainputportandsingledataoutput
portwithupto4FIFOqueuesinparallelbufferingbetweenthetwoports.The
usercansetupbetween1and4FIFOQueueswithinthedevice.Thesequeues
canbeconfiguredtoutilizethetotalavailablememory,providingtheuserwith
fullflexibilityandabilitytoconfigurethequeuestobevariousdepths,indepen-
dentofoneanother.
MEMORYORGANIZATION/ALLOCATION
PROGRAMMABLE FLAG BUSSES
Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing
512x18or1,024x9bits.Whentheuserisconfiguringthenumberofqueues
andindividualqueue sizes the usermustallocate the memorytorespective
queues,inunitsofblocks,thatis,asinglequeuecanbemadeupfrom0tom
blocks,wheremisthetotalnumberofblocksavailablewithinadevice.Alsothe
total size ofanygiven queue mustbe inincrements of512x18or 1,024x 9.
Forthe IDT72T51233, IDT72T51243andIDT72T51253the TotalAvailable
Memoryis64,128and256blocksrespectively(ablockbeing512x18or1,024
x9).Ifanyportisconfiguredforx18buswidth,ablocksizeis512x18.Ifboth
thewriteandreadportsareconfiguredforx9buswidth,ablocksizeis1,024
x9.Queuescanbebuiltfromtheseblockstomakeanysizequeuedesiredand
any number of queues desired.
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost
fullflagstatusbusisprovided,thisbusis4bitswide.Also,analmostemptyflag
statusbusisprovided,againthisbusis4bitswide.Thepurposeoftheseflag
bussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels
within FIFO queues that may not be selected on the write or read port. As
mentioned,thedeviceprovidesalmostfullandalmostemptyregisters(program-
mable by the user) for each of the 4 FIFO queues in the device.
The4bitPAEnand4bitPAFnbussesprovideadiscretestatusoftheAlmost
EmptyandAlmostFullconditionsofall4queue's.Ifthedeviceisprogrammed
for less than 4 queue's, then there will be a corresponding number of active
outputs onthePAEnandPAFnbusses.
Theflagbussescanprovideacontinuousstatusofallqueues.Ifdevicesare
connectedinexpansionmodetheindividualflagbussescanbeleftinadiscrete
form,providingconstantstatusofallqueues,orthebussesofindividualdevices
canbe connectedtogethertoproduce a single bus of4bits. The device can
then operate in a "Polled" or "Direct" mode.
Whenoperatinginpolledmodetheflagbusprovidesstatusofeachdevice
sequentially,thatis,oneachrisingedgeofaclocktheflagbusisupdatedtoshow
thestatusofeachdeviceinorder.Therisingedgeofthewriteclockwillupdate
theAlmostFullbusandarisingedgeonthereadclockwillupdatetheAlmost
Emptybus.
Whenoperatingindirectmodethedevicedrivingtheflagbusisselectedby
theuser.Theuseraddresses thedevicethatwilltakecontrolofarespective
flagbus, these PAFnandPAEnflagbusses operatingindependentlyofone
another.AddressingoftheAlmostFullflagbus is doneviathewriteportand
addressingoftheAlmostEmptyflagbus is doneviathereadport.
BUS WIDTHS
TheinputportiscommontoallFIFOqueueswithinthedevice,asistheoutput
port.ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinput
portandoutputportcanbe eitherx9orx18bits wide, the readandwrite port
widthsbeingsetindependentlyofoneanother.Becausetheportsarecommon
toallqueuesthewidthofthequeuesisnotindividuallyset,sothattheinputwidth
of all queues are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete
FIFOqueueviathewritequeueselectaddressinputs.Conversely,databeing
readfromthedevicereadportisreadfromaqueueselectedviathereadqueue
selectaddressinputs.Datacanbesimultaneouslywrittenintoandreadfromthe
sameFIFOqueueordifferentFIFOqueues.Onceaqueueisselectedfordata
writes or reads, the writing and reading operation is performed in the same
mannerasconventionalIDTsynchronousFIFO’s,utilizingclocksandenables,
thereisasingleclockandenableperport.Whenaspecificqueueisaddressed
on the write port, data placed on the data inputs is written to that queue
sequentiallybasedontherisingedgeofawriteclockprovidedsetupandhold
timesaremet.Conversely,dataisreadontotheoutputportafteranaccesstime
from a rising edge on a read clock.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.
WhenaFIFOqueueisselectedontheoutputport,thenextwordinthatqueue
willautomaticallyfallthroughtotheoutputregister.Allsubsequentwordsfrom
thatqueuerequireanenabledreadcycle.Datacannotbereadfromaselected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the
lastwordfromtheprevious queuewillremainontheoutputregister.
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice
EXPANSION
ExpansionofMulti-Queuedevicesisalsopossible,upto8devicescanbe
connectedinaparallelfashionprovidingthepossibilityofbothdepthexpansion
or queue expansion. Depth Expansion means expanding the depths of
individual queues. Queue expansion means increasing the total number of
queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore
memoryblockswithinaMulti-Queuedevicecanbeallocatedtoincreasethe
depth of a queue. For example, depth expansion of 8 devices provides the
possibilityof8queuesof32Kx18deepwithintheIDT72T51233,64Kx18deep
withintheIDT72T51243and128Kx18deepwithintheIDT72T51253,each
queuebeingsetupwithinasingledeviceutilizingallmemoryblocksavailable
toproduceasinglequeue.ThisisthedeepestFIFOqueuethatcansetupwithin
a device.
For queue expansion of the 4 queue device, a maximum number of 32 (8
x 4) queues may be setup, each queue being 4K x18 or 2K x 9 deep, if less
queuesaresetup,thenmorememoryblockswillbeavailabletoincreasequeue
depthsifdesired.WhenconnectingMulti-Queuedevicesinexpansionmode
allrespectiveinputpins(data&control)andoutputpins(data& flags),should
be“connected”togetherbetweenindividualdevices.
5
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFIFO(4QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS
Symbol
Name
I/OTYPE
Description
D[17:0]
Din
DataInputBus
LVTTL
INPUT
These are the 18data inputpins. Data is writtenintothe device via these inputpins onthe risingedge
ofWCLKprovidedthatWENisLOW.Duetobusmatchingnotallinputsmaybeused,anyunusedinputs
shouldbetiedLOW.
DF(1)
DefaultFlag
DefaultMode
LVTTL
INPUT
IftheuserrequiresdefaultprogrammingoftheMulti-Queuedevice,thispinmustbesetupbeforeMaster
Reset andmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
(1)
DFM
LVTTL
INPUT
TheMulti-Queuedevicerequiresprogrammingaftermasterreset.Theusercandothisseriallyviathe
serialport,ortheusercanusethedefaultmethod.IfDFMisLOWatmasterresetthenserialmodewillbe
selected,ifHIGHthendefaultmodeisselected.
ERCLK
EREN
ESTR
RCLK Echo
HSTL-LVTTL ReadClockEchooutput,thisoutputgeneratesaclockbasedonthereadclockinput,thisisusedforSource
OUTPUT SynchronousclockingwherethereceivingdevicesutilizestheERCLKtoclockdataoutputfromtheFIFO.
REN Echo
HSTL-LVTTL ReadEnableEchooutput,canbeusedinconjunctionwiththeERCLKoutputtoloaddataoutputfromthe
OUTPUT FIFOintothe receivingdevice.
PAEn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK
andtheRDADDbustoselectadeviceforitsqueuestobeplacedontothe PAEnbusoutputs.Adevice
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.
ESYNC
EXI
PAEnBus Sync
LVTTL
ESYNCisanoutputfromtheMulti-QueuedevicethatprovidesasynchronizingpulseforthePAEnbus
OUTPUT duringPolledoperationofthePAEnbus.DuringPolledoperationeachdevicesqueuestatusflagsare
loadedontothePAEnbusoutputssequentiallybasedonRCLK.ThefirstRCLKrisingedgeloadsdevice1
ontoPAEn,thesecondRCLKrisingedgeloadsdevice2andsoon.DuringtheRCLKcyclethataselected
device is placed on to the PAEn bus, the ESYNC output will be HIGH.
PAEnBus
ExpansionIn
LVTTL
INPUT
TheEXIinputis usedwhenMulti-Queuedevices areconnectedinexpansionmodeandPolledPAEn/
bus operationhas beenselected. EXIofdevice ‘N’connects directlytoEXOofdevice ‘N-1’. The EXI
receivesatokenfromthepreviousdeviceinachain.InsingledevicemodetheEXIinputshouldbetied
LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheEXIinput
shouldbeconnectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
EXO
PAEnBus
ExpansionOut
LVTTL
EXOisanoutputthatisusedwhenMulti-QueuedevicesareconnectedinexpansionmodeandPolled
OUTPUT PAEnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.This
pinpulsesHIGHwhendeviceNplacesitsPAEstatusontothePAEnbuswithrespecttoRCLK.Thispulse
(token)isthenpassedontothenextdeviceinthechain‘N+1’andonthenextRCLKrisingedgethefirst
quadrantofdevice N+1willbe loadedontothe PAEnbus. This continues throughthe chainandEXO
ofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeachdeviceinthe
chainprovidessynchronizationtotheuserofthisloopingevent.
FF
Full Flag
LVTTL
This pinprovides thefullflagoutputfortheactiveFIFOqueue,thatis,thequeueselectedontheinput
OUTPUT portforwrite operations, (selectedvia WCLK, WRADDbus andWADEN). Onthe WCLKcycle aftera
queueselection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueue
onthenextcycleprovidedFFisHIGH.ThisflaghasHigh-Impedancecapability,thisisimportantduring
expansionofdevices,whentheFFflagoutputofupto8devicesmaybeconnectedtogetheronacommon
line.ThedevicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutput
intoHigh-Impedance.Whenaqueueselectionismadeonthewriteportthisoutputwillswitchfrom
High-ImpedancecontrolonthenextWCLKcycle.ThisflagissynchronizedtoWCLK.
(1)
FM
Flag Mode
LVTTL
INPUT
Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe
FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled
orDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.
FSTR
PAFn Flag Bus
Strobe
LVTTL
INPUT
IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK
andtheWRADDbustoselectadeviceforitsqueuestobeplacedontothe PAFnbusoutputs.Adevice
addressedviatheWRADDbus is selectedontherisingedgeofWCLKprovidedthatFSTRis HIGH.If
Polledoperationshasbeenselected,FSTRshouldbetiedinactive,LOW.
6
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFIFO(4QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
FSYNC
PAFn Bus Sync
LVTTL
FSYNCisanoutputfromtheMulti-QueuedevicethatprovidesasynchronizingpulseforthePAFnbus
OUTPUT duringPolledoperationofthePAFnbus.DuringPolledoperationeachquadrantofqueuestatusflags
is loadedontothePAFnbus outputs sequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads
device1ontothePAFnbusoutputs,thesecondWCLKrisingedgeloadsdevice2andsoon.Duringthe
WCLKcycle thata selecteddevice is placedontothe PAFnbus, the FSYNCoutputwillbe HIGH.
FXI
PAFnBus
ExpansionIn
LVTTL
INPUT
The FXIinputis usedwhenMulti-Queue devices are connectedinexpansionmode andPolledPAFn
bus operation has been selected . FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receivesatokenfromthepreviousdeviceinachain.InsingledevicemodetheFXIinputshouldbetied
LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheFXIinput
shouldbeconnectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
FXO
PAFnBus
ExpansionOut
LVTTL
FXOisanoutputthatisusedwhenMulti-QueuedevicesareconnectedinexpansionmodeandPolled
OUTPUT PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This
pinpulsesHIGHwhendeviceNplacesitsPAFstatusontothePAFnbuswithrespecttoWCLK.Thispulse
(token)isthenpassedontothenextdeviceinthechain‘N+1’andonthenextWCLKrisingedgethefirst
quadrantofdevice N+1willbe loadedontothe PAFnbus. This continues throughthe chainandFXO
ofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdeviceinthe
chainprovidessynchronizationtotheuserofthisloopingevent.
(1)
ID[2:0]
Device ID Pins
LVTTL
INPUT
Forthe4QMulti-QueuedevicetheWRADDaddressbusis5bitsandRDADDaddressbusis6bitswide.
Whenaqueueselectiontakesplacethe3MSB’softhisaddressbusareusedtoaddressthespecificdevice
(theLSB’sareusedtoaddressthequeuewithinthatdevice).Duringwrite/readoperationsthe3MSB’s
oftheaddressarecomparedtothedeviceIDpins.ThefirstdeviceinachainofMulti-Queue’s(connected
inexpansionmode),maybesetupas‘000’,thesecondas‘001’andsoonthroughtodevice8whichis
‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould
besetupas‘000’andthe3MSB’softheWRADDandRDADDaddressbussesshouldbetiedLOW.The
ID[2:0]inputssetuparespectivedevicesIDduringmasterreset.TheseIDpinsmustnottoggleduring
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
IOSEL
IOSelect
LVTTL
INPUT
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
required then IOSEL should be tied LOW. If LVTTL I/O are required then it should be tied HIGH.
(1)
IW
InputWidth
MasterDevice
LVTTL
INPUT
IWselectsthebuswidthforthedatainputbus.IfIWisLOWduringaMasterResetthenthebuswidth
is x18, if HIGH then it is x9.
(1)
MAST
LVTTL
INPUT
ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe
MasterdeviceoraSlave.Ifthis pinis HIGH,thedeviceis themaster,ifitis LOWthenitis aSlave.The
masterdeviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgoto
High-Impedance,preventingbuscontention.IfaMulti-Queuedeviceisbeingusedinsingledevicemode,
thispinmustbesetHIGH.
MRS
MasterReset
LVTTL
INPUT
AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
aftermasterreset.
NULL-Q
OE
NullQueueSelect HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD
INPUT
address bus toaddress the Null-Q.
OutputEnable
LVTTL
INPUT
TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontroloftheMulti-Queue
dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswillbe
inaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbein
HighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbein
HighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-
stateofthatrespectivedevice.
OV
OutputValidFlag
LVTTL
ThisoutputflagprovidesoutputvalidstatusforthedatawordpresentontheMulti-QueueFIFOdataoutput
OUTPUT port,Qout.Thisflagistherefore,2-stagedelayedtomatchthedataoutputpathdelay.Thatis,thereis
a2RCLKcycledelayfromthetimeagivenqueueisselectedforreads,tothetimetheOVflagrepresents
thedatainthatrespectivequeue.Whenaselectedqueueonthereadportisreadtoempty,theOVflag
willgoHIGH,indicatingthatdataontheoutputbus is notvalid.The OVflagalsohas High-Impedance
capability,requiredwhenmultipledevices areusedandtheOVflags aretiedtogether.
7
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFIFO(4QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
(1)
OW
OutputWidth
LVTTL
INPUT
OWselectsthebuswidthforthedataoutputbus.IfOWisLOWduringaMasterResetthenthebuswidth
is x18, if HIGH then it is x9.
PAE
Programmable
Almost-EmptyFlag
LVTTL ThispinprovidestheAlmost-EmptyflagstatusfortheFIFOqueuethathasbeenselectedontheoutput
OUTPUT portforreadoperations,(selectedviaRCLK,RDADDandRADEN).ThispinisLOWwhentheselected
FIFOqueuealmost-empty.This flagoutputmaybeduplicatedononeofthe PAEnbus lines.This flag
is synchronizedtoRCLK.
PAEn
Programmable
Almost-EmptyFlag
Bus
LVTTL Onthe4QdevicethePAEnbusis4bitswide.ThisoutputbusprovidesPAEstatusofall4queues,withina
OUTPUT selecteddevice.DuringFIFOread/writeoperationstheseoutputsprovideprogrammableemptyflagstatus
ineitherdirectorpolledmode.Themodeofflagoperationisdeterminedduringmasterresetviathestateof
theFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansionof
Multi-Queuedevices.DuringdirectoperationthePAEnbusisupdatedtoshowthePAEstatusofqueues
within a selected device. Selection is made using RCLK, ESTR and Flag Bus RDADD. During Polled
operationthePAEnbusisloadedwiththePAEstatusofMulti-QueueFIFOdevicessequentiallybased
on the rising edge of RCLK.
PAF
Programmable
Almost-FullFlag
LVTTL ThispinprovidestheAlmost-FullflagstatusfortheFIFOqueuethathasbeenselectedontheinputportfor
OUTPUT writeoperations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselectedFIFO
queueis almost-full.This flagoutputmaybeduplicatedononeofthePAFnbuslines.Thisflagis
synchronizedtoWCLK.
PAFn
Programmable
LVTTL Onthe4QdevicethePAFnbusis4bitswide.ThisoutputbusprovidesPAFstatusofall4queues,withina
Almost-FullFlagBus OUTPUT selecteddevice.DuringFIFOread/writeoperationstheseoutputsprovideprogrammablefullflagstatus,in
eitherdirectorpolledmode.Themodeofflagoperationisdeterminedduringmasterresetviathestateof
theFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansionof
Multi-Queuedevices.DuringdirectoperationthePAFnbusisupdatedtoshowthePAFstatusofaqueues
withinaselecteddevice.Selectionis madeusingWCLK,FSTR,WRADDandWADEN.During
PolledoperationthePAFnbusisloadedwiththePAFstatusofMulti-QueueFIFOdevicessequentially
basedonthe risingedge ofWCLK.
PD
Power Down
HSTL This inputis usedtoprovide additionalpowersavings. Whenthe device I/Ois setupforHSTL/eHSTL
INPUT modeaHIGHonthePDinputdisablesthedatainputsonthewriteportonly,providingsignificantpower
savings. In LVTTL mode this pin has no operation
PRS
PartialReset
LVTTL APartialResetcanbeperformedonasinglequeueselectedwithintheMulti-Queuedevice.BeforeaPartial
INPUT Resetcanbe performedona queue, thatqueue mustbe selectedonboththe write portandreadport
2clockcycles beforetheresetis performed.APartialResetis thenperformedbytakingPRSLOWfor
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
thefirstmemorylocation,noneofthedevicesconfigurationwillbechanged.
Q[17:0]
Qout
DataOutputBus
LVTTL Thesearethe18dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge
OUTPUT ofRCLKprovidedthatRENis LOW,OEis LOWandtheFIFOqueueis selected.Duetobus matching
notalloutputs maybeused,anyunusedoutputs shouldnotbeconnected.
RADEN
RCLK
ReadAddress Enable LVTTL The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to
INPUT be read from. A FIFO queue addressed via the RDADD bus is selected on the rising edge of RCLK
provided that RADEN is HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR.
ReadClock
LVTTL WhenenabledbyREN,therisingedgeofRCLKreadsdatafromtheselectedFIFOqueueviatheoutput
INPUT busQout.TheFIFOqueuetobereadisselectedviatheRDADDaddressbusandarisingedgeofRCLK
whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe
devicetobeplacedonthePAEnbusduringdirectflagoperation.DuringpolledflagoperationthePAEn
bus is cycledwithrespecttoRCLKandtheESYNCsignalis synchronizedtoRCLK.ThePAE andOV
outputsareallsynchronizedtoRCLK.DuringdeviceexpansiontheEXOandEXIsignalsarebasedon
RCLK.RCLKmustbecontinuous andfree-running.
RDADD
[5:0]
Read Address Bus
LVTTL For the 4Q device the RDADD bus is 6 bits. The RDADD bus is a dual purpose address bus. The first
INPUT functionofRDADDis toselectaFIFOqueuetobereadfrom.Theleastsignificant2bits ofthebus,
RDADD[1:0] are used to address 1 of 4 possible queues within a Multi-Queue device. Address pin,
RDADD[2]providestheuserwithaNull-Qaddress.Iftheuserdoesnotwishtoaddressoneofthe4queues,
8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFIFO(4QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
RDADD
[5:0]
(Continued)
Read Address Bus
LVTTL aNull-Qcanbeaddressedusingthispin.TheNull-Qoperationisdiscussedinmoredetaillater.Themost
INPUT significant3bits,RDADD[5:3]areusedtoselect1of8possibleMulti-Queuedevicesthatmaybeconnected
inexpansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent
ontheRDADDbuswillbeselectedonarisingedgeofRCLKprovidedthatRADENisHIGH,(note,that
datacanbeplacedontotheQoutbus,readfromthepreviouslyselectedFIFOqueueonthisRCLKedge).
On the next rising RCLK edge after a read queue select, a data word from the previous queue will be
placedontotheoutputs,Qout,regardlessoftheRENinput.TwoRCLKrisingedgesafterreadqueueselect,
datawillbeplacedontotheQoutoutputsfromthenewlyselectedqueue,regardlessofRENduetothe
firstwordfallthrougheffect.
ThesecondfunctionoftheRDADDbusistoselectthedeviceofFIFOqueuestobeloadedontothePAEn
bus duringstrobedflagmode.Themostsignificant3bits,RDADD[5:3]areagainusedtoselect1of8
possibleMulti-Queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsRDADD[2:0]are
don’tcareduringdeviceselection.ThedeviceaddresspresentontheRDADDbuswillbeselectedonthe
risingedgeofRCLKprovidedthatESTRisHIGH,(note,thatdatacanbeplacedontotheQoutbus,read
fromthepreviouslyselectedFIFOQonthisRCLKedge).PleaserefertoTable2fordetailsonRDADDbus.
REN
ReadEnable
LVTTL The RENinputenables readoperations fromaselectedFIFOqueuebasedonarisingedgeofRCLK.
INPUT Aqueue tobe readfromcanbe selectedvia RCLK, RADENandthe RDADDaddress bus regardless
ofthestateofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond
RCLKcycle afterqueue selectionregardless ofRENdue tothe FWFToperation. Areadenable is not
required to cycle the PAEn bus (in polled mode) or to select the device , (in direct mode).
SCLK
SerialClock
LVTTL IfserialprogrammingoftheMulti-Queuedevicehasbeenselectedduringmasterreset,theSCLKinput
INPUT clockstheserialdatathroughtheMulti-Queuedevice.DatasetupontheSIinputisloadedintothedevice
ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed
theSCLKofalldevices shouldbeconnectedtothesamesource.
SENI
SerialInputEnable
LVTTL DuringserialprogrammingofaMulti-Queuedevice,dataloadedontotheSIinputwillbeclockedintothe
INPUT part(via a risingedge ofSCLK), providedthe SENIinputofthatdevice is LOW. Ifmultiple devices are
cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loadingofagivendeviceiscomplete,itsSENOoutputgoesLOW,allowingthenextdeviceinthechain
tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.
SENO
SerialOutputEnable LVTTL ThisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingoftheMulti-Queuedevice
OUTPUT hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso
goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENOoutput
shouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthe
firstdeviceiscomplete,SENOwillgoLOW,therebytakingtheSENIinputofthenextdeviceLOWand
soonthroughoutthe chain. Whena givendevice inthe chainis fullyprogrammedthe SENO output
essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.
WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.
SI
SerialIn
LVTTL DuringserialprogrammingthispinisloadedwiththeserialdatathatwillconfiguretheMulti-Queuedevices.
INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connectstotheSIpinofthesecondandsoon.TheMulti-Queuedevicesetupregistersareshiftregisters.
SO
SerialOut
LVTTL Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain
OUTPUT tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe
chain. The SOofthe finaldevice ina chainshouldnotbe connected.
TCK
TDI
JTAGClock
LVTTL ClockinputforJTAGfunction. TMSandTDIare sampledonthe risingedge ofTCK. TDOis outputon
INPUT thefallingedgeofTCK.
TestDataInput
LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.
INPUT This is alsothedatafortheInstructionRegister,JTAGIDRegisterandBypass Register.
9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T51233/72T51243/72T512532.5V,MULTI-QUEUEFIFO(4QUEUES)
18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
TDO
TestDataOutput
LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.
INPUT ThisoutputisinHigh-ImpedanceexceptwhenshiftingdatawhileinSHIFT-DRandSHIFT-IRcontroller
states.
TMS
JTAGModeSelect
JTAGReset
LVTTL TMSis a serialinputpin. Bits are seriallyloadedonthe risingedge ofTCK, whichselects 1of5modes
INPUT ofoperationforthe JTAGboundaryscan.
TRST
WADEN
LVTTL TRSTistheasynchronousresetpinfortheJTAGcontroller.IftheJTAGportisnotutilized,TRSTshould
INPUT be tiedtoGND.
WriteAddressEnable LVTTL TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto
INPUT be written in to. A FIFO queue addressed via the WRADD bus is selected on the rising edge of WCLK
providedthatWADENis HIGH. WADENcannotbe HIGHforthe same WCLKcycle as FSTR.
WCLK
WriteClock
LVTTL WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheselectedFIFOqueueviatheinput
INPUT bus, Din. The FIFO queue to be written to is selected via the WRADD address bus and a rising edge
ofWCLKwhileWADENisHIGH.ArisingedgeofWCLKinconjunctionwithFSTRandWRADDwillalso
selectthedevicetobeplacedonthePAFnbusduringdirectflagoperation.Duringpolledflagoperation
thePAFnbusiscycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.ThePAFn,
PAFandFFoutputs areallsynchronizedtoWCLK.DuringdeviceexpansiontheFXOandFXIsignals
are basedonWCLK. The WCLKmustbe continuous andfree-running.
WEN
WriteEnable
LVTTL The WEN input enables write operations to a selected FIFO queue based on a rising edge of WCLK.
INPUT AqueuetobewrittentocanbeselectedviaWCLK,WADENandtheWRADDaddress bus regardless
ofthestateofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLK
cycleafterqueueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFn
bus (in polled mode) or to select the device , (in direct mode).
WRADD
[4:0]
WriteAddressBus
LVTTL Forthe 4Qdevice the WRADDbus is 5bits. The WRADDbus is a dualpurpose address bus. The first
INPUT functionofWRADDistoselectaFIFOqueuetobewrittento.Theleastsignificant2bitsofthebus,
WRADD[1:0]areusedtoaddress1of4possiblequeueswithinaMulti-Queuedevice.Themostsignificant
3bits,WRADD[4:2]areusedtoselect1of8possibleMulti-Queuedevices thatmaybeconnectedin
expansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent
ontheWRADDbuswillbeselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,that
datapresentontheDinbuscanbewrittenintothepreviouslyselectedFIFOqueueonthisWCLKedge
andonthenextrisingWCLKalso,providingthatWENisLOW).TwoWCLKrisingedgesafterwritequeue
select,datacanbewrittenintothenewlyselectedqueue.
The secondfunctionofthe WRADDbus is toselectthe device ofFIFOqueues tobe loadedontothe
PAFnbusduringstrobedflagmode.Themostsignificant3bits,WRADD[4:2]areagainusedtoselect
1of8possibleMulti-Queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsWRADD[1:0]
aredon’tcareduringdeviceselection.ThedeviceaddresspresentontheWRADDbuswillbeselected
ontherisingedgeofWCLKprovidedthatFSTRisHIGH,(note,thatdatacanbewrittenintothepreviously
selectedFIFO queue on this WCLKedge). Please refertoTable 1 for details onthe WRADD bus.
VCC
+2.5VSupply
Power These are VCC power supply pins and must all be connected to a +2.5V supply rail.
VDDQ
O/PRailVoltage
Power Thesepinsmustbetiedtothedesiredoutputrailvoltage.ForLVTTLI/Othesepinsmustbeconnected
to+2.5V,forHSTLthesepinsmustbeconnectedto+1.5VandforeHSTLthesepinsmustbeconnected
to+1.8V.
GND
Vref
GroundPin
Power These are Ground pins and must all be connected to the GND supply rail.
ReferenceVoltage
HSTL ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable
INPUT "RecommendedDCOperatingConditions". The inputprovides the reference levelforHSTL/eHSTL
inputs. ForLVTTLI/Omode this inputshouldbe tiedtoGND.
NOTE:
1. Inputs should not change after Master Reset.
10
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BB
Plastic Ball Grid Array (PBGA, BB256-1)
5
6
7-5
Commercial Only
Commercial & Industrial
Commercial & Industrial
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Low Power
L
72T51233 589,824 bits 2.5V Multi-Queue FIFO
72T51243 1,179,648 bits 2.5V Multi-Queue FIFO
72T51253 2,359,296 bits 2.5V Multi-Queue FIFO
6115 drw32
NOTE:
1. Industrial temperature range product for 6ns and 7-5ns speed grades are available as a standard device. All other speed grades available by special order.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
11
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