IDT72V13081L15PFI8 [IDT]
FIFO, 2KX8, 10ns, Synchronous, CMOS, PQFP32, PLASTIC, TQFP-32;
| 型号： | IDT72V13081L15PFI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 2KX8, 10ns, Synchronous, CMOS, PQFP32, PLASTIC, TQFP-32 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总9页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT MULTIMEDIA FIFO
256 x 8, 512 x 8,
1,024 x 8, 2,048 x 8,
and 4,096 x 8
IDT72V10081, IDT72V11081
IDT72V12081, IDT72V13081
IDT72V14081
DESCRIPTION
FEATURES
TheIDT72V10081/72V11081/72V12081/72V13081/72V14081devices
arelow-powerFirst-In,First-Out(FIFO)memorieswithclockedreadandwrite
controls. These devices have a 256, 512, 1,024, 2,048 and 4,096 x 8-bit
memoryarray,respectively.TheseFIFOsareapplicableforawidevarietyof
databufferingneedssuchasgraphicsandinterprocessorcommunication.
These FIFOs have 8-bit input and output ports. The input port is
controlledbya free-runningclock(WCLK)and Write Enable pin(WEN).
Data is writtenintothe Multimedia FIFOoneveryrisingclockedge when
the Write Enable pinis asserted.The outputportis controlledbyanother
clock pin (RCLK) and Read Enable pin (REN). The Read Clock can be
tiedtothe Write Clockforsingle clockoperationorthe twoclocks canrun
asynchronous ofone anotherfordual-clockoperation.AnOutputEnable
pin(OE)is providedonthe readportforthree-state controlofthe output.
The Multimedia FIFOs have two fixed flags, Empty (EF) and Full (FF).
TheseFIFOs arefabricatedusingIDT's submicronCMOStechnology.
• 256 x 8-bit organization array (IDT72V10081)
• 512 x 8-bit organization array (IDT72V11081)
• 1,024 x 8-bit organization array (IDT72V12081)
• 2,048 x 8-bit organization array (IDT72V13081)
• 4,096 x 8-bit organization array (IDT72V14081)
• 15 ns read/write cycle time
• 5V input tolerant
• Independent Read and Write clocks
• Empty and Full Flags signal FIFO status
• Output Enable puts output data bus in high-impedance state
• Available in 32-pin plastic Thin Quad FlatPack (TQFP)
• Industrial temperature range (–40°C to +85°C)
FUNCTIONAL BLOCK DIAGRAM
WCLK
RCLK
READ
CONTROL
WRITE
CONTROL
WEN
REN
OE
FIFO ARRAY
D0
- D
7
Q0 - Q7
Data In
x8
Data Out
x8
RESET LOGIC
FLAG OUTPUTS
EF
FF
RS
6161 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
NOVEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6161/2
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIALTEMPERATURERANGE
PIN CONFIGURATION
INDEX
29 28 27 26 25
32 31 30
1
2
3
4
5
6
7
8
D
6
WEN
24
23
22
21
20
19
18
17
D7
WCLK
DNC(1)
DNC(1)
VCC
VCC
GND
REN
Q0
Q1
Q2
Q3
RCLK
GND
9
10 11 12 13 14 15 16
6161 drw02
NOTE:
1. DNC = Do Not Connect.
TQFP (PR32-1, order code: PF)
TOP VIEW
PINDESCRIPTIONS
Symbol
Name
I/O
Description
D0-D7
DataInputs
EmptyFlag
I
Datainputs fora8-bitbus.
EF
O
When EF is LOW, the FIFOis emptyandfurtherdata reads fromthe outputare inhibited. WhenEF is
HIGH, the FIFO is not empty. EF is synchronized to RCLK.
FF
Full Flag
O
I
WhenFF is LOW, the FIFOis fullandfurtherdata writes intothe inputare inhibited. When FF is HIGH, the FIFO
isnotfull.FF issynchronizedtoWCLK.
When OE is LOW, the data outputbus is active. IfOE is HIGH, the outputdata bus willbe ina high-impedance
OE
OutputEnable
state.
Q0-Q7
RCLK
REN
DataOutputs
ReadClock
ReadEnable
O
I
Dataoutputsfora8-bitbus.
Data is readfromthe FIFOona LOW-to-HIGHtransitionofRCLKwhenREN is asserted.
WhenREN is LOW, data is readfromthe FIFOoneveryLOW-to-HIGHtransitionofRCLK.
Data will not be read from the FIFO if the EF is LOW.
I
RS
Reset
I
When RS is setLOW, internalreadandwrite pointers are settothe firstlocationofthe RAMarray, FF
goes HIGH, and EF goes LOW. A Reset is required before an initial Write after power-up.
WCLK
WriteClock
I
I
DataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLKwhentheWriteEnableisasserted.
WEN
WriteEnable
WhenWEN isLOW,dataiswrittenintotheFIFOoneveryLOW-to-HIGHtransitionWCLK.Data
willnotbewrittenintotheFIFOiftheFF is LOW.
VCC
Power
I
I
3.3V volt power supply.
Groundpin.
GND
Ground
2
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIALTEMPERATURERANGE
(1)
RECOMMENDEDOPERATING
CONDITIONS
ABSOLUTEMAXIMUMRATINGS
Symbol
VTERM
Rating
TerminalVoltagewith
RespecttoGND
Industrial
–0.5 to +5
Unit
V
(2)
Symbol
Parameter
Min. Typ.
Max. Unit
VCC
GND
VIH
SupplyVoltageIndustrial
SupplyVoltage
InputHighVoltageIndustrial 2.0
InputLowVoltageIndustrial -0.5
3.0
0
3.3
0
—
—
—
3.6
0
V
V
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55to +125
–50 to +50
°C
mA
5.5
0.8
85
V
V
NOTES:
VIL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TA
OperatingTemperature
Industrial
-40
°C
2. VCC terminal only.
DCELECTRICALCHARACTERISTICS
(Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
IDT72V10081
IDT72V11081
IDT72V12081
IDT72V13081
IDT72V14081
Industrial
tCLK = 15 ns
Symbol
Parameter
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
Min.
–1
Typ.
Max.
1
Unit
µA
µA
V
(1)
ILI
—
—
—
—
—
—
(2)
ILO
–10
2.4
—
10
—
0.4
20
5
VOH
VOL
Output Logic “1” Voltage, IOH= –2mA
Output Logic “0” Voltage, IOL = 8mA
Active Power Supply Current
StandbyCurrent
V
(3,4,5)
ICC1
—
mA
mA
(3,6)
ICC2
—
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs disabled (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 0.17 + 0.48*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions
Max.
Unit
(2)
CIN
InputCapacitance
VIN = 0V
10
pF
(1,2)
COUT
OutputCapacitance
VOUT = 0V
10
pF
NOTES:
1. With output deselected (OE ≥ VIH).
2. Characterized values, not currently tested.
3
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIALTEMPERATURERANGE
(1)
ACELECTRICALCHARACTERISTICS
(Industrial: VCC = 3.3 ±0.3V, TA = -40°C to + 85°C)
Industrial
IDT72V10081L15
IDT72V11081L15
IDT72V12081L15
IDT72V13081L15
IDT72V14081L15
Symbol
Parameter
Clock Cycle Frequency
Min.
Max.
Unit
fS
—
66.7
MHz
tA
DataAccessTime
Clock Cycle Time
Clock High Time
2
15
6
10
—
—
—
—
—
—
—
—
—
—
15
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Low Time
6
DataSetupTime
4
tDH
DataHoldTime
1
tENS
tENH
tRS
EnableSetupTime
EnableHoldTime
ResetPulseWidth(1)
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
4
1
15
10
10
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
(2)
OutputEnabletoOutputinLow-Z
OutputEnabletoOutputValid
3
(2)
tOHZ
tWFF
tREF
tSKEW1
OutputEnabletoOutputinHigh-Z
Write Clock to Full Flag
3
8
—
—
6
10
10
—
Read Clock to Empty Flag
Skew time between Read Clock & Write
Clock for Empty Flag &Full Flag
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
3.3V
330Ω
D.U.T.
30pF*
510Ω
ACTESTCONDITIONS
In Pulse Levels
GND to 3.0V
3ns
6161 drw03
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1.5V
1.5V
or equivalent circuit
SeeFigure1
Figure 1. Output Load
*Includes jig and scope capacitances.
4
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIALTEMPERATURERANGE
READ ENABLES (REN)
SIGNALDESCRIPTIONS
WhenbothReadEnable(REN)isLOW,dataisreadfromtheFIFOarray
totheoutputregisterontheLOW-to-HIGHtransitionoftheReadClock(RCLK).
WhenReadEnable(REN)isHIGH,theoutputregisterholdstheprevious
data and no new data is allowed to be loaded into the register.
WhenallthedatahasbeenreadfromtheFIFO,theEmptyFlag(EF)willgo
LOW,inhibitingfurtherreadoperations.Onceavalidwriteoperationhasbeen
accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read
can begin. The Read Enable (REN) is ignored when the FIFO is empty.
INPUTS
DATA IN (D0 - D7)
Datainputsfor8-bitwidedata.
CONTROLS
RESET (RS)
ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate.
During reset, both internal read and write pointers are set to the first location.
Aresetis requiredafterpower-upbeforeawriteoperationcantakeplace. The
Full Flag (FF) will be reset to HIGH after tRSF. The Empty Flag (EF) will be
resettoLOWaftertRSF. Duringreset,theoutputregisterisinitializedtoallzeros.
OUTPUTENABLE(OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receivedatafromtheoutputregister. WhenOutputEnable(OE)is disabled
(HIGH),theQoutputdatabusisinahigh-impedancestate.
WRITE CLOCK (WCLK)
OUTPUTS
AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock
(WCLK). DatasetupandholdtimesmustbemetinrespecttotheLOW-to-HIGH
transitionoftheWriteClock(WCLK). TheFullFlag(FF)issynchronizedwith
respecttotheLOW-to-HIGHtransitionoftheWriteClock(WCLK).
The Write andReadclocks canbe asynchronous orcoincident.
FULL FLAG (FF)
TheFullFlag(FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe
device is full. If no reads are performed after Reset (RS), the Full Flag (FF)
will go LOW after 256 writes for the IDT72V10081, 512 writes for the
IDT72V11081, 1,024 writes for the IDT72V12081, 2,048 writes for the
IDT72V13081 and 4,096 writes for the IDT72V14081.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transitionoftheWriteClock(WCLK).
WRITE ENABLE (WEN)
WhenWriteEnable(WEN)islow,datacanbeloadedintotheinputregister
andFIFOarrayontheLOW-to-HIGHtransitionofeveryWriteClock(WCLK).
DataisstoredintheFIFO arraysequentiallyandindependentlyofanyon-going
readoperation.
EMPTY FLAG (EF)
TheEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations,when
thereadpointerisequaltothewritepointer,indicatingthedeviceisempty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transitionoftheReadClock(RCLK).
Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther
writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)
will go HIGH after tWFF, allowing a valid write to begin. Write Enable (WEN)
is ignored when the FIFO is full.
DATA OUTPUTS (Q0 - Q7)
READ CLOCK (RCLK)
Dataoutputsfora8-bitwidedata.
DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead
Clock(RCLK).TheEmptyFlag(EF)is synchronizedwithrespecttotheLOW-
to-HIGHtransitionoftheReadClock(RCLK).
The Write andReadclocks canbe asynchronous orcoincident.
5
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIALTEMPERATURERANGE
tRS
RS
t
RSS
RSS
t
RSR
RSR
REN
t
t
WEN
EF
tRSF
tRSF
FF
tRSF
OE = 1(1)
Q0 - Q7
6161 drw06
OE = 0
NOTES:
1. After reset, the outputs will be LOW if OE = 0 and high-impedance if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 2. Reset Timing
tCLK
tCLKH
tCLKL
WCLK
tDH
tDS
D0 - D7
DATA IN VALID
tENH
tENS
NO OPERATION
WEN
tWFF
tWFF
FF
(1)
SKEW1
t
RCLK
REN
6161 drw07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 3. Write Cycle Timing
6
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
REN
NO OPERATION
tREF
tREF
EF
tA
VALID DATA
Q0 - Q7
tOLZ
tOHZ
tOE
OE
(1)
SKEW1
t
WCLK
WEN
6161 drw08
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 4. Read Cycle Timing
WCLK
tDS
D1
D2
D3
D0 - D7
D
Write)
0
(First Valid
tENS
WEN
(1)
FRL
t
tSKEW1
RCLK
tREF
EF
tENS
REN
tA
tA
D0
D1
Q0 - Q7
tOLZ
tOE
OE
6161 drw09
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 5. First Data Word Latency Timing
7
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIALTEMPERATURERANGE
NO WRITE
NO WRITE
NO WRITE
WCLK
tSKEW1
tSKEW1
tDS
D0 - D7
tWFF
tWFF
tWFF
FF
(1)
ENS
t
tENH
tENS
WEN
RCLK
tENH
tENH
tENS
tENS
REN
OE
tA
LOW
tA
Q0 - Q7
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
6161 drw10
Figure 6. Full Flag Timing
WCLK
tDS
tDS
DATA WRITE 1
DATA WRITE 2
D0 - D7
tENH
tENS
tENS
tENH
WEN
(1)
FRL
(1)
FFL
t
t
tSKEW1
tSKEW1
RCLK
tREF
tREF
tREF
EF
REN
OE
LOW
tA
DATA READ
DATA IN OUTPUT REGISTER
Q0 - Q7
6161 drw11
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 7. Empty Flag Timing
8
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
I
Industrial (-40°C to +85°C)
PF
Plastic Thin Quad Flatpack (TQFP, PR32-1)
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
15
L
Industrial
Low Power
72V10081 256 x 8
72V11081 512 x 8
3.3V Multimedia FIFO
3.3V Multimedia FIFO
72V12081 1,024 x 8 3.3V Multimedia FIFO
72V13081 2,048 x 8 3.3V Multimedia FIFO
72V14081 4,096 x 8 3.3V Multimedia FIFO
6161 drw18
DATASHEETDOCUMENTHISTORY
11/17/2003
pg. 1.
CORPORATE HEADQUARTERS
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Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
9
相关型号：
IDT72V13165L15TFI
3.3 VOLT MULTIMEDIA FIFO 256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16, and 4,096 x 16
IDT
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