IDT72V15320L10BBGI [IDT]
FIFO, 2KX32, 6.5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144;
| 型号： | IDT72V15320L10BBGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 2KX32, 6.5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144 先进先出芯片 |
| 文件： | 总26页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72V15160
IDT72V16160
IDT72V17160
IDT72V18160
IDT72V19160
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
3.3V MULTIMEDIA FIFO
16 BIT V-III, 32 BIT Vx-III FAMILY
UP TO 1 Mb DENSITY
• Master Reset clears entire FIFO
FEATURES:
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags through serial input
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function (PBGA Only)
• Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III)
Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid
Array (PBGA) (with additional features)
• Choose among the following memory organizations: Commercial
V-III
Vx-III
IDT72V15160 - 4,096 x 16
IDT72V16160 - 8,192 x 16
IDT72V17160 - 16,384 x 16
IDT72V18160 - 32,768 x 16
IDT72V19160 - 65,536 x 16
IDT72V14320 - 1,024 x 32
IDT72V15320 - 2,048 x 32
IDT72V16320 - 4,096 x 32
IDT72V17320 - 8,192 x 32
IDT72V18320 - 16,384 x 32
IDT72V19320 - 32,768 x 32
• Industrial temperature range (–40°C to +85°C)
• High-performance submicron CMOS technology
• Up to 100 MHz Operation of the Clocks
• 5V input tolerant
• Auto power down minimizes standby power consumption
FUNCTIONALBLOCKDIAGRAM
*Available on the Vx-III PBGA package only.
MRS
PRS
WCLK
RCLK
READ
CONTROL
WRITE
CONTROL
RESET LOGIC
FIFO ARRAY
WEN
REN
OE
D0 - Dn
Data In
x16, x32
Q0 - Qn
Data Out
x16, x32
TCK
*
FLAG LOGIC
*
TRST
*
JTAG CONTROL
(BOUNDARY
SCAN)
TMS
*
TDI
TDO
*
*
LD
SI
FSEL1 EF
HF
PAE
FF
PAF
SEN PFM FSEL0
6163 drw01
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.
NOVEMBER 2003
INDUSTRIALTEMPERATURERANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6163/3
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedwiththeserialinterfacetoanyuserdesiredvalueorbydefaultvalues.
Eightdefaultoffsetsettingsareprovided,sothatPAEcanbesettoswitchata
predefinednumberoflocationsfromtheemptyboundaryandthePAFthreshold
canalsobesetatsimilarpredefinedvaluesfromthefullboundary. Thedefault
offsetvaluesaresetduringMasterResetbythestateoftheFSEL0,FSEL1,and
LD pins.
For serial programming, SEN together with LD on each rising edge of
WCLK,areusedtoloadtheoffsetregisters viatheSerialInput(SI).
DuringMasterReset(MRS)thereadandwritepointersaresettothefirst
locationoftheFIFO.
DESCRIPTION:
The IDT V-III and Vx-III Multimedia FIFOs are exceptionally deep, high
speed,CMOSFirst-In-First-Out(FIFO)memorieswithindependent clocked
readandwrite controls andhighdensityofferings upto1Mbit.
Each FIFO has a data input port (Dn) and a data output port (Qn). The
frequencies ofboththe RCLK (read port clock) and the WCLK (write port
clock) signals may vary from 0 to fS(MAX) with complete independence.
There are norestrictions onthe frequencyoftheoneclockinputwithrespect
totheother.
TheseFIFOshavefiveflagpins,EF(EmptyFlag),FF(FullFlag),HF(Half-
fullFlag),PAE(ProgrammableAlmost-Emptyflag)andPAF(Programmable
Almost-Fullflag).
PIN CONFIGURATIONS (16-BIT V-III FAMILY)
INDEX
V
CC
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
WEN
SEN
OE
DNC(1)
VCC
VCC
Q0
DNC(1)
GND
GND
D0
Q1
GND
GND
DNC(1)
VCC
9
Q2
D1
GND
D2
D3
GND
D4
D5
D6
D7
D8
10
11
12
13
14
15
16
17
18
19
20
VCC
Q3
Q4
GND
Q5
GND
Q6
V
Q7
Q8
Q9
CC
VCC
6163 drw02
NOTE:
1. DNC = Do Not Connect.
TQFP (PN80-1, order code: PF)
TOP VIEW
2
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
The Partial Reset (PRS) also sets the read and write pointers to the first
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
locationofthememory.However,theprogrammableflagsettingsexistingbefore updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
PartialResetremainunchanged.PRS isusefulforresettingadeviceinmid- assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
operation,whenreprogrammingprogrammableflagswouldbeundesirable. desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost- Mode (PFM) pin.
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
PAFflags. currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW- The IDT V-III and Vx-III family of FIFOs are fabricated using IDT’s high
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW- speedsubmicronCMOStechnology.
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
PIN CONFIGURATIONS (32-BIT Vx-III FAMILY)
INDEX
WEN
OE
1
2
3
4
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
SEN
DNC(1)
VCC
Q0
Q1
Q2
Q3
GND
VCC
DNC(1)
GND
D0
5
6
7
8
9
D1
D2
D3
GND
Q4
Q5
Q6
Q7
Q8
DNC(1)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VCC
D4
D5
GND
D6
VCC
D7
Q9
D8
GND
D9
D10
GND
GND
D11
Q10
GND
GND
DNC(1)
Q11
Q12
Q13
Q14
Q15
GND
Q16
Q17
VCC
D12
D13
D14
D15
GND
D16
D17
GND
D18
D19
VCC
VCC
DNC(1)
Q18
Q19
Q20
VCC
GND
Q21
Q22
D20
GND
D21
6163 drw03
NOTE:
1. DNC - Do Not Connect.
TQFP: (PK128-1, order code: PF)
TOP VIEW
3
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
PIN CONFIGURATIONS-CONTINUED (32-BIT VX-III FAMILY)
A1 BALL PAD CORNER
A
WEN
PAF
LD
FF
HF
EF
REN
OE
V
CC
WCLK
GND
FS1
RCLK
GND
PAE
Q0
B
C
SEN
PRS
MRS
GND
FS0
VCC
PFM
VCC
Q1
D0
D3
D6
D1
D4
D7
D2
D5
D8
SI
GND
VCC
VCC
GND
GND
Q6
Q3
Q2
Q4
Q7
D
E
VCC
VCC
GND
GND
GND
GND
VCC
VCC
Q5
Q8
VCC
GND
GND
VCC
Q9
F
Q12
Q13
Q16
Q19
Q22
D9
D10
D13
D16
D19
D22
D11
D12
D15
D18
D21
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Q11
Q14
Q17
Q20
Q23
Q10
Q15
Q18
Q21
DNC
V
CC
VCC
G
D14
D17
D20
D23
VCC
VCC
H
J
VCC
VCC
V
CC
VCC
VCC
VCC
K
L
D28
D31
D30
VCC
VCC
TDO
Q29
TCK
GND
GND
1
GND
GND
2
D25
D24
3
D27
D26
4
TMS
TRST
6
Q31
Q30
8
Q28
Q27
9
Q26
Q25
10
DNC
Q24
11
DNC
DNC
M
D29
TDI
5
7
12
6163 drw03b
NOTE:
1. DNC - Do Not Connect.
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
4
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
PINDESCRIPTION
Symbol
D0–Dn
EF
Name
DataInputs
EmptyFlag
Full Flag
I/O
I
Description
Data inputs for a 16 or 32-bit bus
O
O
I
EF indicates the FIFOmemoryis empty. See Table 2.
FF indicates the FIFOmemoryis full. See Table 2.
DuringMasterReset,thisinputalongwithFSEL1andtheLD pin,willselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
HFindicatestheFIFOmemoryismorethanhalf-full.HFisassertedwhenthenumberofwordswrittenintotheFIFO
reaches N÷2+1, where N is the total depth of the FIFO. See Table 2.
DuringMasterReset,thestateoftheLD inputalongwithFSEL0andFSEL1,determinesoneofeightdefaultoffset
values forthePAEandPAF flags andserialprogrammingmode.AfterMasterReset, LDmustbehighandshould
onlytoggleLOWtogetherwithSENtostartserialloadingoftheflagoffsets.
FF
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
I
O
I
HF
LD
Half-FullFlag
Load
MRS
MasterReset
OutputEnable
I
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoall zeroes.DuringMasterReset,
theFIFOisconfiguredforoneofeightprogrammableflagdefaultsettings,serialprogrammingoftheoffsetsettingsand
synchronousversusasynchronousprogrammableflagtimingmodes.
OE
I
OEcontrolstheoutputlinedrivers.
PAE
Programmable
Almost-EmptyFlag
O
PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmptyOffset
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF
Programmable
Almost-FullFlag
O
I
PAF goes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedinthe
FullOffsetregister. PAF goes LOWifthe numberoffree locations inthe FIFOmemoryis less thanorequaltom.
DuringMasterReset,aLOWonPFMwillselectAsynchronous Programmableflagtimingmode.AHIGHonPFM
willselectSynchronousProgrammableflagtimingmode.
(1)
PFM
Programmable
Flag Mode
PRS
PartialReset
I
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
theserialprogrammingmethodorprogrammableflagsettingsareallretained.
Q0–Qn
RCLK
REN
DataOutputs
ReadClock
ReadEnable
SerialEnable
O
I
Dataoutputs foran16or32-bitbus.Outputs arenot5Vtolerantregardless ofthestateofOE.
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory.
REN enables RCLK for reading data from the FIFO memory.
SENenablesserialloadingofprogrammableflagoffsets. SENmustbehighduringMasterResetandshouldonly
toggleLOWtogetherwithLDtostartserialloadingoftheflagoffsets.
I
SEN
I
SI
SerialIn
I
I
I
I
I
AtMaserResetthispinisLOW.AfterMasterReset,thispinfunctionsasaserialinputforloadingoffsetregisters.
Enabled by WEN, the risingedge ofWCLKwrites data intothe FIFO.
WENenables WCLKforwritingdataintotheFIFOmemory.
WCLK
WEN
VCC
WriteClock
WriteEnable
+3.3VSupply
Ground
These are VCC supply inputs and must be connected to the 3.3V supply rail.
GND
GroundPins.
NOTE:
1. Inputs should not change state after Master Reset.
**Please continue to next page for more Pin descriptions for PBGA package.
5
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
PIN DESCRIPTION (32-BIT VX-III PBGA PACKAGE ONLY)
Symbol
Name
I/O
Description
(1)
TCK
JTAGClock
I
ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperationsofthe
devicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedgeofTCKandoutputschange
onthefallingedgeofTCK.IftheJTAGfunctionis notusedthis signalneeds tobetiedtoGND.
(1)
TDI
JTAGTestData
Input
I
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister.
Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(1)
TDO
JTAGTestData
Output
O
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass
Register.This outputis highimpedanceexceptwhenshifting,whileinSHIFT-DRandSHIFT-IRcontrollerstates.
TMS(1)
JTAGModeSelect
JTAGReset
I
I
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough
itsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(1)
TRST
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomaticallyreset
upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP
controllerisnotproperlyresetthentheFIFOoutputswillalwaysbeinhigh-impedance.IftheJTAGfunctionisused
butthe userdoes notwanttouse TRST, thenTRST canbe tiedwithMRS toensure properFIFOoperation. Ifthe
JTAGfunctionisnotusedthenthissignalneedstobetiedtoGND.Aninternalpull-upresistorforcesTRSTHIGHif
leftunconnected.
NOTE:
1. These pins are for the JTAG port. Please refer to pages 15-19 and Figures 2-4.
6
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol
Rating
Industrial
Unit
(2)
Symbol
Parameter
SupplyVoltageIndustrial
Min. Typ.
Max. Unit
VTERM
TerminalVoltage
with respect to GND
–0.5to+4.5
V
(1)
VCC
3.15
0
3.3
0
3.45
0
V
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50to+50
°C
GND SupplyVoltageIndustrial
(2)
VIH
InputHighVoltageIndustrial
InputLowVoltageIndustrial
OperatingTemperatureIndustrial
2.0
—
-40
—
—
—
5.5
0.8
85
V
DCOutputCurrent
mA
(3)
VIL
TA
V
NOTES:
°C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTES:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
3. 1.5V undershoots are allowed for 10ns once per cycle.
2. VCC terminal only.
DCELECTRICALCHARACTERISTICS
(Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72V15160, IDT72V14320
IDT72V16160, IDT72V15320
IDT72V17160, IDT72V16320
IDT72V18160, IDT72V17320
IDT72V19160, IDT72V18320
IDT72V19320
Industrial
tCLK = 10ns
Symbol
Parameter
Min.
Max.
Unit
(1)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
–10
2.4
—
—
—
1
µ A
µA
V
(2)
ILO
10
—
0.4
40
15
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
VOL
V
ICC1(3,4,5)
ICC2(3,6)
mA
mA
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 4.2 + 1.4*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
7
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
ACELECTRICALCHARACTERISTICS
(Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Industrial
IDT72V15160L10
IDT72V16160L10
IDT72V17160L10
IDT72V18160L10
IDT72V19160L10
IDT72V14320L10
IDT72V15320L10
IDT72V16320L10
IDT72V17320L10
IDT72V18320L10
IDT72V19320L10
Symbol Parameter
Min.
—
2
Max
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
Unit
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fS
Clock Cycle Frequency
tA
DataAccessTime
Clock Cycle Time
Clock High Time
tCLK
tCLKH
tCLKL
tDS
10
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
15
10
—
0
Clock Low Time
DataSetupTime
tDH
DataHoldTime
tENS
tENH
tLDS
EnableSetupTime
EnableHoldTime
LoadSetupTime
tLDH
tRS
LoadHoldTime
ResetPulseWidth(1)
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
tRSS
tRSR
tRSF
tOLZ
tOE
(2)
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid
—
6
2
(2)
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
OutputEnabletoOutputinHigh-Z
2
6
Write Clock to FF
Read Clock to EF
—
—
—
—
—
—
—
7
6.5
6.5
16
ClocktoAsynchronousProgrammableAlmost-FullFlag
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
Clock to HF
6.5
16
6.5
16
tSKEW1
tSKEW2
Skew time between RCLK and WCLK for EF and FF
Skew time between RCLK and WCLK for PAE and PAF
—
—
10
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
8
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
AC TEST LOADS
ACTESTCONDITIONS
InputPulseLevels
GND to 3.0V
3ns(1)
3.3V
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoadfortCLK=10ns
1.5V
330Ω
1.5V
SeeFigure1
D.U.T.
510Ω
30pF*
6163 drw04
Figure 1. Output Load
* Includes jig and scope capacitances.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
Output
Normally
LOW
VCC
2
V
2
CC
100mV
100mV
100mV
VOL
VOH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
6163 drw04a
NOTE:
1. REN is HIGH.
9
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
FUNCTIONALDESCRIPTION
TABLE 1 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
To write data into to the FIFO, Write Enable (WEN) must be LOW. Data
presentedtothe DATAINlines willbe clockedintothe FIFOonsubsequent
transitionsoftheWriteClock(WCLK).Afterthefirstwriteisperformed,theEmpty
Flag(EF)willgoHIGH.SubsequentwriteswillcontinuetofilluptheFIFO.The
ProgrammableAlmost-Emptyflag(PAE)willgoHIGHaftern + 1wordshave
beenloadedintotheFIFO,where“n”istheemptyoffsetvalue.Thedefaultsetting
forthesevaluesarestatedinthefootnoteofTable1.Thisparameterisalsouser
programmable.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
D/2+1(D=totalnumberof words)waswrittenintotheFIFO. Continuingtowrite
dataintotheFIFOwillcausetheProgrammableAlmost-Fullflag(PAF)togo
LOW.Again,ifnoreadsareperformed, thePAFwillgoLOWafter(D-m).The
offset“m”isthefulloffsetvalue.Thedefaultsettingforthesevaluesarestated
inthefootnoteofTable1.Thisparameterisalsouserprogrammable.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
totheFIFO.
IDT72V14320, 72V15360
LD
L
L
L
L
H
H
H
H
FSEL1
FSEL0
Offsets n,m
H
L
L
H
L
H
L
H
L
H
L
H
L
L
H
H
511
255
127
63
31
15
7
3
IDT72V16320, 72V17320, 72V18320, 72V19320
IDT72V15160, 72V16160, 72V17160, 72V18160
LD
H
L
L
L
FSEL1
FSEL0
Offsets n,m
L
H
L
L
L
H
L
H
L
H
H
1,023
511
255
127
63
31
15
7
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGH.If furtherread
operationsoccur,withoutwriteoperations,PAEwillgoLOWwhenthereare
n words in the FIFO, where n is the empty offset value. Continuing read
operationswillcausetheFIFOtobecomeempty.Whenthelastwordhasbeen
readfromtheFIFO,theEFwillgoLOWinhibitingfurtherreadoperations.REN
is ignored when the FIFO is empty.
L
L
H
H
L
H
H
H
H
The EFand FF outputs are double register-bufferedoutputs.
IDT72V19160
LD
H
L
L
L
FSEL1
FSEL0
Offsets n,m
1,023
8,191
16,383
127
PROGRAMMING FLAG OFFSETS
Full andEmptyFlagoffsetvalues are userprogrammable. The IDTV-III
andVx-IIIFIFOs haveinternalregisters fortheseoffsets.
Therearetwowaystoprogramtheflagoffsetvalues.Selectingoneofthe
eightpre-setvaluesduringmasterresetorserialprogramming.
L
H
L
L
L
H
L
L
L
H
H
L
H
L
H
H
4,095
511
2,047
255
DEFAULT FLAG OFFSETS
ThereareeightdefaultoffsetvaluesselectableduringMasterReset. These
offset values are shown in Table 1.
Programming offsets with default values (LD, SEN pins): With the
LDpintogetherwiththeFSEL0andFSEL1theuserhastheoptiontochoose
oneofeightpresetvaluesforbothoffsetregisters.DuringmasterresettheLD
pincanbeeitherHIGHorLOWdependingontheselectedvalue.AfterMaster
Reset,LDmust be high andshouldnotchangestate.SENshouldbehighduring
andafterMasterResetandshouldnotchangestate.
H
H
H
H
All Devices
LD
FSEL1
FSEL0
Program Mode
(3)
H
X
X
Serial
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
SERIAL PROGRAMMING MODE
Offset values can also be programmed into the FIFO by serial loading
method.Theoffsetregistersmaybeprogrammed(andreprogrammed)any
timeafterMasterReset.Validprogrammingrangesarefrom0toD-1.
Serialprogrammingofoffsetvalues (LD,SENpins):Inordertoselect
serialprogrammingthe LD pinhas tobe HIGHduringmaster. Both,LD and
SEN pinhave totoggle toLOWinordertoinitialthe serialprogramming. LD
should be high during normal FIFO operation.
Atotalof
20 bits for the IDT72V14320
22 bits for the IDT72V15320
24 bits for the IDT72V15160, IDT72V16320
26 bits for the IDT72V16160, IDT72V17320
28 bits for the IDT72V17160, IDT72V18320
30 bits for the IDT72V18160, IDT72V19320
32 bits for the IDT72V19160
IfSerialProgrammingmodehasbeenselectedthenprogrammingofPAE
andPAFvaluescanbeachievedbyusingacombinationoftheLD,SEN,WCLK
andSIinputpins.ProgrammingPAEandPAFproceedsasfollows: whenLD
andSENaresetLOW,dataontheSIinputarewritten,onebitforeachWCLK
risingedge,startingwiththeEmptyOffsetLSBandendingwiththeFullOffset
MSB.
has to be loaded serial for the two (PAF, PAE) registers.
10
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
TABLE 2 STATUS FLAGS FOR IDT STANDARD MODE
IDT72V15160
IDT72V14320
IDT72V15320
IDT72V16320
FF PAF HF PAE EF
L
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
0
0
1 to n(1)
1 to n(1)
1 to n(1)
Number of
Words in
FIFO
H
H
H
H
H
(n+1) to 512
H
H
H
H
(n+1) to 1,024
(n+1) to 2,048
513 to (1,024-(m+1))
(1,024-m) to 1,023
1,024
1,025 to (2,048-(m+1))
(2,048-m) to 2,047
2,048
2,049 to (4,096-(m+1))
(4,096m) to 4,095
4,096
L
L
L
IDT72V18160
IDT72V19320
IDT72V16160
IDT72V19160
IDT72V17160
IDT72V18320
IDT72V17320
FF PAF HF PAE EF
L
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
0
0
0
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
Number of
Words in
FIFO
H
H
H
H
H
(n+1) to 4,096
H
H
H
H
(n+1) to 8,192
(n+1) to 16,384
(n+1) to 32,768
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
16,384
16,385 to (32,768-(m+1)) 32,769 to (65,536-(m+1))
L
(32,768-m) to 32,767
32,768
(65,536-m) to 65,535
65,536
L
L
6163 drw05
NOTE:
1. See Table 1 for values for n, m.
11
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
TABLE 3 — FLAG OFFSET PROGRAMMING, STATE OF LD AND
SEN AFTER MASTER RESET
Operation
LD
WEN
REN
SEN
WCLK RCLK
Serial Flag Programming
0
1
1
0
X
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
Write Memory
Read Memory
1
1
0
X
0
X
X
X
X
X
X
X
X
1
1
1
No Operation
X
X
1
0
1
0
1
1
X
1
No Operation
Invalid Operation
X
0
1
0
1
Invalid Operation
6163 drw06
Using the serial method, individual registers cannot be programmed
selectively. PAEandPAFcanshowavalidstatusonlyafterthecompleteset
of bits (for all offset registers) has been entered. The registers can be
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot
havetooccuratonce. AselectnumberofbitscanbewrittentotheSIinputand
then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia
DnbytogglingWEN. WhenWENisbroughtHIGHwithLDandSENrestored
toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI. Ifan
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW
anddeactivateSENortosetSENLOWanddeactivateLD. OnceLDandSEN
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen
written. MeasuringfromtherisingWCLKedgethatachievestheabovecriteria;
PAFwillbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalid
afterthe nexttworisingRCLKedges plus tPAE plus tSKEW2.
Refer also to LD Signal description for more information on flag offset
programmingandstaterequirementsforLD andSENpins
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
TheIDTV-IIIandVx-III canbeconfiguredduringtheMasterResetcycle
witheither synchronousorasynchronoustimingforPAFandPAEflagsbyuse
ofthe PFMpin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
notRCLK. Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.
12
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
TheOEinputisusedtoprovideAsynchronouscontrolofthethree-stateQn
outputs.
SIGNALDESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
READ ENABLE ( REN )
Data inputs for16or32-bitwide data.
When Read Enable is LOW, data is loaded from the FIFO array into the
outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
andnonewdata is loadedintothe outputregister. The data outputs Q0-Qn
maintainthepreviousdatavalue.
EverywordaccessedatQn,includingthefirstwordwrittentoanemptyFIFO,
mustberequestedusingREN. WhenthelastwordhasbeenreadfromtheFIFO,
the Empty Flag (EF) will go LOW, inhibiting further read operations. RENis
ignoredwhentheFIFOisempty.Onceawriteisperformed,EFwillgoHIGH
allowingareadtooccur. TheEFflagisupdatedbytwoRCLKcycles+tSKEW
afterthevalidWCLKcycle.
CONTROLS:
MASTER RESET ( MRS )
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
ofthe RAMarray. PAEwill goLOW, PAF willgoHIGH,HF willgoHIGH,EF
will go LOW and FF will go HIGH.
SIis supposedtobeLOWduringmasterreset.
PFMcontrolsettingsaredefinedduringtheMasterResetcycle.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
SERIAL ENABLE ( SEN )
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofWCLK.
When SEN is HIGH, the programmable registers retains the previous
settingsandnooffsetsareloaded. SENfunctionsthesamewayinbothIDT.
RefertoLOAD(LD)pinandsection“ProgrammingFlagOffsets”formore
informationonoffsetprogramming.
PARTIAL RESET ( PRS )
APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW, PAFgoesHIGH,
HF goes HIGH, FF willgoHIGHandEF willgoLOW. The outputregisteris
initializedtoallzeroes. PRSisasynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
OUTPUT ENABLE (OE)
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
intoahighimpedancestate.
SERIAL IN (SI)
AtthetimeofMasterReset,SImustbeLOW.
AfterMasterReset,SIactsasaserialinputforloadingPAEandPAFoffsets
intotheprogrammableregisters.
LOAD ( LD )
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
thePAEandPAFflags,alongwiththeserialprogrammingoptionfortheseoffset
registers (see Table 3).
AfterMasterReset, the LD pinis usedinconjunctionwiththe SEN pinto
activatetheprogrammingprocessoftheflagoffsetvaluesPAEandPAF.Pulling
LDLOWwillbeginaserialloadingoftheseoffsetvalues.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF,
PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating HF flag to LOW). The Write and Read Clocks can either be
independentorcoincident.
DependingonthedefaultorserialprogrammingoptionthestateofLDand
SENhavetobeconsideredbeforeandaftermasterreset.Referalsotosection
“ProgrammingFlagOffsets”formoreinformationonoffsetprogramming.
Programmingoffsets withdefaultvalues:WiththeLDpintogetherwith
the FSEL0andFSEL1the userhas the optiontochoose one ofeightpreset
values forbothoffsetregisters.DuringmasterresettheLD pincanbeeither
HIGHorLOWdependingontheselectedvalue.AfterMasterReset,LDmust
be high and should not change state. SEN should be high during and after
MasterResetandshouldnotchangestate.
Serialprogrammingofoffsetvalues:Inordertoselectserialprogram-
ming the LD pin has to be HIGH during master. Both, LD and SEN pin have
totoggletoLOWinordertoinitialtheserialprogramming.LDshouldbehigh
duringnormalFIFOoperation.
WRITE ENABLE ( WEN )
WhentheWENinput isLOW,datamaybeloadedintotheFIFOarrayon
the risingedge ofeveryWCLKcycle ifthe device is notfull. Data is storedin
theFIFOarraysequentiallyandindependentlyofanyongoingreadoperation.
WhenWENisHIGH,nonewdataiswrittenintheFIFO arrayoneachWCLK
cycle.
Topreventdataoverflow,FFwillgoLOW,inhibitingfurtherwriteoperations.
Uponthecompletionofavalidreadcycle,FF willgoHIGHallowingawriteto
occur. TheFFisupdatedbytwoWCLKcycles+tSKEW aftertheRCLKcycle.
WEN is ignored when the FIFO is full.
READ CLOCK (RCLK)
A readcycleisinitiatedontherisingedgeoftheRCLKinput. Datacanbe
readontheoutputs,ontherisingedgeoftheRCLKinput. Itispermissibleto
stoptheRCLK. NotethatwhileRCLKisidle,theEF,PAEandHFflagswillnot
beupdated.(NotethatRCLKisonlycapableofupdatingtheHF flagtoHIGH).
The Write andReadClocks canbe independentorcoincident.
PROGRAMMABLEFLAGMODE(PFM)
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram-
mableflagtimingmode.AHIGHonPFMwillselectSynchronousProgrammable
flagtimingmode.IfasynchronousPAF/PAEconfigurationisselected(PFM,
13
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
ofwords,m=fulloffsetvalue).Thedefaultsettingforthisvalueisstatedinthe
footnoteofTable1.
IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). IfsynchronousPAF
configurationisselected,thePAFisupdatedontherisingedgeofWCLK.
LOWduringMRS),thePAEisassertedLOWontheLOW-to-HIGHtransition
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFis resettoHIGHontheLOW-to-HIGHtransitionofRCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand
notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK
onlyandnotRCLK.Themodedesiredisconfiguredduringmasterresetbythe
stateoftheProgrammableFlagMode(PFM)pin.
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
reachesthealmost-emptycondition.PAEwillgoLOWwhentherearenwords
orlessintheFIFO.Theoffset“n”istheemptyoffsetvalue.Thedefaultsetting
forthisvalueisstatedinthefootnoteofTable 1.
OUTPUTS:
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). IfsynchronousPAE
configurationisselected,thePAEisupdatedontherisingedgeofRCLK.
FULL FLAG ( FF )
WhentheFIFOisfull,FF willgoLOW,inhibitingfurtherwriteoperations.
WhenFF isHIGH,theFIFOisnotfull. Ifnoreadsareperformedafterareset
(eitherMRSorPRS),FFwillgoLOWafterDwritestotheFIFO(D = totalnumber
ofwords).
FFissynchronousandupdatedontherisingedgeofWCLK.FFisadouble
register-bufferedoutput.
HALF-FULL FLAG ( HF )
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
HIGH.
Ifnoreadsareperformedafterreset(MRSorPRS),HFwillgoLOWafter
(D/2 + 1)writestotheFIFO,whereD=totalnumberofwordsavailableinthe
FIFO.
EMPTY FLAG ( EF )
WhentheFIFOisempty,EFwillgoLOW,inhibitingfurtherreadoperations.
When EF is HIGH, the FIFOis notempty.
EFissynchronousandupdatedontherisingedgeofRCLK.EFisadouble
register-bufferedoutput.
Because HF is updated by both RCLK and WCLK, it is considered
asynchronous.
PROGRAMMABLE ALMOST-FULL FLAG (PAF )
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reachesthealmost-fullcondition.Ifnoreadsareperformedafterreset(MRS),
PAFwillgoLOWafter(D - m)wordsarewrittentotheFIFO.(D=totalnumber
DATAOUTPUTS(Q0-Qn)
(Q0-Qn)are data outputs for16-bitor32-bitwide data.
14
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
6163 drw07
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 2. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(VCC = 3.3V ± 5%; Tcase = 0°C to +85°C)
SYSTEMINTERFACEPARAMETERS
Parameter
Symbol
Test
Conditions
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
Min. Max. Units
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
15
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V14320/72V15320/
72V16320/72V17320/72V18320/72V19320incorporatesthenecessarytap
controllerandmodifiedpadcellstoimplementtheJTAG facility.
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The Figure belowshows the standardBoundary-ScanArchitecture
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
6163 drw08
Figure 3. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
16
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-IR
Shift-DR
1
1
1
1
Exit1-IR
EXit1-DR
Input = TMS
0
0
0
0
Pause-IR
Pause-DR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-IR
Update-DR
1
0
1
0
6163 drw09
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 4. TAP Controller State Diagram
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe lasttwosignificantbits arealways requiredtobe“01”.
TCLKpulse. The TMSsignallevel(0or1)determines the state progression
Shift-IR In this controller state, the instruction register gets connected
thatoccursoneachTCLKrisingedge.TheTAPcontrollertakesprecedence betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
over the FIFO memory and must be reset after power up of the device. See ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
TRSTdescriptionformoredetailsonTAPcontrollerreset.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe
register.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch IRstateorUpdate-IRstateismade.
awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction
statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This registertobetemporarilyhalted.
is the reason why the Test Reset (TRST) pin is optional.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif IRstateorUpdate-IRstateismade.
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
intheICis idles otherwise.
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
otherwise. Update-IRstatesintheInstructionpath.
17
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
THE INSTRUCTION REGISTER
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0 0X33
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
1
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
IDT72V14320/15320/16320/17320/18320/19320 JTAG Device Identification Register
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
TESTDATAREGISTER
•
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions. Instructionsaredecodedasfollows.
Hex
Instruction
Function
Value
0x00
0x02
0x01
0x03
0x0F
EXTEST
IDCODE
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
SAMPLE/PRELOAD SelectBoundaryScanRegister
HIGH-IMPEDANCE JTAG
BYPASS
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
SelectBypassRegister
JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
EXTEST
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO. Duringthis instruction, theboundary-scanregisteris accessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
THE DEVICE IDENTIFICATION REGISTER
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
IIDCODE
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe
TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
For the IDT72V14320/72V15320/72V16320/72V17320/72V18320/
72V19320,thePartNumberfieldcontainsthefollowingvalues:
Device
Part# Field
04E5
04E4
04E3
04E2
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
SAMPLE/PRELOAD
TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto
theboundary-scanregisterbeforeloadinganEXTESTinstruction.
04E1
04E0
18
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
19
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
tRS
MRS
tRSR
tRSS
tRSS
tRSS
REN
WEN
SI
tRSR
tRSR
tRSS
tRSS
tRSR
LD
FSEL0,
FSEL1
tRSS
tRSS
PFM
SEN
tRSF
tRSF
tRSF
tRSF
tRSF
EF
FF
PAE
PAF, HF
Q0 - Qn
OE = HIGH
OE = LOW
6163 drw10
Figure 5. Master Reset Timing
20
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
tRSS
SEN
EF
tRSF
tRSF
FF
tRSF
PAE
tRSF
PAF,
HF
tRSF
OE = HIGH
Q0 - Qn
6163 drw11
OE = LOW
Figure 6. Partial Reset Timing
21
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
tCLK
tCLKH
NO WRITE
NO WRITE
tCLKL
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
tDS
tDH
tDS
tDH
DX
DX+1
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENH
tENS
tENH
REN
tA
tA
Q0
- Q
n
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
6163 drw12
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between
the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
tENH
tENS
tENS
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
t
A
tA
tA
D0
LAST WORD
D1
LAST WORD
Q0 - Qn
tOLZ
tOLZ
tOHZ
tOE
OE
WCLK
WEN
(1)
SKEW1
t
tENH
tENH
tENS
tENS
tDS
tDH
tDH
tDS
D0
D1
D0 -
Dn
6163 drw13
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing
22
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
WCLK
tENH
tENS
tENH
SEN
LD
tLDH
tLDH
tLDS
tDH
tDS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
6163 drw20
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 9 for the IDT72V14320 (total of 20 bits), X = 10 for the IDT72V15320 (total of 22 bits), X = 11 for the IDT72V15160 and IDT72V16320 (total of 24 bits), X = 12 for the IDT72V16160,
and IDT72V17320 (total of 26 bits), X = 13 for the IDT72V17160 and IDT72V18320 (total of 28 bits), X = 14 for the IDT72V18160 and IDT72V19320 (total of 30 bits), X = 15 for the
IDT72V19160 (total of 32 bits).
Figure 9. Serial Loading of Programmable Flag Registers
tCLKL
tCLKL
1
2
WCLK
WEN
PAF
2
1
tENS
tENH
tPAFS
tPAFS
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
2)
in FIFO(
(3)
tSKEW2
RCLK
tENS
tENH
6163 drw23
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
V-III: D = 4,096 for the IDT72V15160 and 8,192 for the IDT72V16160, 16,384 for the IDT72V17160 and 32,768 for the IDT72V18160, 65,526 for the IDT72V19160.
Vx-III: D = 1,024 for the IDT72V14320, 2,048 for the IDT72V15320, 4,096 for the IDT72V16320 and 8,192 for the IDT72V17320, 16,384 for the IDT72V18320 and 32,768 for the
IDT72V19320.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 10. Synchronous Programmable Almost-Full Flag Timing
23
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO
n words in FIFO
,
n+1 words in FIFO
(2)
tPAES
tPAES
t
SKEW2
1
2
1
2
RCLK
tENS
tENH
6163 drw24
REN
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. PAE is asserted and updated on the rising edge of WCLK only.
4. Select this mode by setting PFM HIGH during Master Reset.
Figure 11. Synchronous Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1)
words in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
6163 drw25
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
V-III: D = 4,096 for the IDT72V15160 and 8,192 for the IDT72V16160, 16,384 for the IDT72V17160 and 32,768 for the IDT72V18160, 65,526 for the IDT72V19160.
Vx-III: D = 1,024 for the IDT72V14320, 2,048 for the IDT72V15320, 4,096 for the IDT72V16320 and 8,192 for the IDT72V17320, 16,384 for the IDT72V18320 and 32,768 for the
IDT72V19320.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 12. Asynchronous Programmable Almost-Full Flag Timing
24
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
INDUSTRIAL
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
TEMPERATURE RANGE
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
n + 1 words in FIFO
n words in FIFO
PAE
RCLK
REN
n words in FIFO
tPAEA
tENS
6163 drw26
NOTES:
1. n = PAE offset.
2. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
3. Select this mode by setting PFM LOW during Master Reset.
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 words in FIFO
D/2 words in FIFO
D/2 + 1 words in FIFO
HF
t
RCLK
tENS
REN
6163 drw27
NOTES:
1. D = maximum FIFO depth.
V-III: D = 4,096 for the IDT72V15160 and 8,192 for the IDT72V16160, 16,384 for the IDT72V17160 and 32,768 for the IDT72V18160, 65,526 for the IDT72V19160.
Vx-III: D = 1,024 for the IDT72V14320, 2,048 for the IDT72V15320, 4,096 for the IDT72V16320 and 8,192 for the IDT72V17320, 16,384 for the IDT72V18320 and 32,768 for the
IDT72V19320.
Figure 14. Half-Full Flag Timing
25
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
Industrial (-40°C to +85°C)
I
PF
BB
Thin Plastic Quad Flatpack (TQFP, PN80-1, PK128-1)
Plastic Ball Grid Array (PBGA, BB144-1, Vx-III only)
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Industrial
10
L
Low Power
4,096 x 16 3.3V Multimedia FIFO, V-III
8,192 x 16 3.3V Multimedia FIFO, V-III
16,384 x 16 3.3V Multimedia FIFO, V-III
32,768 x 16 3.3V Multimedia FIFO, V-III
65,526 x 16 3.3V Multimedia FIFO, V-III
72V15160
72V16160
72V17160
72V18160
72V19160
1,024 x 32 3.3V Multimedia FIFO, Vx-III
2,048 x 32 3.3V Multimedia FIFO, Vx-III
4,096 x 32 3.3V Multimedia FIFO, Vx-III
8,192 x 32 3.3V Multimedia FIFO, Vx-III
16,384 x 32 3.3V Multimedia FIFO, Vx-III
32,768 x 32 3.3V Multimedia FIFO, Vx-III
72V14320
72V15320
72V16320
72V17320
72V18320
72V19320
6163 drw05
DATASHEETDOCUMENTHISTORY
11/17/2003
pg. 1.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
26
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