IDT72V2103L10PF9 [IDT]
FIFO, 128KX18, 6.5ns, Synchronous, CMOS, PQFP80, PLASTIC, TQFP-80;
| 型号： | IDT72V2103L10PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 128KX18, 6.5ns, Synchronous, CMOS, PQFP80, PLASTIC, TQFP-80 LTE 先进先出芯片 |
| 文件： | 总46页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT HIGH-DENSITY SUPERSYNC II™
NARROW BUS FIFO
131,072 x 18/262,144 x 9
262,144 x 18/524,288 x 9
IDT72V2103
IDT72V2113
FEATURES:
• Partial Reset clears data, but retains programmable settings
• Choose among the following memory organizations:
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
IDT72V2103
IDT72V2113
131,072 x 18/262,144 x 9
262,144 x 18/524,288 x 9
• Functionally compatible with the IDT72V255LA/72V265LA and • Selectable synchronous/asynchronous timing modes for Almost-
IDT72V275/72V285 SuperSync FIFOs
Empty and Almost-Full flags
• Up to 166 MHz Operation of the Clocks
• Program programmable flags by either serial or parallel means
• User selectable Asynchronous read and/or write ports (BGA Only) • Select IDT Standard timing (using EF and FF flags) or First Word
• 7.5 ns read/write cycle time (5.0 ns access time)
• User selectable input and output port bus-sizing
- x9 in to x9 out
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
• JTAG port, provided for Boundary Scan function (BGA Only)
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Big-Endian/Little-Endian user selectable byte representation
• 5V tolerant inputs
• Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball
Grid Array (BGA) (with additional features)
• Fixed, low first word latency
• Zero latency retransmit
• Pin compatible to the SuperSync II (IDT72V223/72V233/72V243/
72V253/72V263/72V273/72V283/72V293)family
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
D0 -Dn (x9 or x18)
LD SEN
*Available on the
BGA package only.
WEN WCLK/WR
*
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
ASYW
HF
*
RAM ARRAY
FWFT/SI
PFM
131,072 x 18 or 262,144 x 9
262,144 x 18 or 524,288 x 9
FSEL0
FSEL1
WRITE POINTER
READ POINTER
BE
CONTROL
LOGIC
IP
RT
RM
ASYR
READ
CONTROL
LOGIC
OUTPUT REGISTER
IW
OW
BUS
*
CONFIGURATION
MRS
PRS
RESET
LOGIC
RCLK/RD
*
REN
TCK
*
*
TRST
JTAG CONTROL
(BOUNDARY
SCAN)
*
TMS
6119 drw01
*
TDI
*
Q0 -Qn (x9 or x18)
OE
TDO
*
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
SEPTEMBER 2003
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6119/10
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothetimeitcanberead,isnowfixedandshort.(Thevariable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
• Asynchronous/Synchronoustranslationonthereadorwriteports.
• Highdensityofferingsupto4Mbit.
Bus-MatchingSuperSyncFIFOsareparticularlyappropriatefornetwork,
video,telecommunications,datacommunicationsandotherapplicationsthat
needtobufferlargeamountsofdataandmatchbussesofunequalsizes.
DESCRIPTION:
The IDT72V2103/72V2113 are exceptionally deep, high speed, CMOS
First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrolsanda
flexibleBus-Matchingx9/x18dataflow.TheseFIFOsoffernumerousimprove-
mentsoverpreviousSuperSyncFIFOs,includingthefollowing:
• Flexible x9/x18 Bus-Matching on both read and write ports.
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
beenremoved.TheFrequencySelectpin(FS)has beenremoved,thus it
isnolongernecessarytoselectwhichofthetwoclockinputs,RCLKorWCLK,
is runningatthe higherfrequency.
PIN CONFIGURATIONS
INDEX
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RT
OE
WEN
SEN
DNC(1)
2
3
4
5
6
7
8
VCC
VCC
Q17
Q16
GND
GND
Q15
DNC(1)
IW
GND
D17
VCC
9
Q14
D16
D15
D14
D13
GND
D12
D11
D10
D9
10
11
12
13
14
15
16
17
18
19
20
VCC
Q13
Q12
GND
Q11
GND
Q10
VCC
Q9
Q8
Q7
D8
VCC
6119 drw02
NOTE:
1. DNC = Do Not Connect.
TQFP (PN80-1, order code: PF)
TOP VIEW
2
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe
FIFO.Datais readonarisingedgeofRD,theRENinputshouldbetiedtoits
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
theFIFOmustbeconfiguredforStandardIDTmode,andtheOEinputused
toprovidethree-statecontroloftheoutputs,Qn.
DESCRIPTION(CONTINUED)
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeitheran18-bitora9-bitwidthasdeterminedbythestate
ofexternalcontrolpinsInputWidth(IW)andOutputWidth(OW)duringtheMaster
Resetcycle.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence.Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data
presentontheDndatainputs is writtenintotheFIFOoneveryrisingedgeof
WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR
inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR,
theWENinputshouldbetiedtoitsactivestate,(LOW).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
orAsynchronousinterface.DuringSynchronousoperationtheoutputportis
controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
PINCONFIGURATIONS(CONTINUED)
A1 BALL PAD CORNER
A
PRS
MRS
SEN
LD
PAF
BE
ASYR
REN
RCLK
OE
WCLK
WEN
FSEL0
PFM
RM
EF/OR
RT
B
C
HF
PAE
FWFT/SI OW
FSEL1
IP
ASYW
FF/IR
VCC
VCC
VCC
VCC
VCC
D
E
D17
D16
IW
V
CC
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
CC
Q16
Q14
Q17
Q15
D15
VCC
V
F
Q12
Q10
Q8
D14
D12
D9
V
CC
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
Q13
Q11
Q9
D13
D11
D8
G
V
CC
VCC
H
J
D10
D2
VCC
VCC
VCC
VCC
Q1
Q2
TCK
D6
D7
D0
TMS
TDO
Q4
Q7
K
D5
D4
D3
D1
TDI
Q0
Q3
Q5
Q6
TRST
1
2
3
4
5
6
7
8
9
10
6119 drw02b
BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC)
TOP VIEW
3
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
Forserialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK,
DESCRIPTION(CONTINUED)
are used to load the offset registers via the Serial Input (SI). For parallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadthe offsetregisters via Dn.REN togetherwithLD oneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DuringMasterReset(MRS)thefollowingeventsoccur:thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standardmode orFWFTmode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming
modeandoffsetsineffect.PRSisusefulforresettingadeviceinmid-operation,
whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
not have to be asserted for accessing the first word. However, subsequent
words writtentotheFIFOdorequireaLOWonREN foraccess.Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs ofthe next). Noexternallogicis required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag).TheEFandFF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory.Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial.Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary.Thedefaultoffsetvaluesaresetduring
MasterResetbythe state ofthe FSEL0, FSEL1, and LD pins.
Ifasynchronous PAE/PAFconfigurationisselected,thePAEisasserted
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK/RD*)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK/WR*)
WRITE ENABLE (WEN)
LOAD (LD)
IDT
72V2103
72V2113
(x9 or x18) DATA IN (D
0
- D
n
)
(x9 or x18) DATA OUT (Q0 - Qn)
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
SERIAL CLOCK (SCLK)
FIRST WORD FALL THROUGH/SERIAL
INPUT (FWFT/SI)
FULL FLAG/INPUT READY (FF/IR)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
PROGRAMMABLE ALMOST-FULL (PAF)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
6119 drw03
INPUT WIDTH
(IW)
OUTPUT WIDTH
(OW)
Figure 1. Single Device Configuration Signal Flow Diagram
4
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO
willbereadoutfirst,followedbythemostsignificantbyte.Themodedesiredis
configuredduringmasterresetbythestateoftheBig-Endian(BE)pin.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitislocatedinbitpositionD8duringtheparallel
programmingoftheflagoffsets.IfNon-InterspersedParitymodeisselected,then
D8isassumedtobeavalidbitandD16andD17areignored.IPmodeisselected
duringMasterResetbythestateoftheIPinputpin.Thismodeisrelevantonly
whentheinputwidthis settox18mode.InterspersedParitycontrolonlyhas
aneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthe
data writtentoandreadfromthe FIFO.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
BoundaryScanArchitecture.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized.Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
TheIDT72V2103/72V2113arefabricatedusingIDT’shighspeedsubmi-
cronCMOStechnology.
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringmasterresetbythestateoftheProgrammableFlag
Mode (PFM) pin.
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan
once.ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit
operationbysettingthereadpointertothefirstlocationofthememoryarray.
Azero-latencyretransmittimingmodecanbeselectedusingtheRetransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero-
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero-latency retransmit operation is selected the first data word to be
retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK
edgethatinitiatedtheretransmitbasedonRTbeingLOW.
RefertoFigure11and12forRetransmitTimingwithnormallatency.Refer
to Figure 13 and 14 for Retransmit Timing with zero-latency.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
useful when data is written into the FIFO in long word format (x18) and read
outoftheFIFOinsmallword(x9)format.IfBig-Endianmodeisselected,then
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IW
OW
Write Port Width
Read Port Width
L
L
L
H
L
x18
x18
x9
x18
x9
H
H
x18
x9
H
x9
5
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
PIN DESCRIPTION (TQFP & BGA PACKAGES)
Symbol
Name
I/O
Description
(1)
BE
*Big-Endian/
Little-Endian
I
DuringMasterReset, a LOWonBE willselectBig-Endianoperation. AHIGHonBE duringMasterResetwill
selectLittle-Endianformat.
D0–D17 DataInputs
I
Data inputs for a 18- or 9-bit bus. When in 18-bit mode, D0–D17 are used. When in 9-bit mode, D0–D8 are used
andthe unusedinputs, D9–D17, shouldbe tiedLOW.
EF/OR EmptyFlag/
O
O
IntheIDTStandardmode, the EFfunctionis selected. EF indicates whetherornotthe FIFOmemoryis empty.In
FWFTmode,theORfunctionisselected.OR indicateswhetherornotthereisvaliddataavailableattheoutputs.
Inthe IDTStandardmode, the FF functionis selected.FF indicates whetherornotthe FIFOmemoryis full. Inthe
FWFTmode,the IRfunctionisselected.IRindicateswhetherornotthereisspaceavailableforwritingtotheFIFO
memory.
OutputReady
FF/IR
Full Flag/
Input Ready
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
I
I
I
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe
programmableflagsPAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.AfterMasterReset,thispinfunctions
asaserialinputforloadingoffsetregisters.
FWFT/SI FirstWordFall
Through/Serial In
HF
IP(1)
Half-FullFlag
O
I
HF indicates whethertheFIFOmemoryis moreorless thanhalf-full.
InterspersedParity
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.AHIGHwillselectInterspersed
Paritymode. InterspersedParitycontrolonlyhasaneffectduringparallelprogrammingoftheoffsetregisters.It
doesnoteffectthedatawrittentoandreadfromtheFIFO.
(1)
IW
InputWidth
Load
I
I
This pinselects the bus widthofthe write port. DuringMasterReset, whenIWis LOW, the write portwillbe
configured with a x18 bus width. If IW is HIGH, the write port will be a x9 bus width.
LD
Thisisadualpurposepin.DuringMasterReset,thestateoftheLDinput,alongwithFSEL0andFSEL1,determines
oneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscan
beprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswritingtoandreadingfromthe
offsetregisters.
MRS
MasterReset
I
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringMasterReset,the
FIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,oneofeightprogrammable
flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatency
timingmode,interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
OE
OW
OutputEnable
OutputWidth
I
I
OEcontrolstheoutputimpedanceofQn.
This pinselects the bus widthofthe readport. DuringMasterReset, whenOWis LOW, the readportwillbeconfig-
ured with a x18 bus width. If OW is HIGH, the read port will be a x9 bus width.
(1)
PAE
PAF
Programmable
Almost-EmptyFlag
O
O
I
PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmptyOffset
register. PAE goes HIGHifthe numberofwords inthe FIFOmemoryis greaterthanorequaltooffsetn.
PAF goes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedinthe
FullOffsetregister. PAFgoes LOWifthenumberoffreelocations intheFIFOmemoryis less thanorequaltom.
DuringMasterReset,aLOWonPFMwillselectAsynchronous Programmableflagtimingmode.AHIGHonPFM
willselectSynchronousProgrammableflagtimingmode.
Programmable
Almost-FullFlag
(1)
PFM
Programmable
Flag Mode
PRS
PartialReset
I
PRS initializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings are
allretained.
Q0–Q17 DataOutputs
O
Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q0–Q17 are used and when in 9-bit mode, Q0–Q8 are
used,andtheunusedoutputs,Q9-Q17 shouldnotbeconnected.Outputsarenot5Vtolerantregardlessofthe
stateofOE.
REN
ReadEnable
I
I
RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
RCLK/ ReadClock/
RD
If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevaluesloaded
intothe offsetregisters is outputona risingedge ofRCLK. IfAsynchronous operationofthe readporthas been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
Asynchronous operationofthe RCLK/RDinputis onlyavailable inthe BGApackage.
ReadStrobe
NOTE:
1. Inputs should not change state after Master Reset.
6
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES)
Symbol
Name
I/O
Description
(1)
RM
RetransmitTiming
Mode
I
DuringMasterReset,aLOWonRMwillselectzerolatencyRetransmittimingMode.AHIGHonRMwillselect
normallatencymode.
RT
Retransmit
I
RT assertedonthe risingedge ofRCLKinitializes the READpointertozero, sets the EF flagtoLOW(OR toHIGH
inFWFTmode)anddoesnotdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammable
flagsettings.RTisusefultorereaddatafromthefirstphysicallocationoftheFIFO.
SEN
WCLK/
WR
SerialEnable
I
I
SENenablesserialloadingofprogrammableflagoffsets.
WriteClock/
WriteStrobe
If Synchronous operation of the write port has been selected, when enabled byWEN, the risingedge ofWCLK
writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdataintothe
FIFOonarisingedgeinanAsynchronousmanner,(WENshouldbetiedtoitsactivestate).Asynchronousoperation
oftheWCLK/WRinputisonlyavailableintheBGApackage.
WEN
VCC
WriteEnable
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
These are VCC supply inputs and must be connected to the 3.3V supply rail.
+3.3VSupply
NOTE:
1. Inputs should not change state after Master Reset.
PIN DESCRIPTION (BGA PACKAGE ONLY)
Symbol
Name
I/O
Description
(1)
ASYR
Asynchronous
ReadPort
I
AHIGHonthis inputduringMasterResetwillselectSynchronous readoperationfortheoutputport.ALOW
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
(1)
ASYW
Asynchronous
WritePort
I
I
AHIGHonthis inputduringMasterResetwillselectSynchronous writeoperationfortheinputport.ALOW
willselectAsynchronousoperation.
(2)
TCK
JTAGClock
ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperationsofthe
devicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedgeofTCKandoutputschange
onthefallingedgeofTCK.IftheJTAGfunctionis notusedthis signalneeds tobetiedtoGND.
(2)
TDI
JTAGTestData
Input
I
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister.
Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData
Output
O
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass
Register.This outputis highimpedanceexceptwhenshifting,whileinSHIFT-DRandSHIFT-IRcontrollerstates.
TMS(2)
JTAGMode
JTAGReset
I
I
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough
itsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerwillautomaticallyresetupon
power-up.IftheJTAGfunctionis notusedthenthis signalshouldtobetiedtoGND.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 41-45 and Figures 31-33.
7
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Com'l & Ind'l
Unit
(2)
Symbol
Parameter
Supply Voltage (Com'l & Ind'l)
Min.
3.15
0
Typ. Max. Unit
VTERM
TerminalVoltage
with respect to GND
–0.5to+4.5
V
(1)
VCC
3.3
0
3.45
0
V
V
TSTG
IOUT
StorageTemperature
–55to+125
–50 to +50
° C
GND Supply Voltage (Com'l & Ind'l)
(2)
VIH
Input High Voltage (Com'l & Ind'l)
Input Low Voltage (Com'l & Ind'l)
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
2.0
—
0
—
—
—
—
5.5
0.8
+70
+85
V
DC Output Current
mA
(3)
VIL
TA
V
NOTE:
° C
° C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TA
-40
NOTES:
1. VCC=3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
2. VCC terminal only.
3. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72V2103L
IDT72V2113L
Commercial and Industrial(1)
tCLK = 6, 7.5, 10, 15 ns
Symbol
Parameter
Min.
–1
Max.
1
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
µA
µA
V
ILO(3)
–10
2.4
—
10
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current (x9 Input to x9 Output)
Active Power Supply Current (x18 Input to x18 Output)
StandbyCurrent
—
0.4
30
VOL
V
ICC1(4,5,6)
ICC1(4,5,6)
ICC2(4,7)
—
mA
mA
mA
—
35
—
15
NOTES:
1. Industrial temperature range product for the 10ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. For x 18 bus widths, typical ICC1 = 5 + fS + 0.002*CL*fS (in mA);
for x 9 bus widths, typical ICC1 = 5 + 0.775*fS + 0.002*CL*fS (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input
Conditions
Max.
Unit
(2)
CIN
VIN = 0V
10
pF
Capacitance
Output
(1,2)
COUT
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
8
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
(2)
Commercial
BGA & TQFP
Commercial
BGA & TQFP
Com’l & Ind’l
TQFP Only
Commercial
TQFP Only
IDT72V2103L6
IDT72V2113L6
IDT72V2103L7-5 IDT72V2103L10 IDT72V2103L15
IDT72V2113L7-5 IDT72V2113L10 IDT72V2113L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
DataAccessTime(5)
Clock Cycle Time
Clock High Time
Clock Low Time
—
166
—
133.3
—
1(5)
100
—
66.7
MHz
(5)
tA
1
6
4
1
5
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
6
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
1(5)
15
6
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
4
7.5
3.5
3.5
2.5
0.5
2.5
0.5
3.5
0.5
10
10
2.7
2.7
2
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
6
DataSetupTime
4
tDH
DataHoldTime
0.5
2
1
tENS
tENH
tLDS
EnableSetupTime
EnableHoldTime
LoadSetupTime
4
0.5
3
1
4
tLDH
tRS
LoadHoldTime
0.5
10
15
10
—
3
1
ResetPulseWidth(3)
ResetSetupTime
ResetRecoveryTime
15
15
15
—
4
tRSS
tRSR
tRSF
tRTS
tOLZ
tOE
15
15
10
10
ResettoFlagandOutputTime
RetransmitSetupTime
—
3.5
0
—
3.5
0
—
—
6
(4)
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid(5)
0
0
(5)
1
1
1(5)
1(5)
—
—
—
—
—
—
—
7
1(5)
1(5)
—
—
—
—
—
—
—
9
(4,5)
(5)
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
OutputEnabletoOutputinHighZ
1
4
1
6
6
8
Write Clock to FF or IR
Read Clock to EF or OR
—
—
—
—
—
—
—
4
4
—
—
—
—
—
—
—
5
5
6.5
6.5
16
10
10
20
10
20
10
20
—
—
4
5
ClocktoAsynchronousProgrammableAlmost-FullFlag
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
Clock to HF
10
4
12.5
5
6.5
16
10
4
12.5
5
6.5
16
10
—
—
12.5
—
—
tSKEW1
tSKEW2
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
—
—
5
7
10
14
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 10ns is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7.5ns, 10ns and 15ns the minimum for tA, tOE, and tOHZ is 2ns.
9
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(1)—ASYNCHRONOUSTIMING
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
IDT72V2103L6
IDT72V2113L6
IDT72V2103L7-5
IDT72V2113L7-5
Symbol
Parameter
Cycle Frequency (Asynchronous mode)
DataAccessTime
Min.
—
0.6
10
Max.
Min.
—
0.6
12
Max.
83
Unit
MHz
ns
(4)
fA
100
8
(4)
tAA
10
(4)
tCYC
Cycle Time
—
—
—
—
8
—
—
—
—
10
ns
(4)
tCYH
Cycle HIGH Time
4.5
4.5
8
5
ns
(4)
tCYL
Cycle LOW Time
5
ns
(4)
tRPE
Read Pulse after EF HIGH
Clock to Asynchronous FF
Clock to Asynchronous EF
ClocktoAsynchronousProgrammableAlmost-FullFlag
10
ns
(4)
tFFA
—
—
—
—
—
—
—
—
ns
(4)
tEFA
8
10
ns
(4)
tPAFA
8
10
ns
(4)
tPAEA
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
8
10
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Parameters apply to the BGA package only.
10
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ACTESTLOADS-6ns,7.5nsSpeedGrades
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns(1)
1.5V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load for tCLK = 10ns, 15 ns
OutputLoadfortCLK =6ns,7.5ns
1.5V
50Ω
1.5V
See Figure 2a
See Figure 2b & 2c
Z0 = 50Ω
I/O
6119 drw04a
NOTE:
Figure 2b. AC Test Load
1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns.
ACTESTLOADS-10ns,15nsSpeedGrades
6
5
4
3
2
1
3.3V
330Ω
D.U.T.
20 30 50 80 100
Capacitance (pF)
200
30pF*
510Ω
6119 drw04b
Figure 2c. Lumped Capacitive Load, Typical Derating
6119 drw04
Figure 2a. Output Load
* Includes jig and scope capacitances.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
Output
Normally
LOW
VCC
2
V
2
CC
100mV
100mV
100mV
VOL
VOH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
6119 drw04c
NOTE:
1. REN is HIGH.
11
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
If the FIFO is full, the first read operation will cause FF to go HIGH.
FUNCTIONALDESCRIPTION
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
TheIDT72V2103/72V2113supporttwodifferenttimingmodesofopera-
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selectionofwhichmodewilloperateisdeterminedduringMasterReset,by
thestateoftheFWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbe selected. This mode uses the EmptyFlag(EF)toindicate whetheror
notthereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOhasanyfreespaceforwriting.InIDT
Standardmode, everywordreadfromthe FIFO, includingthe first, mustbe
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,REN=LOWisnotnecessary.Subsequentwordsmustbeaccessed
using the Read Enable (REN) and RCLK.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable4.TowritedataintotheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern+2words havebeenloadedintotheFIFO,wherenis theempty
offsetvalue.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2.Thisparameterisalsouserprogrammable.SeesectiononProgrammable
FlagOffsetLoading.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHFwouldtoggletoLOWoncethe(D/2+2)
wordswerewrittenintotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,
(D/2+ 2) = the65,538thwordfortheIDT72V2103and131,074thwordforthe
IDT72V2113. If both x9 Input and x9 Output bus Widths are selected,
(D/2 + 2) = the131,074thwordfortheIDT72V2103and262,146thwordfor
theIDT72V2113.ContinuingtowritedataintotheFIFOwillcausethePAFto
goLOW.Again,ifnoreadsareperformed,thePAFwillgoLOWafter(D-m)writes
totheFIFO.Ifx18Inputorx18OutputbusWidthisselected,(D-m) = (131,073-m)
writesfortheIDT72V2103and(262,145-m)writesfortheIDT72V2113.Ifboth
x9Inputandx9OutputbusWidthsareselected,(D-m)=(262,145-m)writes
fortheIDT72V2103and(524,289-m)writes fortheIDT72V2113.Theoffset
misthefulloffsetvalue.Thedefaultsettingforthesevaluesarestatedinthe
footnoteofTable2.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations.Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected,
D = 131,073writesfortheIDT72V2103and262,145writesfortheIDT72V2113.
Ifbothx9Inputandx9OutputbusWidthsareselected,D=262,145writesfor
theIDT72V2103and524,289writesfortheIDT72V2113,respectively.Note
thattheadditionalwordinFWFTmodeisduetothecapacityofthememoryplus
outputregister.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditionsdescribedinTable4.Iffurtherreadoperationsoccur,withoutwrite
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,ORwillgo
HIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOisempty.
When configured in FWFT mode, the OR flag output is triple register-
buffered,andtheIRflagoutputisdoubleregister-buffered.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable3.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
(D/2+1)wordswerewrittenintotheFIFO.Ifx18Inputorx18OutputbusWidth
isselected,(D/2+1)=the65,537thwordfortheIDT72V2103and131,073rd
word for the IDT72V2113. If both x9 Input and x9 Output bus Widths are
selected,(D/2 + 1)=the131,073rdwordfortheIDT72V2103and262,145th
wordfortheIDT72V2113.ContinuingtowritedataintotheFIFOwillcausethe
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed,thePAFwillgoLOWafter(D-m)writestotheFIFO.Ifx18Inputor
x18OutputbusWidthisselected,(D-m) = (131,072-m)writesfortheIDT72V2103
and(262,144-m)writesfortheIDT72V2113.Ifbothx9Inputandx9Outputbus
Widths are selected, (D-m) = (262,144-m) writes for the IDT72V2103 and
(524,288-m)writesfortheIDT72V2113.Theoffset“m”isthefulloffsetvalue.
ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.This
parameter is also user programmable. See section on Programmable Flag
OffsetLoading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
totheFIFO.Ifthex18Inputorx18OutputbusWidthisselected,D=131,072
writesfortheIDT72V2103and262,144writesfortheIDT72V2113.Ifbothx9
Input and x9 Output bus Widths are selected, D = 262,144 writes for the
IDT72V2103 and 524,288 writes for the IDT72V2113, respectively.
RelevanttimingdiagramsforFWFTmodecanbefoundinFigure9,10and
12.
12
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
PROGRAMMING FLAG OFFSETS
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V2103/ thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
72V2113hasinternalregistersfortheseoffsets.Thereareeightdefaultoffset Foramoredetaileddescription,seediscussionthatfollows.
valuesselectableduringMasterReset.TheseoffsetvaluesareshowninTable
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
2.OffsetvaluescanalsobeprogrammedintotheFIFOinoneoftwoways;serial MasterReset,regardlessofwhetherserialorparallelprogramminghasbeen
orparallelloadingmethod.Theselectionoftheloadingmethodisdoneusing selected.Validprogrammingranges arefrom0toD-1.
theLD (Load)pin.DuringMasterReset,thestateoftheLDinputdetermines
whetherserialorparallelflagoffsetprogrammingis enabled. AHIGHonLD SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
duringMasterResetselectsserialloadingofoffsetvalues.ALOWonLDduring TIMING SELECTION
MasterResetselectsparallelloadingofoffsetvalues.
The IDT72V2103/72V2113 can be configured during the Master Reset
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread cyclewitheithersynchronousorasynchronoustimingforPAFandPAEflags
thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport by use of the PFM pin.
Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis
notpossibletoreadtheoffsetvaluesinserialfashion.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
notRCLK.Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure18forsynchronous
PAF timingandFigure19forsynchronous PAEtiming.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK.Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure
20forasynchronousPAFtimingandFigure21forasynchronousPAEtiming.
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
IDT72V2103, IDT72V2113
LD
L
L
FSEL0
FSEL1
H
L
H
H
L
Offsets n,m
16,383
8,191
4,095
2,047
1,023
511
L
H
H
L
L
H
H
L
H
H
H
H
L
H
255
L
L
L
127
LD
FSEL0
FSEL1
Program Mode
(3)
H
L
X
X
X
X
Serial
(4)
Parallel
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
13
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE
IW = OW = x9
IDT72V2103
IDT72V2113
IDT72V2113
IW OW or
≠
HF
PAE EF
IDT72V2103
FF PAF
IW = OW = x18
0
0
H
H
H
H
H
H
H
H
H
H
H
L
L
L
0
1 to n
1 to n
1 to n
L
H
H
H
Number of
Words in
FIFO
(n+1) to 131,072
(n+1) to 262,144
262,145 to (524,288-(m+1))
(524,288-m) to 524,287
524,288
(n+1) to 65,536
65,537 to (131,072-(m+1))
(131,072-m) to 131,071
131,072
H
H
131,073 to (262,144-(m+1))
(262,144-m) to 262,143
262,144
H
L
L
L
L
L
H
H
H
H
NOTE:
1. See Table 2 for values for n, m.
TABLE 4 STATUS FLAGS FOR FWFT MODE
IW = OW = x9
IDT72V2103
IDT72V2113
IW OW or
IW = OW = x18
≠
IDT72V2103
IDT72V2113
HF PAE OR
IR PAF
L
L
L
L
H
H
H
H
H
H
H
L
L
H
L
0
0
0
L
1 to n+1
1 to n+1
1 to n+1
Number of
Words in
H
H
L
(n+2) to 65,537
65,538 to (131,073-(m+1))
(n+2) to 131,073
(n+2) to 262,145
262,146 to (524,289-(m+1))
L
131,074 to (262,145-(m+1))
(2)
FIFO
L
L
L
L
L
H
H
L
L
(524,289-m) to 524,288
524,289
(131,073-m) to 131,072
131,073
(262,145-m) to 262,144
262,145
H
4666 drw05
NOTE:
1. See Table 2 for values for n, m.
2. Number of Words in FIFO = FIFO Depth + Output Register
14
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
1st Parallel Offset Write/Read Cycle
D/Q8
1st Parallel Offset Write/Read Cycle
D/Q0
D/Q17
Data Inputs/Outputs
EMPTY OFFSET (LSB) REGISTER
D/Q16
D/Q0
EMPTY OFFSET REGISTER
Non-Interspersed
Parity
16 15 14 13 12 11 10
16 15 14 13 12 11 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
8
7
6
5
4
3
2
1
9
Interspersed
Parity
D/Q8
2nd Parallel Offset Write/Read Cycle
D/Q8
# of Bits Used
D/Q0
2nd Parallel Offset Write/Read Cycle
D/Q17
EMPTY OFFSET REGISTER
15 14 13 12
Data Inputs/Outputs
EMPTY OFFSET (MSB) REGISTER
D/Q0
D/Q16
16
11
19
10
18
9
18 17
18 17
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
3rd Parallel Offset Write/Read Cycle
EMPTY OFFSET REGISTER
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
17
FULL OFFSET (LSB) REGISTER
16 15 14 13 12 11 10
16 15 14 13 12 11 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
4th Parallel Offset Write/Read Cycle
9
D/Q8
D/Q0
D/Q8
FULL OFFSET REGISTER
4th Parallel Offset Write/Read Cycle
D/Q17
8
7
6
5
4
3
2
1
Data Inputs/Outputs
FULL OFFSET (MSB) REGISTER
D/Q0
D/Q16
5th Parallel Offset Write/Read Cycle
D/Q8
18 17
18 17
D/Q0
FULL OFFSET REGISTER
15 14 13 12
IDT72V2103/72V2113 x18 Bus Width
16
11
10
9
6119 drw 06
x9 to x9 Mode
# of Bits Used:
6th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
18 bits for the IDT72V2103
19 bits for the IDT72V2113
Note: All unused bits of the
LSB & MSB are don’t care
FULL OFFSET REGISTER
19
18
17
All Other Modes
# of Bits Used:
IDT72V2103/72V2113 x9 Bus Width
17 bits for the IDT72V2103
18 bits for the IDT72V2113
Note: All unused bits of the
LSB & MSB are don’t care
Figure 3. Programmable Flag Offset Programming Sequence
15
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V2103
IDT72V2113
WCLK
RCLK
X
LD WEN REN SEN
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
0
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
1
0
1
Full Offset (MSB)
x9 to x9 Mode
All Other Modes
Serial shift into registers:
34 bits for the IDT72V2103
36 bits for the IDT72V2113
Serial shift into registers:
36 bits for the IDT72V2103
38 bits for the IDT72V2113
0
1
1
0
X
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
1
1
1
No Operation
1
1
1
0
X
1
X
0
1
X
X
X
Write Memory
X
X
Read Memory
No Operation
X
6119 drw06b
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
16
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
SERIAL PROGRAMMING MODE
Notethatforx9buswidth,oneextraWritecycleisrequiredforboththeEmpty
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then OffsetRegisterandFullOffsetRegister. See Figure 16, ParallelLoadingof
programmingofPAEandPAFvaluescanbeachievedbyusingacombination ProgrammableFlagRegisters,forthetimingdiagramforthismode.
oftheLD,SEN,WCLKandSIinputpins.ProgrammingPAEandPAFproceeds
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
as follows:whenLD andSEN are setLOW, data onthe SIinputare written, pointer. The act of reading offsets employs a dedicated read offset register
onebitforeachWCLKrisingedge,startingwiththeEmptyOffsetLSBandending pointer.Thetwopointersoperateindependently;however,areadandawrite
withtheFullOffsetMSB.Ifx9tox9modeis selected,atotalof36bits forthe shouldnotbeperformedsimultaneouslytotheoffsetregisters.AMasterReset
IDT72V2103and38bitsfortheIDT72V2113.Foranyothermodeofoperation initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
(thatincludesx18buswidthoneithertheInputorOutput),minus2bitsfromthe noeffectonthepositionofthesepointers.RefertoFigure3,Programmable
values above. So, a total of 34 bits for the IDT72V2103 and 36 bits for the FlagOffsetProgrammingSequence,foradetaileddiagramofthedatainput
IDT72V2113. See Figure 15, Serial Loading of Programmable Flag Regis- lines D0-Dnusedduringparallelprogramming.
ters,forthetimingdiagramforthismode.
Write operations to the FIFO are allowed before and during the parallel
Using the serial method, individual registers cannot be programmed programmingsequence.Inthiscase,theprogrammingofalloffsetregisters
selectively.PAEandPAFcanshowavalidstatusonlyafterthecompleteset does nothavetooccuratonetime.One,twoormoreoffsetregisters canbe
of bits (for all offset registers) has been entered. The registers can be writtenandthenbybringingLDHIGH,writeoperations canberedirectedto
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered.When theFIFOmemory.WhenLDissetLOWagain,andWENisLOW,thenextoffset
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
registerinsequenceiswrittento.AsanalternativetoholdingWENLOWand
Write operations to the FIFO are allowed before and during the serial togglingLD,parallelprogrammingcanalsobeinterruptedbysettingLDLOW
programmingsequence.Inthiscase,theprogrammingofalloffsetbitsdoesnot andtogglingWEN.
havetooccuratonce.AselectnumberofbitscanbewrittentotheSIinputand
Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid
then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia during the programming process. From the time parallel programming has
DnbytogglingWEN.WhenWENisbroughtHIGHwithLDandSENrestored begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset
toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI.Ifan wordhasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfrom
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW therisingWCLKedgethatachievestheabovecriteria;PAFwillbevalidafter
anddeactivateSENortosetSENLOWanddeactivateLD.OnceLDandSEN twomorerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen registerpointer.ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
written.MeasuringfromtherisingWCLKedgethatachievestheabovecriteria; pinswhenLDissetLOWandRENissetLOW.IftheFIFOisconfiguredforan
PAFwillbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalid inputbuswidthandoutputbuswidthbothsettox9,thenthetotalnumberofread
afterthe nexttworisingRCLKedges plus tPAE plus tSKEW2.
Itis notpossibletoreadtheflagoffsetvalues inaserialmode.
operations required to read the offset registers is 6 for the IDT72V2103/
72V2113. Refer to Figure 3, Programmable Flag Offset Programming
Sequence, for a detailed diagram of the data input lines D0-Dn used during
parallelprogramming.IftheFIFOisconfiguredforaninputtooutputbuswidth
PARALLELPROGRAMMINGMODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then of x9 to x18, x18 to x9 or x18 to x18, then the following number of read
programmingofPAEandPAFvaluescanbeachievedbyusingacombination operations are required: for an output bus width of x18 a total of 4 read
oftheLD,WCLK,WENandDninputpins.IftheFIFOisconfiguredforaninput operationswillberequiredfortheIDT72V2103/72V2113.Foranoutputbus
bus widthandoutputbus widthbothsettox9, thenthe totalnumberofwrite widthofx9atotalof6willberequiredfortheIDT72V2103/72V2113.Referto
operations requiredtoprogramtheoffsetregisters is 6fortheIDT72V2103/ Figure3,ProgrammableFlagOffsetProgrammingSequence,foradetailed
72V2113. Refer to Figure 3, Programmable Flag Offset Programming diagram.Forexample,readingPAEandPAFontheIDT72V2103/72V2113
Sequence, for a detailed diagram of the data input lines D0-Dn used during configuredforx18bus widthproceeds as follows:dataarereadviaQn from
parallelprogramming.IftheFIFOisconfiguredforaninputtooutputbuswidth theEmptyOffsetRegisteronthefirstandsecondLOW-to-HIGHtransitionof
ofx9tox18,x18tox9orx18tox18,thenthefollowingnumberofwriteoperations RCLK.UponthethirdandfourthLOW-to-HIGHtransitionofRCLK,dataare
are required. For an input bus width of x18 total of 4 write operations will be readfromtheFullOffsetRegister.ThefifthandsixthtransitionofRCLKreads,
requiredfortheIDT72V2103/72V2113.Foraninputbuswidthofx9atotalof onceagain,fromtheEmptyOffsetRegister.Notethatforax9buswidth,one
6willberequiredfortheIDT72V2103/72V2113.RefertoFigure3,Program- extraReadcycleisrequiredforboththeEmptyOffsetRegisterandFullOffset
mable Flag Offset Programming Sequence, for a detailed diagram.
Register.SeeFigure17,ParallelReadofProgrammableFlagRegisters,for
Forexample,programmingPAEandPAFontheIDT72V2103/72V2113 thetimingdiagramforthismode.
configuredforx18buswidthproceedsasfollows:whenLDandWENareset
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
LOW,dataontheinputsDnarewrittenintotheLSBoftheEmptyOffsetRegister writestotheFIFO.TheinterruptionisaccomplishedbydeassertingREN,LD,
onthefirstLOW-to-HIGHtransitionofWCLK.UponthesecondLOW-to-HIGH orbothtogether.WhenRENandLD arerestoredtoaLOWlevel,readingof
transitionofWCLK,dataarewrittenintotheMSBoftheEmptyOffsetRegister. theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
OnthethirdLOW-to-HIGHtransitionofWCLK,dataarewrittenintotheLSBof betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
theFullOffsetRegister.OnthefourthLOW-to-HIGHtransitionofWCLK,data the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
are written into the MSB of the Full Offset Register. The fifth LOW-to-HIGH
Parallelreadingoftheoffsetregisters is always permittedregardless of
transitionofWCLK,dataarewritten,onceagaintotheEmptyOffsetRegister. whichtimingmode (IDTStandardorFWFTmodes)has beenselected.
17
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
RETRANSMITOPERATION
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
The Retransmit operation allows data that has already been read to be requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
accessedagain.Thereare2modesofRetransmitoperation,normallatency Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
andzerolatency.TherearetwostagestoRetransmit:first,asetupprocedure
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
that resets the read pointer to the first location of memory, then the actual setupbysettingOR HIGH.Duringthis period,theinternalreadpointeris set
retransmit,whichconsistsofreadingoutthememorycontents,startingatthe tothefirstlocationoftheRAMarray.
beginningofmemory.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge. contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
RENandWENmustbeHIGHbeforebringingRTLOW.Whenzerolatencyis thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
utilized,RENdoesnotneedtobeHIGHbeforebringingRTLOW.Atleasttwo all subsequent words requires a LOW on REN to enable the rising edge of
words, butnomorethanD-2 words should have been written into the FIFO, RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
and read from the FIFO, between Reset (Master or Partial) and the time of diagram.
Retransmitsetup.Ifx18Inputorx18OutputbusWidthisselected,D=131,072
ForeitherIDTStandardmodeorFWFTmode,updatingofthePAE,HFand
fortheIDT72V2103and262,144fortheIDT72V2113.Ifbothx9Inputandx9 PAF flags beginwiththe risingedge ofRCLKthatthe RT is setupon. PAEis
OutputbusWidthsareselected,D=262,144fortheIDT72V2103and524,288 synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafterRTissetup,
for the IDT72V2113. In FWFT mode, if x18 Input or x18 Output bus Width is thePAEflagwillbeupdated.HFisasynchronous,thustherisingedgeofRCLK
selected,D=131,073fortheIDT72V2103and262,145fortheIDT72V2113. thatRTissetupwillupdateHF.PAFissynchronizedtoWCLK,thusthesecond
If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the risingedgeofWCLKthatoccurstSKEW aftertherisingedgeofRCLKthatRT
IDT72V2103 and 524,289 for the IDT72V2113.
is setup will update PAF. RT is synchronized to RCLK.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
TheRetransmitfunctionhastheoptionof2modesofoperation,either"normal
RetransmitsetupbysettingEFLOW.Thechangeinlevelwillonlybenoticeable latency" or "zero latency". Figure 11 and Figure 12 mentioned previously,
if EF was HIGH before setup. During this period, the internal read pointer is relate to "normal latency". Figure 13 and Figure 14 show "zero latency"
initializedtothefirstlocationoftheRAMarray.
retransmitoperation.Zerolatencybasicallymeansthatthefirstdatawordtobe
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations retransmitted,isplacedontotheoutputregisterwithrespecttotheRCLKpulse
maybeginstartingwiththefirstlocationinmemory.SinceIDTStandardmode thatinitiatedtheretransmit.
18
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
Asynchronousoperationofthereadportwillbeselected.DuringAsynchronous
operation of the read port the RCLK input becomes RD input, this is the
Asynchronousreadstrobeinput.ArisingedgeonRDwillreaddatafromthe
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operationofthe readport).
SIGNALDESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
Datainputsfor18-bitwidedata(D0-D17)ordatainputsfor9-bitwidedata
(D0-D8).
The OE input provides three-state control of the Qn output bus, in an
asynchronousmanner.
WhenthereadportisconfiguredforAsynchronousoperationthedevice
mustbeoperatingonIDTstandardmode,FWFTmodeisnotpermissibleifthe
readportisAsynchronous.TheEmptyFlag(EF)operatesinanAsynchronous
manner,thatis,theemptyflagwillbeupdatedbasedonbothareadoperation
andawriteoperation.Refertofigures25,26,27and28forrelevanttimingand
operationalwaveforms.
CONTROLS:
MASTER RESET (MRS)
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray.PAEwillgoLOW,PAFwillgoHIGH,andHF willgoHIGH.
IfFWFT/SIisLOWduringMasterResetthentheIDTStandardmode,along
withEF andFF are selected. EFwillgoLOWandFF willgoHIGH. IfFWFT/
SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwithIRand
OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,BE,RM,PFMandIParedefinedduring
theMasterResetcycle.
RETRANSMIT (RT)
The Retransmit operation allows data that has already been read to be
accessedagain.Thereare2modesofRetransmitoperation,normallatency
andzerolatency.TherearetwostagestoRetransmit:first,asetupprocedure
that resets the read pointer to the first location of memory, then the actual
retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
beginningofthememory.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
REN and WEN must be HIGH before bringing RT LOW. Whenzerolatency
is utilized, REN does not need to be HIGH before bringing RT LOW.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
RetransmitsetupbysettingEFLOW.Thechangeinlevelwillonlybenoticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initializedtothefirstlocationoftheRAMarray.
See Figure 5, Master Reset Timing, forthe relevanttimingdiagram.
PARTIAL RESET (PRS)
APartialResetisaccomplishedwheneverthePRSinputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW,PAFgoesHIGH,
and HF goes HIGH.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
maybeginstartingwiththefirstlocationinmemory.SinceIDTStandardmode
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setupbysettingORHIGH.Duringthisperiod,theinternalreadpointerisset
tothefirstlocationoftheRAMarray.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode
orFirstWordFallThrough,thatmodewillremainselected.IftheIDTStandard
modeisactive,thenFFwillgoHIGHandEFwillgoLOW.IftheFirstWordFall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged.Theprogrammingmethod(parallelorserial)currentlyactiveat
thetimeofPartialResetisalsoretained.Theoutputregisterisinitializedtoall
zeroes.PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
See Figure 6, PartialResetTiming, forthe relevanttimingdiagram.
ASYNCHRONOUS WRITE (ASYW)
In Retransmit operation, zero-latency mode can be selected using the
RetransmitMode(RM)pinduringaMasterReset.Thiscanbeappliedtoboth
IDT Standard mode and FWFT mode.
ThewriteportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronousoperationofthewriteportwillbeselected.DuringAsynchro-
nousoperationofthewriteporttheWCLKinputbecomesWRinput,thisisthe
Asynchronouswritestrobeinput.ArisingedgeonWRwillwritedatapresent
ontheDninputsintotheFIFO.(WENmustbetiedLOWwhenusingthewrite
portinAsynchronous mode).
WhenthewriteportisconfiguredforAsynchronousoperationthefullflag
(FF)operatesinanasynchronousmanner,thatis,thefullflagwillbeupdated
based in both a write operation and read operation. Note, if Asynchronous
modeis selected,FWFTis notpermissable.RefertoFigures 23,24,27and
28forrelevanttimingandoperationalwaveforms.
RETRANSMIT LATENCY MODE (RM)
Azero-latencyretransmittimingmodecanbeselectedusingtheRetransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero-
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero-latency retransmit operation is selected the first data word to be
retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK
edgethatinitiatedtheretransmitbasedonRTbeingLOW.
RefertoFigure13forRetransmitTimingwithzerolatency(IDTStandard
Mode). Refer to Figure 14 for Retransmit Timing with zero latency (FWFT
Mode).
ASYNCHRONOUS READ (ASYR)
ThereadportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
19
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAE
This is a dualpurpose pin. DuringMasterReset, the state ofthe FWFT/ andHFflagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor the HF flag to HIGH). The Write and Read Clocks can be independent or
First Word Fall Through (FWFT) mode.
coincident.
If Asynchronous operation has been selected this input is RD (Read
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornot Strobe) . Data is Asynchronously read from the FIFO via the output register
there are any words present in the FIFO memory. It also uses the Full Flag whenever there is a rising edge on RD. In this mode the REN input must be
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace tiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthethree-
forwriting. InIDTStandardmode, everywordreadfromthe FIFO, including stateQnoutputs.
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe READ ENABLE (REN)
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate register on the rising edge of every RCLK cycle if the device is not empty.
whetherornottheFIFOmemoryhasanyfreespaceforwriting.IntheFWFT
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK and no new data is loaded into the output register. The data outputs Q0-Qn
rising edges, REN = LOW is not necessary. Subsequent words must be maintainthepreviousdatavalue.
accessed using the Read Enable (REN) and RCLK.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF wordwrittentoanemptyFIFO,mustberequestedusingREN.Whenthelast
offsetsintotheprogrammableregisters.Theserialinputfunctioncanonlybe wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset. furtherreadoperations.RENisignoredwhentheFIFOisempty.Onceawrite
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT isperformed,EFwillgoHIGHallowingareadtooccur.TheEFflagisupdated
StandardandFWFTmodes.
by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOWtoHIGHtransitionofRCLK+tSKEW
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this afterthefirstwrite.RENdoesnotneedtobeassertedLOW.Inordertoaccess
inputbehavesasWCLK. allotherwords,areadmustbeexecutedusingREN.TheRCLKLOWtoHIGH
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup transitionafterthelastwordhasbeenreadfromtheFIFO,OutputReady(OR)
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe willgoHIGHwithatrueread(RCLKwithREN=LOW),inhibitingfurtherread
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ operations. REN is ignored when the FIFO is empty.
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof
IfAsynchronousoperationoftheReadporthasbeenselected,thenREN
updating HF flag to LOW). The Write and Read Clocks can either be mustbeheldactive,(tiedLOW).
independentorcoincident.
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). SERIAL ENABLE (SEN)
DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere
is arisingedgeonWR.Inthis modetheWENinputmustbetiedLOW.
TheSENinputisanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset.SENisalwaysusedinconjunctionwithLD.Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
WRITE ENABLE (WEN)
WhentheWENinputisLOW,datamaybeloadedintotheFIFORAMarray LOW-to-HIGHtransitionofWCLK.
ontherisingedgeofeveryWCLKcycleifthedeviceis notfull.Datais stored
in the RAM array sequentially and independently of any ongoing read settings andnooffsets are loaded. SEN functions the same wayinbothIDT
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLKcycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW, OUTPUTENABLE(OE)
inhibitingfurtherwriteoperations.Uponthecompletionofavalidreadcycle,FF
willgoHIGHallowingawritetooccur.TheFFisupdatedbytwoWCLKcycles datafromtheoutputregister.WhenOEisHIGH,theoutputdatabus(Qn)goes
+tSKEW afterthe RCLKcycle.
When SEN is HIGH, the programmable registers retains the previous
StandardandFWFTmodes.
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
intoahighimpedancestate.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
furtherwriteoperations.Uponthecompletionofavalidreadcycle,IRwillgo LOAD (LD)
LOWallowinga write tooccur. The IR flagis updatedbytwoWCLKcycles +
tSKEW afterthe validRCLKcycle.
Thisisadualpurposepin.DuringMasterReset,thestateoftheLDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode. thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
IfAsynchronousoperationoftheReadporthasbeenselected,thenWEN canbe programmed, parallelorserial(see Table 2). AfterMasterReset, LD
mustbeheldactive,(tiedLOW).
enableswriteoperationstoandreadoperationsfromtheoffsetregisters.Only
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offsetregisters canbereadonlyinparallel.
READ STROBE & READ CLOCK (RD/RCLK)
IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput. orparallelloadorreadofthese offsetvalues.
20
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
BUS-MATCHING (IW, OW)
afterareset(eitherMRS orPRS), FF willgoLOWafterDwrites totheFIFO.
The pins IWandOWare usedtodefine the inputandoutputbus widths. Ifx18Inputorx18OutputbusWidthisselected,D=131,072fortheIDT72V2103
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus and262,144forthe IDT72V2113. Ifbothx9Inputandx9Outputbus Widths
sizes.SeeTable1forcontrolsettings.Allflagswilloperatebasedontheword/ areselected,D = 262,144fortheIDT72V2103and524,288fortheIDT72V2113.
bytesizeboundaryasdefinedbytheselectionofthewidestinputoroutputbus SeeFigure7,WriteCycleandFullFlagTiming(IDTStandardMode),forthe
width.
relevanttiminginformation.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
whenmemoryspace is available forwritingindata. Whenthere is nolonger
BIG-ENDIAN/LITTLE-ENDIAN (BE)
During Master Reset, a LOW on BE will select Big-Endian operation. A anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations.Ifnoreads
HIGHonBEduringMasterResetwillselectLittle-Endianformat.Thisfunction areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writes
isusefulwhendataiswrittenintotheFIFOinwordformat(x18)andreadout totheFIFO.Ifx18Inputorx18OutputbusWidthisselected,D = 131,073for
of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9
selected,thenthemostsignificantbyteofthewordwrittenintotheFIFOwillbe OutputbusWidthsareselected,D=262,145fortheIDT72V2103and524,289
readoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian fortheIDT72V2113.SeeFigure9,WriteTiming(FWFTMode),fortherelevant
formatisselected,thentheleastsignificantbyteofthewordwrittenintotheFIFO timinginformation.
willbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.Refer countsthepresenceofawordintheoutputregister.Thus,inFWFTmode,the
toFigure4,Bus-MatchingByteArrangement,foradiagramshowingthebyte totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
arrangement.
assert FF in IDT Standard mode.
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare
doubleregister-bufferedoutputs.
PROGRAMMABLEFLAGMODE(PFM)
During Master Reset During Master Reset, a LOW on PFM will select
Asynchronous Programmable flag timing mode. A HIGH on PFM will select EMPTYFLAG(EF/OR)
Synchronous Programmable flag timing mode. If asynchronous PAF/PAE
Thisisadualpurposepin.IntheIDTStandardmode,theEmptyFlag(EF)
configurationisselected(PFM,LOWduringMRS),thePAEisassertedLOW functionisselected.WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
ontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-to- readoperations.WhenEFisHIGH,theFIFOisnotempty.SeeFigure8,Read
HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-to- Cycle, EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for
HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH therelevanttiminginformation.
transitionofRCLK.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
If synchronous PAE/PAF configuration is selected (PFM, HIGH during atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand theoutputs.ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK lastwordfromtheFIFOmemorytotheoutputs.ORgoesHIGHonlywithatrue
onlyandnotRCLK.Themodedesiredisconfiguredduringmasterresetbythe read(RCLKwithREN=LOW).Thepreviousdatastaysattheoutputs,indicating
stateoftheProgrammableFlagMode(PFM)pin.
the last word was read. Further data reads are inhibited untilOR goes LOW
again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
INTERSPERSED PARITY (IP)
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.
AHIGHwillselectInterspersedParitymode.TheIPbitfunctionallowstheuser
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode, EFis a double register-bufferedoutput. InFWFT
to select the parity bit in the word loaded into the parallel port (D0-Dn) when mode,ORisatripleregister-bufferedoutput.
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitislocatedinbitpositionD8andD17during PROGRAMMABLE ALMOST-FULL FLAG (PAF)
theparallelprogrammingoftheflagoffsets,andwillthereforeignoreD8when
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
loadingthe offsetregisterinparallelmode. This is alsoappliedtothe output reaches the almost-full condition. In IDT Standard mode, if no reads are
registerwhenreadingthevalueoftheoffsetregister.IfInterspersedParityis performedafterreset(MRS),PAFwillgoLOWafter(D-m)wordsarewritten
selected then output Q8 will be invalid. If Non-Interspersed Parity mode is totheFIFO.Ifx18Inputorx18OutputbusWidthisselected,(D-m) = (131,072-m)
selected,thenD16andD17aretheparitybitsandareignoredduringparallel writesfortheIDT72V2103and(262,144-m)writesfortheIDT72V2113.Ifboth
programmingoftheoffsets.(D8becomesavalidbit).Additionally,outputQ8will x9Inputandx9OutputbusWidthsareselected,(D-m)=(262,144-m)writes
become a valid bit when performing a read of the offset register. IP mode is fortheIDT72V2103and(524,288-m)writes fortheIDT72V2113.Theoffset
selectedduringMasterResetbythestateoftheIPinputpin. InterspersedParity “m”isthefulloffsetvalue.ThedefaultsettingforthisvalueisstatedinTable2.
controlonlyhasaneffectduringparallelprogrammingoftheoffsetregisters.It
doesnoteffectthedatawrittentoandreadfromtheFIFO.
InFWFTmode,ifx18Inputorx18Outputbus Widthis selected,thePAF
will go LOW after (131,073-m) writes for the IDT72V2103 and (262,145-m)
writes for the IDT72V2113. If both x9 Input and x9 Output bus Widths are
selected,thePAFwillgoLOWafter(262,145-m)writesfortheIDT72V2103and
(524,289-m)writesfortheIDT72V2113.Theoffsetmisthefulloffsetvalue.The
defaultsettingforthisvalueisstatedinTable2.
OUTPUTS:
FULL FLAG (FF/IR)
Thisisadualpurposepin.InIDTStandardmode,theFullFlag(FF)function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFF is HIGH, the FIFOis notfull. Ifnoreads are performed
SeeFigure18,SynchronousProgrammableAlmost-FullFlagTiming(IDT
StandardandFWFTMode),fortherelevanttiminginformation.
21
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW HALF-FULL FLAG (HF)
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).PAFisresettoHIGH
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).IfsynchronousPAF beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
configurationisselected,thePAFisupdatedontherisingedgeofWCLK.See thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
Figure 20 for Asynchronous Programmable Almost-Full Flag Timing (IDT ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
Standard and FWFT Mode).
HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO bus Widthis selected,D = 131,072fortheIDT72V2103and262,144forthe
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D =
whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
value.Thedefaultsettingforthis valueis statedinTable2.
In FWFT mode, the PAE will go LOW when there are n+1 words or less willgoLOWafter(D-1/2 + 2)writestotheFIFO.Ifx18Inputorx18Outputbus
intheFIFO.Thedefaultsettingforthis valueis statedinTable2. Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the
See Figure 19, Synchronous ProgrammableAlmost-EmptyFlagTiming IDT72V2113. If both x9 Input and x9 Output bus Widths are selected,
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
(IDTStandardandFWFTMode), forthe relevanttiminginformation.
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW
D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Mode),
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).PAEisresettoHIGH fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).IfsynchronousPAE WCLK,itisconsideredasynchronous.
configurationisselected,thePAEisupdatedontherisingedgeofRCLK.See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT DATAOUTPUTS(Q0-Qn)
StandardandFWFTMode),fortherelevanttiminginformation.
(Q0 -Q17)dataoutputsfor18-bitwidedataor(Q0-Q8)dataoutputsfor9-
bitwidedata.
22
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
B
A
Write to FIFO
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE
IW
L
OW
L
A
B
Read from FIFO
L
(a) x18 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
L
B
A
Read from FIFO
H
(b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN
Q8-Q0
Q17-Q9
Q17-Q9
BE
IW
L
OW
H
A
1st: Read from FIFO
2nd: Read from FIFO
L
Q8-Q0
B
(c) x18 INPUT to x9 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
H
B
1st: Read from FIFO
H
Q17-Q9
Q8-Q0
A
2nd: Read from FIFO
(d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
A
1st: Write to FIFO
2nd: Write to FIFO
D17-Q9
D8-Q0
B
BYTE ORDER ON OUTPUT PORT:
Q17-Q9
Q8-Q0
BE
IW OW
A
B
Read from FIFO
L
H
L
(a) x9 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
H
OW
L
A
B
Read from FIFO
H
(a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN
6119 drw07
Figure 4. Bus-Matching Byte Arrangement
23
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
MRS
REN
t
RSR
RSR
tRSS
t
tRSS
WEN
tRSR
tRSS
FWFT/SI
tRSR
tRSS
tRSS
tRSS
LD
ASYW,
ASYR
FSEL0,
FSEL1
tRSS
tRSS
tRSS
tRSS
OW, IW
BE
RM
PFM
tRSS
IP
RT
tRSS
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
t
RSF
FF/IR
PAE
tRSF
tRSF
PAF, HF
tRSF
OE = HIGH
OE = LOW
Q0 - Qn
6119 drw08
Figure 5. Master Reset Timing
24
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
tRSF
FF/IR
PAE
tRSF
tRSF
PAF, HF
tRSF
OE = HIGH
OE = LOW
Q0 - Qn
6119 drw09
Figure 6. Partial Reset Timing
25
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
NO WRITE
NO WRITE
2
1
WCLK
1
2
t
SKEW1(1)
tDS
t
DH
t
SKEW1(1)
t
DH
tDS
DX
DX+1
WFF
D0 - Dn
t
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
tENH
tENH
REN
tA
tA
Q0
- Qn
NEXT DATA READ
6119 drw10
DATA IN OUTPUT REGISTER
DATA READ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising edge
of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENS
tENS
tENH
tENS
tENH
t
ENH
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
tOLZ
tOHZ
tOE
OE
t
SKEW1(1)
WCLK
tENH
tENH
tENS
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
6119 drw11
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency: tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
26
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
27
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
28
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
1
2
RCLK
tENS
tENH
tENS
tENH
tRTS
REN
tA
tA
tA
1(3)
W
2(3)
Q0 - Qn
Wx
Wx+1
W
tSKEW2
1
2
WCLK
WEN
RT
t
RTS
t
ENS
t
ENH
tREF
t
REF
EF
PAE
HF
tPAES
tHF
tPAFS
PAF
6119 drw14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113.
If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
5. There must be at least two words written to and two words read from the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
29
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
3
1
2
4
RCLK
tENH
tENH
tENS
tENS
tRTS
REN
- Q
tA
tA
tA
tA
W (4)
1
W
2(4)
W
3(4)
Q0
n
Wx+1
Wx
W4
tSKEW2
1
2
WCLK
tRTS
WEN
tENS
tENH
RT
OR
tREF
tREF
tPAES
PAE
tHF
HF
tPAFS
PAF
6119 drw15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113.
If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 12. Retransmit Timing (FWFT Mode)
30
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
2
3
1
RCLK
tENH
tENS
REN
tA
tA
tA
tA
tA
(3)
(3)
(3)
Q0 - Qn
Wx
W4
W2
W3
Wx+1
W1
tSKEW2
1
2
WCLK
tRTS
WEN
tENH
tENS
RT
EF(1)
PAE
tPAES
tHF
HF
tPAFS
PAF
6119 drw16
NOTES:
1. If the part is empty at the point of Retransmit, the Empty Flag (EF) will be updated based on RCLK (Retransmit clock cycle). Valid data will also appear on the output.
2. OE = LOW: enables data to be read on outputs Q0-Qn.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113.
If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
5. There must be at least two words written to and read from the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
31
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
4
1
2
5
3
RCLK
tENH
tENS
REN
tA
tA
tA
tA
tA
W
3(3)
2 (3)
W
4(3)
W5
Q0 - Qn
Wx
Wx+1
W1
W
tSKEW2
1
2
WCLK
tRTS
WEN
tENS
tENH
RT
OR
tPAES
PAE
tHF
HF
PAF
tPAFS
6119 drw17
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR), will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113.
If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
WCLK
tENH
tENS
tENH
SEN
t
LDH
tLDS
t
LDH
LD
SI
t
DS
t
DH
BIT X(1)
BIT 0
BIT X(1)
BIT 0
6119 drw18
FULL OFFSET
EMPTY OFFSET
NOTES:
1. x9 to x9 mode: X = 17 for the IDT72V2103 and X = 18 for the IDT72V2113.
2. All other modes: X = 16 for the IDT72V2103 and X = 17 for the IDT72V2113.
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
32
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
WCLK
LD
tLDS
t
LDH
tLDH
t
ENS
tENH
t
ENH
DH
WEN
tDS
tDS
tDS
tDS
t
t
DH
t
DH
tDH
D0
- D16
6119 drw19
PAE OFFSET (LSB)
PAE OFFSET (MSB)
PAF OFFSET (LSB)
PAF OFFSET (MSB)
NOTE:
1. This diagram is based on programming the IDT72V2103/72V2113 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width.
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tLDS
t
LDH
tLDH
LD
tENS
tENH
tENH
REN
tA
tA
tA
tA
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
DATA IN OUTPUT
REGISTER
Q0
- Q16
6119 drw20
NOTES:
1. OE = LOW.
2. This diagram is based on programming the IDT72V2103/72V2113 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
WEN
PAF
1
2
2
1
tENS
tENH
tPAFS
tPAFS
2)
D-(m+1) words in FIFO(
D - m words in FIFO(2)
D-(m+1) words
2)
in FIFO(
t
SKEW2(3)
RCLK
tENH
tENS
6119 drw21
REN
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths
are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths
are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
33
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
n+1 words in FIFO(3)
SKEW2(4)
tPAES
t
tPAES
1
2
1
2
RCLK
tENH
tENS
6119 drw22
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKL
tCLKH
WCLK
tENS
tENH
WEN
PAF
tPAFA
D m words
D (m + 1)
words in FIFO
D (m + 1) words in FIFO
in FIFO
tPAFA
RCLK
tENS
REN
6119 drw23
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths
are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the DT72V2113. If both x9 Input and x9 Output bus Widths are
selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
34
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
(2)
(2)
n words in FIFO
,
n words in FIFO
,
(2)
n+1wordsinFIFO
,
(3)
(3)
PAE
RCLK
REN
n + 1 words in FIFO
n + 1 words in FIFO
(3)
n+2wordsinFIFO
tPAEA
tENS
6119 drw24
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
D
2
D + 1
2
tHF
[
+ 1
]
words in FIFO(1)
+ 1 words in FIFO(2)
,
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
[
]
D + 1
2
D + 1
2
[
]
words in FIFO(2)
[
]
words in FIFO(2)
tHF
RCLK
tENS
REN
6119 drw25
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9
Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
2. In FWFT mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input
and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
35
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
RCLK
tENS
tENH
REN
Qn
tA
W0
W1
tFFA
FF
tFFA
tFFA
tCYC
WR
tCYH
tDS
tDH
Dn
WD
WD+1
6119 drw26
NOTE:
1. OE = LOW and WEN = LOW.
Figure 23. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
1
2
RCLK
tENS
tENH
tA
REN
tA
Last Word
W1
W0
Qn
tREF
tREF
EF
tCYL
tSKEW
tCYH
WR
tCYC
tDH
tDH
tDS
tDS
W0
W1
Dn
6119 drw27
NOTE:
1. OE = LOW and WEN = LOW.
Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
36
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
No Write
1
WCLK
WEN
Dn
2
DF+1
DF
tWFF
tWFF
FF
tCYC
tSKEW
tCYL
tCYH
RD
Qn
tAA
t
AA
Last Word
WX
WX+1
6119 drw28
NOTES:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 25. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
WCLK
WEN
Dn
t
ENS
t
ENH
t
DS
t
DH
W0
tEFA
EF
tEFA
tRPE
RD
Qn
t
CYH
t
AA
Last Word in Output Register
W0
6119 drw29
NOTES:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 26. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
37
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
W0
W1
RD
Qn
tAA
tAA
W
1
W
0
Last Word in O/P Register
tRPE
tEFA
tEFA
EF
6119 drw30
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 27. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
tCYC
tCYH
tCYL
WR
Dn
tDH
t
DH
tDS
tDS
W
y+1
Wy
tCYC
tCYH
tCYL
RD
Qn
tAA
tAA
Wx
Wx+1
Wx+2
tFFA
tFFA
FF
6119 drw31
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
38
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
compositeflags canbecreatedbyORingOR ofeveryFIFO,andseparately
ORing IR of every FIFO.
Figure 29 demonstrates a width expansion using two IDT72V2103/
72V2113devices.Ifx18Inputorx18OutputbusWidthisselected,D0-D17from
eachdevice forma 36-bitwide inputbus andQ0-Q17 fromeachdevice form
a36-bitwideoutputbus.Ifbothx9Inputandx9OutputbusWidthsareselected,
D0-D8 from each device form an 18-bit wide input bus and Q0-Q8 fromeach
deviceforman18-bitwideoutputbus.Anywordwidthcanbeattainedbyadding
additionalIDT72V2103/72V2113devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertiontovarybyone cycle betweenFIFOs. InIDTStandardmode, such
problems can be avoided by creating composite flags, that is, ANDing EF
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m
D0 - Dm
m + n
n
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
IDT
72V2103
72V2113
IDT
72V2103
72V2113
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
FULL FLAG/INPUT READY (FF/IR) #1
FULL FLAG/INPUT READY (FF/IR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
(1
(1
)
GATE
)
GATE
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
DATA
OUT
m
FIFO
#1
FIFO
#2
6119 drw32
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 29. Block Diagram of Width Expansion
For the x18 Input or x18 Output bus Width: 131,072 x 36 and 262,144 x 36
For both x9 Input and x9 Output bus Widths: 262,144 x 18 and 524,288 x 18
39
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
READ ENABLE
WRITE CLOCK
WCLK
WEN
IR
RCLK
WCLK
RCLK
WRITE ENABLE
INPUT READY
OR
WEN
REN
IDT
72V2103
72V2113
IDT
72V2103
72V2113
OUTPUT READY
OUTPUT ENABLE
REN
OR
OE
Qn
IR
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
6119 drw33
Figure 30. Block Diagram of Depth Expansion
For the x18 Input or x18 Output bus Width: 262,144 x 18 and 524,288 x 18
For both x9 Input and x9 Output bus Widths: 524,288 x 9 and 1,048,576 x 9
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
The IDT72V2103 can easily be adapted to applications requiring depths clock,fortheORflag.
greaterthan131,072whenthex18Inputorx18OutputbusWidthisselected
The "ripple down" delay is only noticeable for the first word written to an
and262,144fortheIDT72V2113.Whenbothx9Inputandx9OutputbusWidths empty depth expansion configuration. There will be no delay evident for
areselected,depthsgreaterthan262,144canbeadaptedfortheIDT72V2103 subsequent words written to the configuration.
and524,288fortheIDT72V2113.InFWFTmode,theFIFOscanbeconnected
The first free location created by reading from a full depth expansion
inseries(thedataoutputsofoneFIFOconnectedtothedatainputsofthenext) configuration will "bubble up" from the last FIFO to the previous one until it
withnoexternallogicnecessary.Theresultingconfigurationprovidesatotal finally moves into the first FIFO of the chain. Each time a free location is
depthequivalenttothesumofthedepths associatedwitheachsingleFIFO. createdinoneFIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingthe
Figure30showsadepthexpansionusingtwoIDT72V2103/72V2113devices. preceding FIFO to write a word to fill it.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
in the depth expansion configuration. The first word written to an empty FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFOis
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally the sumofthe delays foreachindividualFIFO:
appears at the outputs of the last FIFO in the chain–no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running.Eachtimethedata
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof period.NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays clock,fortheIRflag.
for each individual FIFO:
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster.Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW1
40
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
tTCK
tJTCKR
tJTCKF
tJTCKL
tJTCKH
TCK
TDI/
TMS
tDH
tDS
TDO
TDO
tDO
tJRSR
6119 drw34
TRST(1)
tJRST
NOTE:
1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
Figure 31. Standard JTAG Timing
JTAGACELECTRICAL
CHARACTERISTICS
(VCC = 3.3V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions Min. Max. Units
SYSTEMINTERFACEPARAMETERS
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
IDT72V2103
IDT72V2113
JTAGClockHIGH
JTAGClockLow
tJTCKH
tJTCKL
tJTCKR
tJTCKF
tJRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tJRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
41
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V2103/72V2113
incorporatesthenecessarytapcontrollerandmodifiedpadcellstoimplement
theJTAG facility.
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
•
•
•
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The Figure belowshows the standardBoundary-ScanArchitecture
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
6119 drw35
Figure 32. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
42
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-IR
Shift-DR
1
1
1
1
Input = TMS
Exit1-IR
Exit1-DR
0
0
0
0
Pause-IR
Pause-DR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-IR
Update-DR
1
0
1
0
6119 drw36
NOTE:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
Figure 33. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram.
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overthe Queue andmustbe resetafterpowerupofthe device. See TRST
descriptionformoredetailsonTAPcontrollerreset.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IR This state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCKfive
times. This is the reasonwhythe TestReset(TRST)pinis optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-Scan This is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
43
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
THE INSTRUCTION REGISTER
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
•
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions. Instructionsaredecodedasfollows.
Hex
Value
Instruction
Function
TESTDATAREGISTER
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
0x00
0x02
0x01
0x03
0x0F
EXTEST
IDCODE
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
SAMPLE/PRELOAD SelectBoundaryScanRegister
HIGH-IMPEDANCE JTAG
BYPASS
SelectBypassRegister
Table 6. JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
EXTEST
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO. Duringthis instruction, theboundary-scanregisteris accessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
IDCODE
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe
TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
THE DEVICE IDENTIFICATION REGISTER
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
FortheIDT72V2103/72V2113,thePartNumberfieldcontainsthefollowing
values:
Device
IDT72V2103
IDT72V2113
Part# Field
042E
042F
SAMPLE/PRELOAD
TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto
theboundary-scanregisterbeforeloadinganEXTESTinstruction.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
IDT72V2103/72V2113 JTAG Device Identification Register
44
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
HIGH-IMPEDANCE
BYPASS
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
45
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BC
Thin Plastic Quad Flatpack (TQFP, PN80-1)
Ball Grid Array (BGA, BC100-1)
Commercial, BGA & TQFP Only
6
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Commercial, BGA & TQFP Only
Com'l & Ind'l, TQFP Only
Commercial, TQFP Only
7-5
10
15
L
Low Power
131,072 x 18/262,144 x 9 3.3V SuperSync IITM FIFO
262,144 x 18/524,288 x 9 3.3V SuperSync IITM FIFO
72V2103
72V2113
6119 drw37
NOTE:
1. Industrial temperature range product for the 10ns is available as a standard device. All other speed grades are available by special order.
DATASHEETDOCUMENTHISTORY
12/18/2000
03/27/2001
04/06/2001
12/14/2001
12/16/2002
02/11/2003
06/26/2003
07/15/2003
07/21/2003
09/29/2003
pgs. 7, 8, 9, and 37.
pgs. 9 and 37.
pgs. 4, 5, and 21.
pgs. 1-35.
pgs. 1-11, 19, 20, 24, and 36-45.
pgs. 7 and 43.
pgs. 1, 3, 9, 10, and 45.
pgs. 3, 19, and 36-38.
pgs. 7, 41,and 43-45.
pg. 8.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1753
email: FIFOhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
46
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