IDT72V251L20PFI [IDT]

3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9; 3.3伏的CMOS SyncFIFO⑩ 256 ×9 ， 512× 9 ， 1,024× 9 ， 2048 ×9 ， 4096 ×9和8,192 ×9


型号：	IDT72V251L20PFI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	3.3 VOLT CMOS SyncFIFO⑩ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 3.3伏的CMOS SyncFIFO⑩ 256 ×9 ， 512× 9 ， 1,024× 9 ， 2048 ×9 ， 4096 ×9和8,192 ×9 先进先出芯片
文件：	总14页 (文件大小：117K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

3.3 VOLT CMOS SyncFIFO™

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

IDT72V201, IDT72V211

IDT72V221, IDT72V231

IDT72V241, IDT72V251

4,096 x 9 and 8,192 x 9

FEATURES:

clockedreadandwritecontrols.Thearchitecture,functionaloperationandpin

assignments are identical to those of the IDT72201/72211/72221/72231/

72241/72251,butoperateatapowersupplyvoltage(Vcc)between3.0Vand

3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit

memoryarray,respectively.TheseFIFOsareapplicableforawidevarietyof

databufferingneedssuchasgraphics,localareanetworksandinterprocessor

communication.

These FIFOs have 9-bit input and output ports. The input port is

controlled by a free-running clock (WCLK), and two Write Enable pins

(WEN1,WEN2). DataiswrittenintotheSynchronousFIFOoneveryrising

clock edge when the Write Enable pins are asserted. The output port is

controlledbyanotherclockpin(RCLK)andtwoReadEnable pins (REN1,

• 256 x 9-bit organization IDT72V201

• 512 x 9-bit organization IDT72V211

• 1,024 x 9-bit organization IDT72V221

• 2,048 x 9-bit organization IDT72V231

• 4,096 x 9-bit organization IDT72V241

• 8,192 x 9-bit organization IDT72V251

• 10 ns read/write cycle time

• 5V input tolerant

• Read and Write clocks can be independent

• Dual-Ported zero fall-through time architecture

• Empty and Full Flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags can be set to REN2). The Read Clock can be tied to the Write Clock for single clock

any depth

operationorthe twoclocks canrunasynchronous ofone anotherfordual-

clockoperation. AnOutputEnable pin(OE)is providedonthe readport

forthree-state controlofthe output.

• Programmable Almost-Empty and Almost-Full flags default to

Empty+7, and Full-7, respectively

• Output Enable puts output data bus in high-impedance state

• Advanced submicron CMOS technology

• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin

plastic Thin Quad FlatPack (TQFP)

The Synchronous FIFOs have twofixedflags, Empty(EF)andFull(FF).

Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are

provided for improved system control. The programmable flags default to

Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag

offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting

the Load pin (LD).

• Industrial temperature range (–40°C to +85°C) is available

These FIFOs are fabricated using IDT's high-speed submicron CMOS

technology.

DESCRIPTION:

TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™

are very high-speed, low-power First-In, First-Out (FIFO) memories with

FUNCTIONAL BLOCK DIAGRAM

D0 - D8

WCLK

WEN1

WEN2

INPUT REGISTER

OFFSET REGISTER

FLAG

LOGIC

PAE

PAF

WRITE CONTROL

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9, 8,192 x 9

READ POINTER

WRITE POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

4092 drw 01

Q0 - Q8

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEBRUARY 2002

DSC-4092/2

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PIN CONFIGURATION

INDEX

29 28 27 26 25

32 31 30

WEN1

WCLK

WEN2/LD

WCLK

WEN2/LD

V_CC

PAF

PAE

PAF

PAE

GND

REN1

RCLK

REN2

VCC

GND

REN1

RCLK

REN2

10 11 12 13 14 15 16

14 15 16 17 18 19 20

4092 drw02

4092 drw02a

TQFP (PR32-1, order code: PF)

TOP VIEW

PLCC (J32-1, order code: J)

TOP VIEW

PINDESCRIPTIONS

Symbol

D0-D8

Name

DataInputs

Reset

I/O

Description

Datainputs fora9-bitbus.

WhenRS is setLOW, internalreadandwrite pointers are settothe firstlocationofthe RAMarray, FF

and PAF go HIGH, and PAE and EF go LOW. A Reset is required before an initial Write after power-up.

WCLK

WriteClock

DataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLKwhentheWriteEnable(s)areasserted.

WEN1

WriteEnable1

Ifthe FIFOis configuredtohave programmable flags, WEN1 is the onlyWrite Enable pin. WhenWEN1 is

LOW,dataiswrittenintotheFIFOoneveryLOW-to-HIGHtransitionWCLK.IftheFIFOisconfiguredto

have twowrite enables, WEN1 mustbe LOWandWEN2mustbe HIGHtowrite data intothe FIFO. Data

willnotbewrittenintotheFIFOifthe FF is LOW.

WEN2/LD

WriteEnable2/

Load

The FIFOis configuredatResettohave eithertwowrite enables orprogrammable flags. IfWEN2/LD

is HIGHatReset,this pinoperates as asecondwriteenable. IfWEN2/LD is LOWatReset,this pinoperates

as acontroltoloadandreadtheprogrammableflagoffsets.IftheFIFOis configuredtohavetwowrite

enables, WEN1 mustbe LOWandWEN2mustbe HIGHtowrite data intothe FIFO. Data willnotbe written

intothe FIFOiftheFF is LOW. IftheFIFOis configuredtohaveprogrammableflags,WEN2/LD is heldLOWto

writeorreadtheprogrammableflagoffsets.

Q0-Q8

RCLK

REN1

DataOutputs

ReadClock

Dataoutputsfora9-bitbus.

Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.

When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data

will not be read from the FIFO if the EF is LOW.

Read Enable 1

REN2

Read Enable 2

OutputEnable

EmptyFlag

When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.

Data will not be read from the FIFO if the EF is LOW.

WhenOE is LOW, the data outputbus is active. IfOE is HIGH, the outputdata bus willbe ina high-impedance

state.

WhenEF is LOW, the FIFOis emptyandfurtherdata reads fromthe outputare inhibited. When EF is

HIGH, the FIFO is not empty. EF is synchronized to RCLK.

WhenPAE isLOW,theFIFOisalmost-emptybasedontheoffsetprogrammedintotheFIFO.Thedefault

offsetatresetis Empty+7.PAE is synchronizedtoRCLK.

WhenPAF isLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefault

offsetatresetisFull-7.PAF issynchronizedtoWCLK.

WhenFF is LOW, the FIFOis fullandfurtherdata writes intothe inputare inhibited. When FF is HIGH, the FIFO

isnotfull.FF issynchronizedtoWCLK.

PAE

PAF

Programmable

Almost-EmptyFlag

Programmable

Almost-FullFlag

Full Flag

VCC

Power

One 3.3V volt power supply pin.

One 0 volt ground pin.

GND

Ground

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

RECOMMENDEDOPERATING

CONDITIONS

Symbol

V^TERM

Rating

TerminalVoltagewith

RespecttoGND

Com'l & Ind'l

–0.5 to +5

Unit

(2)

Symbol

Parameter

Min.

3.0

Typ. Max. Unit

V^CC

SupplyVoltage

3.3

3.6

Commercial/Industrial

SupplyVoltage

T^STG

I^OUT

StorageTemperature

DCOutputCurrent

–55 to+125

–50 to +50

°C

GND

V^IH

InputHighVoltage

Commercial/Industrial

InputLowVoltage

Commercial/Industrial

2.0

—

5.5

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of the specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

V^IL

T^A

-0.5

—

0.8

°C

OperatingTemperature

Commercial

2. VCC terminal only.

OperatingTemperature

Industrial

-40

DCELECTRICALCHARACTERISTICS

(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)

IDT72V201

IDT72V211

IDT72V221

IDT72V231

IDT72V241

IDT72V251

(1)

Commercial and Industrial

tCLK = 10, 15, 20 ns

Typ.

Symbol

Parameter

InputLeakageCurrent(AnyInput)

OutputLeakageCurrent

Min.

–1

Max.

Unit

µA

(2)

ILI

—

(3)

ILO

–10

2.4

—

0.4

VOH

VOL

Output Logic “1” Voltage, IOH = –2mA

Output Logic “0” Voltage, IOL = 8mA

Active Power Supply Current

StandbyCurrent

(4,5,6)

ICC1

—

(4,7)

ICC2

—

NOTES:

1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.

2. Measurements with 0.4 ≤ VIN ≤ VCC.

3. OE ≥ V^IH,0.4 ≤ VOUT ≤ VCC.

4. Tested with outputs disabled (I^OUT= 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. Typical ICC1 = 0.17 + 0.48*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,

C^L= capacitive load (in pF).

7. All Inputs = V^CC- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol

Parameter

Conditions

Max.

Unit

(2)

C^IN

InputCapacitance

VIN = 0V

(1,2)

C^OUT

OutputCapacitance

VOUT = 0V

NOTES:

1. With output deselected (OE ≥ VIH).

2. Characterized values, not currently tested.

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ACELECTRICALCHARACTERISTICS⁽¹⁾

(Commercial: VCC = 3.3 ±0.3V, TA = 0°C to + 70°C;Industrial: VCC = 3.3 ±0.3V, TA = -40°C to + 85°C)

Commercial

Com'l & Ind'l⁽²⁾

Commercial

IDT72V201L10

IDT72V211L10

IDT72V221L10

IDT72V231L10

IDT72V241L10

IDT72V251L10

IDT72V201L15

IDT72V211L15

IDT72V221L15

IDT72V231L15

IDT72V241L15

IDT72V251L15

IDT72V201L20

IDT72V211L20

IDT72V221L20

IDT72V231L20

IDT72V241L20

IDT72V251L20

Symbol

Parameter

Clock Cycle Frequency

Min.

Max.

Min.

Max.

Min.

Max.

Unit

f^S

—

100

—

66.7

—

MHz

t^A

DataAccessTime

Clock Cycle Time

Clock High Time

4.5

6.5

—

t^CLK

t^CLKH

t^CLKL

t^DS

Clock Low Time

DataSetupTime

t^DH

DataHoldTime

0.5

t^ENS

t^ENH

t^RS

EnableSetupTime

EnableHoldTime

ResetPulseWidth⁽¹⁾

ResetSetupTime

ResetRecoveryTime

ResettoFlagandOutputTime

0.5

—

t^RSS

t^RSR

t^RSF

t^OLZ

t^OE

—

(3)

OutputEnabletoOutputinLow-Z

OutputEnabletoOutputValid

—

6.5

—

(3)

t^OHZ

t^WFF

t^REF

t^AF

OutputEnabletoOutputinHigh-Z

Write ClocktoFullFlag

—

Read Clock to Empty Flag

WriteClocktoAlmost-FullFlag

Read Clock to Almost-Empty Flag

t^AE

t^SKEW1

Skew time between Read Clock & Write

Clock for Empty Flag &Full Flag

t^SKEW2

Skew time between Read Clock & Write

Clock for Almost-Empty Flag &

Almost-FullFlag

—

NOTES:

1. Pulse widths less than minimum values are not allowed.

2. Industrial temperature range is available by special order for speed grades faster than 15ns.

3. Values guaranteed by design, not currently tested.

3.3V

330Ω

D.U.T.

ACTESTCONDITIONS

30pF*

510Ω

In Pulse Levels

GND to 3.0V

3ns

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

OutputLoad

1.5V

4092 drw03

1.5V

or equivalent circuit

SeeFigure1

Figure 1. Output Load

*Includes jig and scope capacitances.

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

OUTPUTENABLE(OE)

SIGNALDESCRIPTIONS

When Output Enable (OE) is enabled (LOW), the parallel output buffers

receivedatafromtheoutputregister. WhenOutputEnable(OE)is disabled

(HIGH),theQoutputdatabusisinahigh-impedancestate.

INPUTS:

DATA IN (D0 - D8)

Datainputsfor9-bitwidedata.

WRITE ENABLE 2/LOAD (WEN2/LD)

This is a dual-purpose pin. The FIFO is configured at Reset to have

programmableflagsortohavetwowriteenables,whichallowsdepthexpansion.

IfWrite Enable 2/Load(WEN2/LD)is sethighatReset(RS =LOW), this pin

operates as asecondWriteEnablepin.

If the FIFO is configured to have two write enables, when Write Enable

(WEN1)is LOW andWrite Enable 2/Load(WEN2/LD)is HIGH, data canbe

loadedintotheinputregisterandRAMarrayontheLOW-to-HIGHtransition

ofeveryWriteClock(WCLK). DataisstoredintheRAMarraysequentiallyand

independently of any on-going read operation.

CONTROLS:

RESET (RS)

ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOWstate.

During reset, both internal read and write pointers are set to the first location.

Aresetis requiredafterpower-upbeforeawriteoperationcantakeplace. The

FullFlag(FF)andProgrammableAlmost-FullFlag(PAF)willberesettoHIGH

aftertRSF. TheEmptyFlag(EF)andProgrammableAlmost-EmptyFlag(PAE)

willbe resettoLOWaftertRSF. Duringreset, the outputregisteris initializedto

all zeros and the offset registers are initialized to their default values.

In this configuration, when Write Enable (WEN1) is HIGH and/or Write

Enable2/Load(WEN2/LD)isLOW,theinputregisterholdsthepreviousdata

and no new data is allowed to be loaded into the register.

WRITE CLOCK (WCLK)

Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther

writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)

willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)

and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.

TheFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable

2/Load(WEN2/LD)issetLOWatReset(RS =LOW). TheIDT72V201/72V211/

72V221/72V231/72V241/72V251devices containfour8-bitoffsetregisters

whichcanbeloadedwithdataontheinputs,orreadontheoutputs. SeeFigure

3fordetailsofthesizeoftheregistersandthedefaultvalues.

AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock

(WCLK). DatasetupandholdtimesmustbemetinrespecttotheLOW-to-HIGH

transitionoftheWriteClock(WCLK). TheFullFlag(FF)andProgrammable

Almost-Full Flag (PAF) are synchronized with respect to the LOW-to-HIGH

transitionoftheWriteClock(WCLK).

The Write andReadclocks canbe asynchronous orcoincident.

WRITE ENABLE 1 (WEN1)

IftheFIFOisconfiguredforprogrammableflags,WriteEnable1(WEN1)

istheonlyenablecontrolpin. Inthisconfiguration,whenWriteEnable1(WEN1)

islow,datacanbeloadedintotheinputregisterandRAMarrayontheLOW-

to-HIGHtransitionofeveryWriteClock(WCLK). DataisstoredintheRAMarray

sequentiallyandindependentlyofanyon-goingreadoperation.

Inthisconfiguration,whenWriteEnable1(WEN1)isHIGH,theinputregister

holdsthepreviousdataandnonewdataisallowedtobeloadedintotheregister.

IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth

expansion,therearetwoenablecontrolpins. SeeWriteEnable2paragraph

belowforoperationinthisconfiguration.

If theFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable

1(WEN1)andWriteEnable2/Load(WEN2/LD)aresetlow,dataontheinputs

DiswrittenintotheEmpty(LeastSignificantBit)OffsetregisteronthefirstLOW-

to-HIGHtransitionoftheWriteClock(WCLK). DataiswrittenintotheEmpty(Most

SignificantBit)OffsetregisteronthesecondLOW-to-HIGHtransitionoftheWrite

Clock(WCLK),intotheFull(LeastSignificantBit)Offsetregisteronthethird

transition,andintotheFull(MostSignificantBit)Offsetregisteronthefourth

transition. Thefifth transitionofthe WriteClock(WCLK)againwritestotheEmpty

(LeastSignificantBit)Offsetregister.

However,writingalloffsetregistersdoesnothavetooccuratonetime. One

ortwooffsetregisterscanbewrittenandthenbybringingtheWriteEnable2/

Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write

operation. WhentheWriteEnable2/Load(WEN2/LD)pinissetLOW,andWrite

Enable1(WEN1)isLOW,thenextoffsetregisterinsequenceiswritten.

Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhenthe

WriteEnable2/Load(WEN2/LD)pinissetlowandbothReadEnables(REN1,

REN2)aresetLOW. DatacanbereadontheLOW-to-HIGHtransitionofthe

Read Clock (RCLK).

Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther

writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)

willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)

is ignored when the FIFO is full.

READ CLOCK (RCLK)

DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead

Clock(RCLK).TheEmptyFlag(EF)andProgrammableAlmost-EmptyFlag

(PAE)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionoftheRead

Clock (RCLK).

A read and write should not be performed simultaneously to the offset

registers.

WEN1

WCLK

Selection

Empty Offset (LSB)

The Write andReadclocks canbe asynchronous orcoincident.

Empty Offset (MSB)

FullOffset(LSB)

Full Offset (MSB)

READ ENABLES (REN1, REN2)

WhenbothReadEnables(REN1,REN2)areLOW,dataisreadfromthe

RAMarraytotheoutputregisterontheLOW-to-HIGHtransitionoftheRead

Clock (RCLK).

WheneitherReadEnable(REN1,REN2)isHIGH,theoutputregisterholds

the previous data and no new data is allowed to be loaded into the register.

WhenallthedatahasbeenreadfromtheFIFO,theEmptyFlag(EF)willgo

LOW,inhibitingfurtherreadoperations.Onceavalidwriteoperationhasbeen

accomplished,theEmptyFlag(EF)willgoHIGHaftertREFandavalidreadcan

begin. TheReadEnables(REN1,REN2)areignoredwhentheFIFOisempty.

NoOperation

WriteIntoFIFO

NoOperation

NOTES:

1. For the purposes of this table, WEN2 = V^IH.

2. The same selection sequence applies to reading from the registers. REN1 and REN2

are enabled and read is performed on the LOW-to-HIGH transition of RCLK.

Figure 2. Write Offset Register

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72V221 - 1,024 x 9-BIT

IDT72V201 - 256 x 9-BIT

IDT72V211 - 512 x 9-BIT

Empty Offset (LSB) Reg.

Empty Offset (LSB)

Default Value 007H

Empty Offset (LSB) Reg.

Default Value 007H

(MSB)

Full Offset (LSB) Reg.

Full Offset (LSB)

Full Offset (LSB) Reg.

Default Value 007H

(MSB)

IDT72V231 - 2,049 x 9-BIT

IDT72V241 - 4,096 x 9-BIT

IDT72V251 - 8,192 x 9-BIT

Empty Offset (LSB)

Default Value 007H

Empty Offset (LSB)

Default Value 007H

Empty Offset (LSB) Reg.

Default Value 007H

(MSB)

00000

(MSB)

0000

000

Full Offset (LSB)

Full Offset (LSB) Reg.

Default Value 007H

(MSB)

0000

00000

000

4092 drw 05

Figure 3. Offset Register Location and Default Values

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72V221, (2,048-m) writes for the IDT72V231, (4,096-m) writes for the

IDT72V241and(8,192-m)writesfortheIDT72V251. Theoffset“m”isdefined

intheFullOffsetregisters.

Ifthereisnofulloffsetspecified,theProgrammableAlmost-Fullflag(PAF)

will go LOW at Full-7 words.

OUTPUTS:

FULL FLAG (FF)

TheFullFlag(FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe

device is full. If no reads are performed after Reset (RS), the Full Flag (FF)

willgoLOWafter256writesfortheIDT72V201,512writesfortheIDT72V211,

1,024writesfortheIDT72V221,2,048writesfortheIDT72V231,4,096writes

for the IDT72V241 and 8,192 writes for the IDT72V251.

The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH

transitionoftheWriteClock(WCLK).

TheProgrammableAlmost-Fullflag(PAF)issynchronizedwithrespectto

theLOW-to-HIGHtransitionoftheWriteClock(WCLK).

PROGRAMMABLEALMOST-EMPTYFLAG(PAE)

TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheread

pointeris"n+1"locationslessthanthewritepointer. Theoffset"n"isdefined

in the Empty Offset registers. If no reads are performed after Reset the

Programmable Almost-Empty flag (PAE) will go HIGH after "n+1" for the

IDT72V201/72V211/72V221/72V231/72V241/72V251.

Ifthereisnoemptyoffsetspecified,theProgrammableAlmost-Emptyflag

(PAE)willgoLOWatEmpty+7words.

EMPTY FLAG (EF)

TheEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations,when

thereadpointerisequaltothewritepointer,indicatingthedeviceisempty.

The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH

transitionoftheReadClock(RCLK).

TheProgrammableAlmost-Emptyflag(PAE)issynchronizedwithrespect

totheLOW-to-HIGHtransitionoftheReadClock(RCLK).

PROGRAMMABLE ALMOST-FULL FLAG (PAF)

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO

reachesthealmost-fullcondition.IfnoreadsareperformedafterReset(RS),

theProgrammableAlmost-Fullflag(PAF)willgoLOWafter (256-m)writesfor

the IDT72V201, (512-m) writes for the IDT72V211, (1,024-m) writes for the

DATA OUTPUTS (Q0 - Q8)

Dataoutputsfora9-bitwidedata.

TABLE 1 STATUS FLAGS

NUMBER OF WORDS IN FIFO

IDT72V201

IDT72V211

IDT72V221

PAF

PAE

1 to n⁽¹⁾

1ton⁽¹⁾

(n+1)to(256-(m+1))

(256-m)⁽²⁾to255

256

(n+1)to(512-(m+1))

(n+1)to(1,024-(m+1))

(2)

(512-m) to511

(1,024-m) to1,023

512

1,024

NUMBER OF WORDS IN FIFO

IDT72V231

IDT72V241

IDT72V251

PAF

PAE

1ton⁽¹⁾

(n+1)to(2,048-(m+1))

(n+1)to(4,096-(m+1))

(n+1)to(8,192-(m+1))

(2,048-m)⁽²⁾to2,047

(4,096-m)⁽²⁾to4,095

4,096

(8,192-m)⁽²⁾to8,191

8,192

2,048

NOTES:

1. n = Empty Offset (n = 7 default value)

2. m = Full Offset (m = 7 default value)

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tRS

tRSS

tRSR

REN1,

REN2

WEN1

WEN2/LD⁽¹⁾

EF, PAE

RSF

FF, PAF

RSF

OE = 1⁽²⁾

Q0 - Q8

4092 drw06

OE = 0

NOTES:

1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable

flag offset registers.

2. After reset, the outputs will be LOW if OE = 0 and high-impedance if OE = 1.

3. The clocks (RCLK, WCLK) can be free-running during reset.

Figure 4. Reset Timing

tCLK

tCLKH

tCLKL

WCLK

tDH

tDS

D0 - D8

DATA IN VALID

tENH

tENS

NO OPERATION

WEN1

tENH

tENS

WEN2/

(If Applicable)

WFF

tWFF

(1)

SKEW1

RCLK

REN1,

REN2

4092 drw07

NOTE:

1. t^SKEW1is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between

the rising edge of RCLK and the rising edge of WCLK is less than t^SKEW1, then FF may not change state until the next WCLK edge.

Figure 5. Write Cycle Timing

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLK

tCLKL

tCLKH

RCLK

tENS

tENH

REN1,

REN2

NO OPERATION

REF

VALID DATA

Q0 - Q8

tOLZ

tOHZ

tOE

(1)

tSKEW1

WCLK

WEN1

WEN2

4092 drw08

NOTE:

1. t^SKEW1is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between

the rising edge of RCLK and the rising edge of WCLK is less than t^SKEW1, then EF may not change state until the next RCLK edge.

Figure 6. Read Cycle Timing

WCLK

tDS

D0 - D8

D0 (First Valid Write)

tENS

WEN1

tENS

WEN2

(If Applicable)

(1)

FRL

tSKEW1

RCLK

REF

tENS

REN1,

REN2

Q0 - Q8

tOLZ

tOE

NOTE:

1. When t^SKEW1≥ minimum specification, tFRL = tCLK + tSKEW1

4092 drw09

When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (EF = LOW).

Figure 7. First Data Word Latency Timing

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

NO WRITE

WCLK

tSKEW1

tDS

D0 - D8

WFF

(1)

ENS

tENH

tENS

WEN1

(1)

ENS

tENS

tENH

WEN2

(If Applicable)

RCLK

tENH

tENS

REN1,

REN2

LOW

- Q8

DATA READ

NEXT DATA READ

DATA IN OUTPUT REGISTER

4092 drw10

NOTE:

1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.

Figure 8. Full Flag Timing

WCLK

tDS

DATA WRITE 1

DATA WRITE 2

D0 - D8

ENH

ENS

ENH

WEN1

ENS

ENH

WEN2

(If Applicable)

(1)

FRL

(1)

FFL

tSKEW1

RCLK

tREF

REN1,

REN2

LOW

DATA READ

DATA IN OUTPUT REGISTER

Q0 - Q8

4092 drw11

NOTE:

1. When t^SKEW1≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (EF = LOW).

Figure 9. Empty Flag Timing

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLKH

tCLKL

(4)

WCLK

tENS

tENH

WEN1

tENS

tENH

WEN2

(If Applicable)

PAF

Full - (m + 1) words in FIFO⁽¹⁾

Full - m words in FIFO ⁽²⁾

PAF

(3)

PAF

tSKEW2

RCLK

tENS

tENH

REN1,

REN2

4092 drw12

NOTES:

1. m = PAF offset.

2. 256 - m words in FIFO for IDT72V201, 512 - m words for IDT72V211, 1,024 - m words for IDT72V221, 2,048 - m words for IDT72V231, 4,096 - m words for IDT72V241, 8,192 - m

words for IDT72V251.

3. t^SKEW2is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and

the rising edge of WCLK is less than t^SKEW2, then PAF may not change state until the next WCLK rising edge.

4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.

Figure 10. Programmable Full Flag Timing

tCLKH

tCLKL

WCLK

ENH

ENS

WEN1

WEN2

(If Applicable)

n + 1 words in FIFO

n words in FIFO⁽¹⁾

PAE

(2)

tSKEW2

PAE

(3)

RCLK

tENH

tENS

REN1,

REN2

4092 drw13

NOTES:

1. n = PAE offset.

2. t^SKEW2is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and

the rising edge of RCLK is less than t^SKEW2, then PAE may not change state until the next RCLK rising edge.

3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.

Figure 11. Programmable Empty Flag Timing

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLK

tCLKH

tCLKL

WCLK

tENS

tENH

tENS

WEN1

tDS

tDH

D0 - D7

4092 drw14

PAE OFFSET

(LSB)

PAE OFFSET

(MSB)

PAF OFFSET

(LSB)

PAF OFFSET

(MSB)

Figure 12. Write Offset Registers Timing

tCLK

tCLKH

tCLKL

RCLK

tENS

tENH

tENS

REN1,

REN2

EMPTY OFFSET

(LSB)

EMPTY OFFSET

(MSB)

FULL OFFSET

(LSB)

DATA IN OUTPUT REGISTER

Q0 - Q7

FULL OFFSET

(MSB)

4092 drw15

Figure 13. Read Offset Registers Timing

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™

256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

theReadEnable2(REN2)controlinputcanbegrounded(seeFigure14). In

thisconfiguration,theWriteEnable2/Load(WEN2/LD)pinissetLOWatReset

sothatthe pinoperates as a controltoloadandreadthe programmable flag

offsets.

OPERATINGCONFIGURATIONS

SINGLE DEVICE CONFIGURATION

A single IDT72V201/72V211/72V221/72V231/72V241/72V251 may be

usedwhentheapplicationrequirementsarefor256/512/1,024/2,048/4,096/

8,192wordsorless. WhentheseFIFOsareinaSingleDeviceConfiguration,

RESET (RS)

WRITE CLOCK (WCLK)

READ CLOCK (RCLK)

WRITE ENABLE 1 (WEN1)

IDT

72V201

READ ENABLE 1 (REN1)

OUTPUT ENABLE (OE)

WRITE ENABLE 2/LOAD (WEN2/LD)

DATA IN (D - D8)

72V211

72V221

72V231

72V241

72V251

DATA OUT (Q

EMPTY FLAG (EF)

PROGRAMMABLE ALMOST-EMPTY (

0 - Q8)

FULL FLAG (FF)

PROGRAMMABLE ALMOST-FULL (PAF)

PAE)

4092 drw16

READ ENABLE 2 (REN2)

Figure 14. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 Synchronous FIFO

WIDTH EXPANSION CONFIGURATION

1,024/2,048/4,096/8,192words. Theexistenceoftwoenablepinsontheread

andwriteportallowdepthexpansion. TheWriteEnable2/Loadpinisusedas

a secondwrite enable ina depthexpansionconfigurationthus the program-

mableflagsaresettothedefaultvalues. Depthexpansionispossiblebyusing

oneenableinputforsystemcontrolwhiletheotherenableinputiscontrolledby

expansionlogictodirecttheflowofdata. Atypicalapplicationwouldhavethe

expansionlogicalternatedataaccessfromonedevicetothenextinasequential

manner. TheseFIFOsoperateintheDepthExpansionconfigurationwhenthe

followingconditionsaremet:

Wordwidthmaybeincreasedsimplybyconnectingthecorrespondinginput

controlssignalsofmultipledevices. Acompositeflagshouldbecreatedforeach

oftheend-pointstatusflags(EFandFF). Thepartialstatusflags(AEandAF)

canbedetectedfromanyonedevice. Figure15demonstratesa18-bitword

widthbyusingtwoIDT72V201/72V211/72V221/72V231/72V241/72V251s.

Any word width can be attained by adding additional IDT72V201/72V211/

72V221/72V231/72V241/72V251s.

When these devices are in a Width Expansion Configuration, the Read

Enable 2 (REN2) control input can be grounded (see Figure 15). In this

configuration,theWriteEnable2/Load(WEN2/LD)pinissetLOWatResetso

thatthepinoperatesasacontroltoloadandreadtheprogrammableflagoffsets.

1. The WEN2/ LD pin is held HIGH during Reset so that this pin

operatesasecondWriteEnable.

2. Externallogicisusedtocontroltheflowofdata.

Please see the Application Note" DEPTH EXPANSION OF IDT'S SYN-

CHRONOUSFIFOsUSINGTHERINGCOUNTERAPPROACH"fordetails

ofthisconfiguration.

DEPTHEXPANSION

The IDT72V201/72V211/72V221/72V231/72V241/72V251 can be

adaptedtoapplicationswhentherequirementsareforgreaterthan256/512/

RESET (RS)

DATA IN (D)

READ CLOCK (RCLK)

WRITE CLOCK (WCLK)

READ ENABLE (REN)

WRITE ENABLE1 (WEN1)

OUTPUT ENABLE (OE)

IDT

WRITE ENABLE2/LOAD (WEN2/LD)

72V201

72V211

72V221

72V231

72V241

72V251

72V201

72V211

72V221

72V231

72V241

72V251

PROGRAMMABLE (PAE)

FULL FLAG (FF) #1

FULL FLAG (FF) #2

EMPTY FLAG (EF) #1

EMPTY FLAG (EF) #2

PROGRAMMABLE (PAF)

DATA OUT (Q)

READ ENABLE 2 (REN2)

4092 drw17

Figure 15. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18

Synchronous FIFO Used in a Width Expansion Configuration

ORDERINGINFORMATION

IDT

XXXXX

Device Type Power

Speed

Package

Process/

Temperature

Range

BLANK

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Plastic Leaded Chip Carrier (PLCC, J32-1)

Plastic Thin Quad Flatpack (TQFP, PR32-1)

Commercial Only

Commercial & Industrial

Commercial Only

Clock Cycle Time (tCLK

Speed in Nanoseconds

)

Low Power

72V201

72V211

72V221

72V231

72V241

72V251

256 x 9

512 x 9

1,024 x 9

2,048 x 9

4,096 x 9

8,192 x 9

3.3V SyncFIFO

4092 drw 18

NOTE:

1. Industrial temperature range product for the 15ns is available as a standard device. All other speed grades are available by special order.

DATASHEETDOCUMENTHISTORY

01/11/2002

02/01/2002

pg. 3.

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

408-330-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

IDT72V251L20PFI [IDT]

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