IDT72V3664L10PF9_技术文档

3.3 VOLT CMOS SyncBiFIFO^TMWITH BUS-MATCHING

2,048 x 36 x 2

4,096 x 36 x 2

8,192 x 36 x 2

IDT72V3654

IDT72V3664

IDT72V3674

• Big- or Little-Endian format for word and byte bus sizes

• Retransmit Capability

• Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

• Mailbox bypass registers for each FIFO

• Free-running CLKA and CLKB may be asynchronous or coincident

(simultaneous reading and writing of data on a single clock edge

is permitted)

• Auto power down minimizes power dissipation

• Available in space saving 128-pin Thin Quad Flatpack (TQFP)

• Pin and functionally compatible version of the 5V operating

IDT723654/723664/723674

FEATURES

• Memory storage capacity:

IDT72V3654

IDT72V3664

IDT72V3674

–

2,048 x 36 x 2

4,096 x 36 x 2

8,192 x 36 x 2

• Clock frequencies up to 100 MHz (6.5ns access time)

• Two independent clocked FIFOs buffering data in opposite

directions

• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRB flag functions)

• Programmable Almost-Empty and Almost-Full flags; each has five

default offsets (8, 16, 64, 256 and 1,024 )

• Serial or parallel programming of partial flags

• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

• Pin compatible to the lower density parts, IDT72V3624/72V3634/

72V3644

• Industrial temperature range (–40°C to +85°C) is available

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

Register

CLKA

Port-A

Control

Logic

CSA

W/RA

ENA

RAM ARRAY

2,048 x 36

4,096 x 36

8,192 x 36

36

MBA

36

FIFO1,

Mail1

Reset

Logic

MRS1

PRS1

Write

Pointer

Read

Pointer

36

Status Flag

Logic

EFB/ORB

AEB

FFA/IRA

AFA

FIFO1

FIFO2

FS2

FS0/SD

Programmable Flag

Offset Registers

Timing

Mode

FWFT

FS1/SEN

B0-B35

A0-A35

13

Status Flag

Logic

EFA/ORA

FFB/IRB

AFB

AEA

36

Read

Pointer

Write

Pointer

36

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

RT1

RTM

RT2

FIFO1 and

FIFO2

Retransmit

Logic

RAM ARRAY

2,048 x 36

4,096 x 36

8,192 x 36

36

CLKB

CSB

W/RB

ENB

MBB

BE

Port-B

Control

Logic

Mail 2

Register

BM

SIZE

MBF2

4664 drw01

IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc. TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

NOVEMBER 2003

COMMERCIAL TEMPERATURE RANGE

1



DSC-4664/5

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

portSRAMFIFOsonboardeachchipbufferdatainoppositedirections. FIFO

dataonPortBcanbeinputandoutputin36-bit,18-bit,or9-bitformatswitha

choiceofBig-orLittle-Endianconfigurations.

These devices are a synchronous (clocked) FIFO, meaning each port

employsasynchronousinterface. Alldatatransfersthroughaportaregated

totheLOW-to-HIGHtransitionofaportclockbyenablesignals. Theclocksfor

each port are independent of one another and can be asynchronous or

DESCRIPTION

TheIDT72V3654/72V3664/72V3674arepinandfunctionallycompat-

ible versions of the IDT723654/723664/723674, designed to run off a 3.3V

supplyforexceptionallylow-powerconsumption. Thesedevicesaremono-

lithic, high-speed, low-power, CMOS bidirectional synchronous (clocked)

FIFOmemorywhichsupportsclockfrequenciesupto100MHzandhasread

accesstimesasfastas6.5ns. Twoindependent2,048/4,096/8,192 x 36dual-

PIN CONFIGURATION

INDEX

W/RA

ENA

CLKA

3

GND

A35

5

A34

A33

7

A32

Vcc

A31

A30

GND

A29

A28

A27

A26

A25

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

CLKB

PRS2/RT2

Vcc

1

2

B35

B34

B33

B32

RTM

GND

B31

B30

B29

B28

B27

B26

Vcc

4

6

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

B25

B24

BM

A24

A23

BE/FWFT

GND

A22

GND

B23

B22

B21

B20

B19

B18

GND

B17

B16

SIZE

Vcc

B15

B14

B13

B12

GND

B11

B10

Vcc

A21

A20

A19

A18

GND

A17

A16

A15

A14

A13

Vcc

A12

GND

A11

A10

4664 drw 02

TQFP (PK128-1, order code: PF)

TOP VIEW

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IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

coincident. The enables for each port are arranged to provide a simple outputs,noreadoperationisrequired(Nevertheless,accessingsubsequent

bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro- wordsdoesnecessitateaformalreadrequest).ThestateoftheBE/FWFTpin

nouscontrol.

CommunicationbetweeneachportmaybypasstheFIFOsviatwomailbox

duringFIFOoperationdetermines themodeinuse.

EachFIFOhas acombinedEmpty/OutputReadyFlag(EFA/ORAand

registers.Themailboxregisters’widthmatchestheselectedPortBbuswidth. EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/

EachMailboxregisterhas a flag(MBF1 andMBF2)tosignalwhennewmail IRB). The EF and FF functions are selected in the IDT Standard mode. EF

has beenstored.

indicates whether or not the FIFO memory is empty. FF shows whether the

TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial memoryisfullornot.TheIRandORfunctionsareselectedintheFirstWord

Reset. MasterResetinitializesthereadandwritepointerstothefirstlocation FallThroughmode.IRindicateswhetherornottheFIFOhasavailablememory

of the memory array, configures the FIFO for Big- or Little-Endian byte locations.ORshowswhethertheFIFOhasdataavailableforreadingornot.

arrangementandselectsserialflagprogramming,parallelflagprogramming, Itmarksthepresenceofvaliddataontheoutputs.

oroneoffivepossibledefaultflagoffsetsettings,8,16,64,256or1,024.There

are two Master Reset pins, MRS1 and MRS2.

Each FIFO has a programmable Almost-Empty flag (AEA and AEB)

and a programmable Almost-Full flag (AFA and AFB). AEA and AEB

PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe indicatewhenaselectednumberofwordsremainintheFIFOmemory.AFA

memory.UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e., and AFB indicate when the FIFO contains more than a selected number of

programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset words.

is useful since it permits flushing of the FIFO memory without changing any

configurationsettings.EachFIFOhasitsown,independentPartialResetpin, port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and

PRS1 and PRS2. AEBaretwo-stagesynchronizedtotheportclockthatreadsdatafromitsarray.

FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the

BothFIFO'shaveRetramsmitcapability,whenaRetransmitisperformed Programmable offsets for AEA, AEB, AFA and AFB are loaded in parallel

onarespectiveFIFOonlythereadpointerisresettothefirstmemorylocation. usingPortAorinserialvia the SDinput. Five defaultoffsetsettings are also

ARetransmitisperformedbyusingtheRetransmitMode,RTMpininconjunction provided. The AEA and AEB threshold can be set at 8, 16, 64, 256 or 1,024

withtheRetransmitpinsRT1orRT2,foreachrespectiveFIFO.Notethatthe locations from the empty boundary and the AFA and AFB threshold can be

two Retransmit pins RT1 and RT2 are muxed with the Partial Reset pins.

Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, are made using the FS0, FS1 and FS2 inputs during Master Reset.

thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray. A Interspersed Parity can also be selected during a Master Reset of the

setat8,16,64,256or1,024locationsfromthefullboundary.Allthesechoices

read operation is required to access that word (along with all other words FIFO.IfInterspersedParityisselectedthenduringparallelprogrammingofthe

residing in memory). In the First Word Fall Through mode (FWFT), the first flagoffsetvalues,thedevicewillignoredatalineA8.IfNon-InterspersedParity

wordwrittentoanemptyFIFOappearsautomaticallyontheoutputs,noread is selectedthendatalineA8willbecomeavalidbit.

operationrequired(Nevertheless,accessingsubsequentwordsdoesneces-

sitate a formal read request). The state of the BE/FWFT pin during Master If, at any time, the FIFO is not actively performing a function, the chip will

Resetdeterminesthemodeinuse. automatically power down. During the power down state, supply current

Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.

Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode, consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol

thefirstwordwrittentoanemptyFIFOis depositedintothememoryarray.A inputs)willimmediatelytakethedeviceoutofthepowerdownstate.

read operation is required to access that word (along with all other words

TheIDT72V3654/72V3664/72V3674arecharacterizedforoperationfrom

residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstlong- 0°Cto70°C.Industrialtemperaturerange(-40°Cto+85°C)isavailable.They

word (36-bit wide) written to an empty FIFO appears automatically on the arefabricatedusingIDT’shighspeed,submicronCMOStechnology.

3

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

PINDESCRIPTIONS

Symbol

A0-A35

AEA

Name

I/O

O

Description

PortAData

36-bitbidirectionaldataportforsideA.

PortAAlmost-

EmptyFlag

ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwordsin

FIFO2islessthanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.

AEB

PortBAlmost-

EmptyFlag

O

ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwordsin

FIFO1islessthanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.

AFA

PortAAlmost-

Full Flag

ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty

locationsinFIFO1islessthanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.

AFB

PortBAlmost-

Full Flag

ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofempty

locations inFIFO2is less thanorequaltothevalueintheAlmost-FullBOffsetregister,Y2.

B0-B35

PortAData

I/O

I

36-bitbidirectionaldataportforsideB.

BE/FWFT Big-Endian/

FirstWord

This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation.

Inthis case, dependingonthe bus size, the mostsignificantbyte orwordonPortAis readfrom

PortBfirst (A-to-Bdata flow)orwrittentoPortBfirst(B-to-Adata flow). ALOWonBEwillselect

Little-Endianoperation. Inthis case,theleastsignificantbyteorwordonPortAis readfromPortB

first(forA-to-Bdataflow)orwrittentoPortBfirst(B-to-Adata flow). After Master Reset, this pin

selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word

FallThroughmode.Oncethetimingmodehas beenselected,thelevelonFWFTmustbestatic

throughoutdeviceoperation.

Fall Through

Select

(1)

BM

Bus-MatchSelect

(Port B)

I

A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of

SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and

endianarrangementforPortB.ThelevelofBMmustbestaticthroughoutdeviceoperation.

CLKA

CLKB

PortAClock

PortBClock

CLKAis acontinuous clockthatsynchronizes alldatatransfers throughPortAandcanbe

asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are allsynchronized

totheLOW-to-HIGHtransitionofCLKA.

CLKBis acontinuous clockthatsynchronizes alldatatransfers throughPortBandcanbe

asynchronous orcoincidenttoCLKA. FFB/IRB, EFB/ORB, AFB, andAEB are synchronizedto

theLOW-to-HIGHtransitionofCLKB.

CSA

CSB

PortAChipSelect

PortBChipSelect

I

CSA mustbeLOWtoenabletoLOW-to-HIGHtransitionofCLKAtoreadorwriteonPortA.

The A0-A35outputs are inthe high-impedance state when CSAis HIGH.

CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.

The B0-B35outputs are inthe high-impedance state when CSBis HIGH.

EFA/ORA PortAEmpty/

OutputReadyFlag

O

This is a dualfunctionpin. Inthe IDTStandardmode, the EFA functionis selected. EFA

indicates whetherornotthe FIFO2memoryis empty. Inthe FWFTmode, the ORAfunctionis

selected. ORAindicates thepresenceofvaliddataonA0-A35outputs,availableforreading.

EFA/ORAissynchronizedtotheLOW-to-HIGHtransitionofCLKA.

EFB/ORB PortBEmpty/

OutputReadyFlag

O

This is adualfunctionpin.IntheIDTStandardmode,theEFBfunctionis selected. EFBindicates

whetherornotthe FIFO1memoryis empty. Inthe FWFTmode, the ORBfunctionis selected. ORB

indicates thepresenceofvaliddataontheB0-B35outputs,availableforreading. EFB/ORBis

synchronizedtotheLOW-to-HIGHtransitionofCLKB.

ENA

PortAEnable

I

ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onPortA.

ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onPortB.

ENB

PortBEnable

FFA/IRA

PortAFull/

Input Ready Flag

O

This is a dualfunctionpin. Inthe IDTStandardmode, the FFA functionis selected. FFA indicates

whetherornotthe FIFO1memoryis full. Inthe FWFTmode, the IRAfunctionis selected. IRA

indicates whetherornotthere is space available forwritingtothe FIFO1memory. FFA/IRAis

synchronizedtotheLOW-to-HIGHtransitionofCLKA.

FFB/IRB

PortBFull/

Input Ready Flag

O

This is adualfunctionpin.IntheIDTStandardmode,the FFB functionis selected. FFB indicates

whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB

indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is

synchronized to the LOW-to-HIGH transition of CLKB.

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IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/O

Description

FS0/SD

FlagOffsetSelect0/

SerialData

I

FS1/SENandFS0/SDaredual-purposeinputs usedforflagoffsetregisterprogramming. During

MasterReset,FS1/SENandFS0/SD,togetherwithFS2,selecttheflagoffsetprogrammingmethod

Threeoffsetregisterprogrammingmethodsareavailable:automaticallyloadoneoffivepresetvalues

(8, 16, 64, 256 or 1,024), parallel load from Port A, and serial load.

FS1/SEN

FlagOffsetSelect1/

SerialEnable,

I

Whenserialloadisselectedforflagoffsetregisterprogramming,FS1/SENisusedasanenable

synchronous totheLOW-to-HIGHtransitionofCLKA.WhenFS1/SENis LOW,arisingedgeonCLKA

load the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program

the offset registers is 44 for the IDT72V3654, 48 for the IDT72V3664, and 52 for the IDT72V3674.

The firstbitwrite stores the Y-register(Y1)MSBandthe lastbitwrite stores the X-register(X2)LSB.

FS2⁽¹⁾

FlagOffsetSelect2

MBA

MBB

MBF1

Port A Mailbox

Select

I

A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When

theA0-A35outputsareactive,aHIGHlevelonMBAselectsdatafromthemail2registerforoutput

andaLOWlevelselectsFIFO2outputregisterdataforoutput.

Port B Mailbox

Select

A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the

B0-B35outputs areactive,aHIGHlevelonMBBselects datafromthemail1registerforoutputand

aLOWlevelselectsFIFO1outputregisterdataforoutput.

Mail1Register

Flag

O

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.

Writes tothe mail1registerare inhibitedwhile MBF1 is LOW. MBF1 is setHIGHbya LOW-to-HIGH

transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either

a MasterorPartialResetofFIFO1.

MBF2

MRS1

Mail2Register

Flag

O

I

MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdatatothemail2register.Writes

tothe mail2registerare inhibitedwhile MBF2is LOW. MBF2 is setHIGHbya LOW-to-HIGH

transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following

eithera MasterorPartialResetofFIFO2.

FIFO1Master

Reset

ALOWonthis pin initializes the FIFO1readandwrite pointers tothe firstlocationofmemoryand sets the

Port B output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming

method(serialorparallel)andoneoffiveprogrammableflagdefaultoffsets forFIFO1andFIFO2.It

also configures PortBforbus size andendianarrangement. FourLOW-to-HIGHtransitions ofCLKA

andfourLOW-to-HIGHtransitionsofCLKBmustoccurwhileMRS1isLOW.

MRS2

FIFO2Master

Reset

I

ALOWonthispininitializestheFIFO2readandwritepointerstothefirstlocationofmemoryandsets

thePortAoutputregistertoallzeroes.ALOW-to-HIGHtransitiononMRS2,toggledsimultaneouslywith

MRS1,selectstheprogrammingmethod(serialorparallel)andoneoftheprogrammableflagdefault

offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB

mustoccurwhileMRS2isLOW.

PRS1/

RT1

PartialReset/

RetransmitFIFO1

This pinis muxedforbothPartialReset andRetransmitoperations,itis usedinconjunctionwiththeRTM

pin. IfRTMis ina LOWcondition, a LOWonthis pinperforms a PartialResetonFIFO1andinitializes

theFIFO1readandwritepointerstothefirstlocationofmemoryandsetsthePortBoutputregisterto

allzeroes.DuringPartialReset,thecurrentlyselectedbussize,endianarrangement,programming

method(serialorparallel), andprogrammable flagsettings are allretained. IfRTMis HIGH, a LOWon

thispinperformsaRetransmitandinitializestheFIFO1readpointeronlytothefirstmemorylocation.

PRS2/

RT2

PartialReset/

RetransmitFIFO2

I

This pinis muxedforbothPartialReset andRetransmitoperations,itis usedinconjunctionwiththeRTM

pin. IfRTMis ina LOWcondition, a LOWonthis pinperforms a PartialResetonFIFO2andinitializes

theFIFO2readandwriteselectedbus size,endianarrangement,programmingmethod(serialor

parallel),andprogrammableflagsettings areallretained.IfRTMis HIGH,aLOWonthis pinperforms

aRetransmitandinitializestheFIFO2readpointeronlytothefirstmemorylocation.

RTM

RetransmitMode

BusSizeSelect

I

This pinis usedinconjunctionwiththe RT1 andRT2 pins. WhenRTMis HIGHa Retransmitis performed

on FIFO1 or FIFO2 respectively.

(1)

SIZE

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when

BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian

arrangementforPortB.ThelevelofSIZEmustbestaticthroughoutdeviceoperation

NOTE:

1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or V^CC.

5

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/O

Description

W/RA

Port-AWrite/

ReadSelect

I

A HIGHselects a write operationanda LOWselects a readoperationonPortAfora LOW-to-HIGH

transitionofCLKA.TheA0-A35outputs areintheHIGHimpedancestatewhenW/RAis HIGH.

W/RB

Port-BWrite/

ReadSelect

I

A LOWselects a write operationanda HIGHselects a readoperationonPortBfora LOW-to-HIGH

transitionofCLKB.TheB0-B35outputsareintheHIGHimpedancestatewhenW/RBisLOW.

6

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR

TEMPERATURE RANGE (Unless otherwise noted)⁽¹⁾

Symbol

Rating

Commercial

–0.5to+4.6

–0.5 to VCC+0.5

±20

Unit

V

VCC

SupplyVoltageRange

InputVoltageRange

OutputVoltageRange

(2)

VI

V

(2)

VO

V

IIK

Input Clamp Current (VI < 0 or VI > VCC)

Output Clamp Current (VO = < 0 or VO > VCC)

Continuous Output Current (VO = 0 to VCC)

Continuous Current Through VCC or GND

StorageTemperatureRange

mA

°C

IOK

±50

IOUT

ICC

±50

±400

TSTG

–65 to 150

NOTES:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these

or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect

device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

RECOMMENDEDOPERATINGCONDITIONS

Symbol

Parameter

SupplyVoltagefor10ns

SupplyVoltagefor15ns

High-LevelInputVoltage

Low-LevelInputVoltage

High-LevelOutputCurrent

Low-LevelOutputCurrent

OperatingTemperature

Min.

3.15

3.0

2

Typ.

3.3

—

Max.

3.45

3.6

Unit

V

(1)

VCC

VIH

VIL

IOH

IOL

TA

V

VCC+0.5

0.8

V

—

0

—

V

—

–4

mA

°C

—

8

—

70

NOTE:

1. For 10ns speed grade: Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-

AIR TEMPERATURE RANGE (Unless otherwise noted)

IDT72V3654

IDT72V3664

IDT72V3674

Commercial

tCLK = 10, 15 ns⁽²⁾

Symbol

VOH

VOL

Parameter

OutputLogic"1"Voltage

OutputLogic"0"Voltage

InputLeakageCurrent(AnyInput)

OutputLeakageCurrent

Test Conditions

IOH = –4 mA

Min.

2.4

—

Typ.⁽¹⁾

—

4

Max.

—

0.5

±10

5

Unit

V

VCC = 3.0V,

VCC = 3.6V,

IOL = 8 mA

V

ILI

VI = VCC or 0

µ A

mA

pF

ILO

VO = VCC or 0

VI = VCC –0.2V or 0V

f = 1 MHz

ICC2⁽³⁾

ICC3⁽³⁾

Standby Current (with CLKA & CLKB running) VCC = 3.6V,

StandbyCurrent(noclocksrunning)

InputCapacitance

VCC = 3.6V,

VI = 0,

1

(4)

CIN

—

(4)

COUT

OutputCapacitance

VO = 0,

f = 1 MHZ

8

pF

NOTES:

1. All typical values are at V^CC= 3.3V, TA = 25°C.

2. Commercial-10ns speed grade only: Vcc = 3.3V ± 0.15V, TA = 0° to +70°; JEDEC JESD8-A compliant.

3. For additional I^CCinformation, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).

4. Characterized values, not currently tested.

7

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

TheICC(f)currentforthegraphinFigure1wastakenwhilesimultaneouslyreadingandwritingaFIFOontheIDT72V3654/72V3664/72V3674withCLKA

andCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnected

tonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice'sinputsdrivenbyTTL

HIGHlevels areknown,thepowerdissipationcanbecalculatedwiththeequationbelow.

CALCULATING POWER DISSIPATION

WithICC(f) takenfromFigure1,themaximumpowerdissipation(PT)oftheseFIFOs maybecalculatedby:

2

PT = VCC x ICC(f) + Σ(CL x VCC x fo)

N

where:

N

CL

fo

=

number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)

output capacitance load

switchingfrequencyofanoutput

100

90

VCC = 3.6V

80

70

60

VCC = 3.0V

VCC = 3.3V

fdata = 1/2 fS

TA

= 25°C

CL

= 0 pF

50

40

30

20

10

0

100

0

10

20

30

40

50

Clock Frequency  MHz

60

70

90

80

4664 drw03

fS



Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)

8

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70° C;JEDEC JESD8-A compliant)

IDT72V3654L10⁽¹⁾

IDT72V3664L10⁽¹⁾

IDT72V3674L10⁽¹⁾

IDT72V3654L15

IDT72V3664L15

IDT72V3674L15

Symbol

fS

Parameter

Min.

—

10

4.5

3

Max.

100

—

Min.

—

15

6

Max.

Unit

MHz

ns

Clock Frequency, CLKA or CLKB

66.7

—

tCLK

tCLKH

tCLKL

tDS

Clock Cycle Time, CLKA or CLKB

Pulse Duration, CLKA or CLKB HIGH

PulseDuration, CLKAandCLKBLOW

SetupTime, A0-A35before CLKA↑andB0-B35before CLKB↑

—

ns

—

6

—

ns

—

4

—

ns

tENS1

SetupTime,CSA andW/RAbefore CLKA↑;CSB and

W/RBbeforeCLKB↑

4

—

4.5

—

ns

tENS2

tRSTS

Setup Time, ENA, and MBA before CLKA↑; ENB, and

MBBbeforeCLKB↑

3

5

—

4.5

5

—

ns

Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before

(2)

CLKA↑orCLKB↑

tFSS

tBES

tSDS

Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH

SetupTime, BE/FWFT beforeMRS1 andMRS2HIGH

SetupTime,FS0/SDbeforeCLKA↑

7.5

3

—

7.5

4

—

ns

tSENS

tFWS

tRTMS

tDH

SetupTime,FS1/SENbeforeCLKA↑

3

4

SetupTime,BE/FWFTbeforeCLKA↑

0

Setup Time, RTM before RT1; RTM before RT2

HoldTime,A0-A35afterCLKA↑andB0-B35afterCLKB↑

5

0.5

1

tENH

HoldTime, CSA, W/RA, ENA, andMBAafterCLKA↑;CSB,

W/RB, ENB, andMBBafterCLKB↑

1

tRSTH

Hold Time, MRS1, MRS2, PRS1 orPRS2 LOW after CLKA↑

4

—

4

—

ns

(2)

orCLKB↑

tFSH

Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH

Hold Time, BE/FWFT after MRS1 and MRS2 HIGH

HoldTime, FS0/SDafterCLKA↑

2

—

2

—

ns

tBEH

tSDH

0.5

2

1

tSENH

tSPH

HoldTime,FS1/SENHIGHafterCLKA↑

1

Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH

HoldTime, RTMafterRT1;RTMafterRT2

2

tRTMH

tSKEW1⁽³⁾

5

SkewTimebetweenCLKA↑andCLKB↑forEFA/ORA,

EFB/ORB, FFA/IRA, and FFB/IRB

5

7.5

tSKEW2^(3,4)SkewTime betweenCLKA↑andCLKB↑ forAEA,AEB, AFA,

12

—

12

—

ns

and AFB

NOTES:

1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°.

2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

4. Design simulated, not tested.

9

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C^L= 30pF

(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0^οC to +70^οC;JEDEC JESD8-A compliant)

IDT72V3654L10⁽¹⁾

IDT72V3664L10⁽¹⁾

IDT72V3674L10⁽¹⁾

IDT72V3654L15

IDT72V3664L15

IDT72V3674L15

Symbol

tA

Parameter

Min.

2

Max.

Min.

2

Max.

Unit

ns

Access Time,CLKA↑toA0-A35andCLKB↑toB0-B35

6.5

10

8

tWFF

PropagationDelayTime, CLKA↑ toFFA/IRAandCLKB↑

toFFB/IRB

2

ns

tREF

tPAE

tPAF

tPMF

tPMR

tMDV

tRSF

PropagationDelayTime,CLKA↑toEFA/ORAandCLKB↑

toEFB/ORB

1

0

3

1

6.5

8

1

0

2

1

8

ns

PropagationDelayTime,CLKA↑toAEAandCLKB↑to

AEB

PropagationDelayTime,CLKA↑toAFAandCLKB↑to

AFB

8

Propagation Delay Time, CLKA↑ toMBF1 LOW or MBF2

HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH

8

PropagationDelayTime, CLKA↑toB0-B35⁽²⁾andCLKB↑

10

15

toA0-A35⁽³⁾

Propagation Delay Time, MBA to A0-A35 valid and MBB to

B0-B35 valid

6.5

10

Propagation Delay Time, MRS1 or PRS1 LOW to AEB

LOW, AFA HIGH, and MBF1 HIGH and MRS2 or PRS2

LOW to AEA LOW, AFB HIGH, and MBF2 HIGH

tEN

tDIS

Enable Time, CSA orW/RALOWtoA0-A35Active and

CSB LOW and W/RB HIGH to B0-B35 Active

2

1

6

2

1

10

8

ns

Disable Time, CSA or W/RA HIGH to A0-A35 at high

impedance and CSB HIGH or W/RB LOW to B0-B35 at

highimpedance

NOTES:

1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°.

2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.

3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.

10

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit

initializesthereadpointerofFIFO1tothefirstmemorylocation.

The FIFO2 memory undergoes a Retransmit by taking its associated

Retransmit(RT2)inputLOWforatleastfourPortAClock(CLKA)andfourPort

CClock(CLKC)LOW-to-HIGHtransitions.TheRetransmitinitializestheread

pointerofFIFO2tothefirstmemorylocation.

The RTM pin must be HIGH during the time of Retranmit. Note that the

RT1inputismuxedwiththePRS1input,thestateoftheRTMpindetermining

whetherthispinperformsaRetransmitorPartialReset.Also,theRT2inputis

muxedwiththePRS2input,thestateoftheRTMpindeterminingwhetherthis

pinperformsaRetransmitorPartialReset.

SIGNALDESCRIPTION

MASTER RESET (MRS1, MRS2)

Afterpowerup,aMasterReset operationmustbeperformedbyproviding

a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, each of the

two FIFO memories of the IDT72V3654/72V3664/72V3674 undergoes a

complete reset by taking its associated Master Reset (MRS1, MRS2) input

LOWforatleastfourPortAClock(CLKA)andfourPortBClock(CLKB)LOW-

to-HIGHtransitions. TheMasterResetinputscanswitchasynchronouslyto

theclocks.AMasterReset initializestheassociatedwriteandreadpointersto

thefirstlocationofthememoryandforcestheFull/InputReadyflag(FFA/IRA,

FFB/IRB)LOW,theEmpty/OutputReadyflag(EFA/ORA,EFB/ORB)LOW,

the Almost-Empty flag (AEA, AEB) LOW and forces the Almost-Full flag

(AFA, AFB)HIGH. AMasterResetalsoforces theassociatedMailboxFlag

(MBF1, MFB2)ofthe parallelmailboxregisterHIGH. Aftera MasterReset,

theFIFO'sFull/InputReadyflagissetHIGHaftertwowriteclockcycles. Then

the FIFO is ready to be written to.

BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)

— ENDIAN SELECTION

Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction

isactive,permittingachoiceofBigorLittle-Endianbytearrangementfordata

writtentoorreadfromPortB.This selectiondetermines theorderbywhich

bytes (orwords)ofdata are transferredthroughthis port. Forthe following

illustrations,assumethatabyte(orword)bussizehasbeenselectedforPort

B.(NotethatwhenPortBis configuredforalongwordsize,theBig-Endian

A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input

latches the values ofthe Big-Endian(BE)inputfordeterminingthe orderby

whichbytes are transferredthroughPortB. Italso latches the values ofthe

FlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-FullandAlmost-

Emptyoffsetprogrammingmethod.

1

functionhas noapplicationandthe BEinputis a “don’tcare” .)

AHIGHonthe BE/FWFTinputwhenthe MasterReset(MRS1, MRS2)

inputsgofromLOWtoHIGHwillselectaBig-Endianarrangement.Whendata

ismovinginthedirectionfromPortAtoPortB,themostsignificantbyte(word)

ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant

byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When

data is movinginthe directionfromPortBtoPortA, the byte (word)written

toPortBfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthe

long word; the byte (word) written to Port B last will be read from Port A as

theleastsignificantbyte(word)ofthelongword.

A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) clears

theFlagOffsetRegistersofFIFO2(X2,Y2). ALOW-to-HIGHtransitiononthe

FIFO2MasterReset(MRS2)togetherwiththeFIFO1MasterReset(MRS1)

inputlatchesthevalueoftheBig-Endian(BE)inputforPortBandalsolatches

thevaluesoftheFlagSelect(FS0,FS1andFS2)inputsforchoosingtheAlmost-

FullandAlmost-Emptyoffsetprogrammingmethod. (FordetailsseeTable1,

FlagProgramming,andtheProgrammingtheAlmost-EmptyandAlmost-Full

Flagssection). TherelevantFIFOMasterResettimingdiagramcanbefound

in Figure 3.

A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2)

inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata

ismovinginthedirectionfromPortAtoPortB,theleastsignificantbyte(word)

ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant

byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When

data is movinginthe directionfromPortBtoPortA, the byte (word)written

toPortBfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthe

long word; the byte (word) written to Port B last will be read from Port A as

the most significant byte (word) of the long word. Refer to Figure 2 for an

illustrationoftheBEfunction.SeeFigure3(MasterReset)fortheEndianselect

timingdiagram.

PARTIAL RESET (PRS1, PRS2)

EachofthetwoFIFOmemoriesofthesedevicesundergoesalimitedreset

bytakingits associatedPartialReset(PRS1,PRS2)inputLOWforatleast

four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH

transitions.ThePartialResetinputscanswitchasynchronouslytotheclocks.

APartialResetinitializestheinternalreadandwritepointersandforcesthe

Full/Input Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready

flag (EFA/ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB)

LOW,andtheAlmost-Fullflag(AFA,AFB)HIGH.APartialResetalsoforces

theMailboxFlag(MBF1,MBF2)oftheparallelmailboxregisterHIGH.After

a PartialReset,the FIFO’s Full/InputReadyflagis setHIGHaftertwowrite

clock cycles. Then the FIFO is ready to be written to.

— TIMING MODE SELECTION

AfterMasterReset,theFWFTselectfunctionisactive,permittingachoice

betweentwopossibletimingmodes:IDTStandardmodeorFirstWordFall

Through (FWFT) mode. Once the Master Reset (MRS1, MRS2) input is

HIGH, a HIGH on the BE/FWFT input during the next LOW-to-HIGH

transitionofCLKA(forFIFO1)andCLKB(forFIFO2)willselectIDTStandard

mode. This mode uses the Empty Flag function (EFA, EFB) to indicate

whetherornotthereareanywordspresentintheFIFOmemory.Itusesthe

Full Flag function (FFA, FFB) to indicate whether or not the FIFO memory

Whateverflagoffsets,programmingmethod(parallelorserial),andtiming

mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial

Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof

the reset operation. A Partial Reset may be useful in the case where

reprogrammingaFIFOfollowingaMasterResetwouldbeinconvenient.See

Figure4forthePartialResettimingdiagram.

RETRANSMIT (RT1, RT2)

TheFIFO1memoryofthesedevicesundergoesaRetransmitbytakingits hasanyfreespaceforwriting.InIDTStandardmode,everywordreadfrom

associatedRetransmit (RT1)inputLOWforatleastfourPortAClock(CLKA) theFIFO,includingthefirst,mustberequestedusingaformalreadoperation.

NOTE:

1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with

unused inputs) must not be left open, rather they must be either HIGH or LOW.

11

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

orLOWduringamasterreset.Forexample,toloadthepresetvalueof64into

X1andY1,FS0,FS1andFS2mustbeHIGHwhenFlFO1reset(MRS1)returns

HIGH.Flag-offsetregisters associatedwithFIFO2areloadedwithoneofthe

preset values in the same way with FIFO2 Master Reset (MRS2), toggled

simultaneously with FIFO1 Master Reset (MRS1). For relevant preset value

loading timing diagram, see Figure 3.

OncetheMasterReset(MRS1,MRS2)inputisHIGH,aLOWontheBE/

FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and

CLKB(forFIFO2)willselectFWFTmode.ThismodeusestheOutputReady

function(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedata

outputs(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)

toindicate whetherornotthe FIFOmemoryhas anyfree space forwriting.

IntheFWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodata

outputs,noreadrequestnecessary. Subsequentwordsmustbeaccessed

byperforminga formalreadoperation.

PARALLEL LOAD FROM PORT A

ToprogramtheX1,X2,Y1,andY2registersfromPortA,performaMaster

ResetonbothFlFOs simultaneouslywithFS2HIGHorLOW, FS0andFS1

LOWduringtheLOW-to-HIGHtransitionofMRS1andMRS2.ThestateofFS2

atthispointofresetwilldeterminewhethertheparallelprogrammingmethod

hasInterspersedParityorNon-InterspersedParity.RefertoTable1forFlag

Programming Flag Offset setup . It is important to note that once parallel

programminghasbeenselectedduringaMasterResetbyholdingbothFS0

& FS1 LOW, these inputs must remain LOW during all subsequent FIFO

operation. They can only be toggled HIGH when future Master Resets are

performedandotherprogrammingmethodsaredesired.

Afterthisresetiscomplete,thefirstfourwritestoFIFO1donotstoredata

in RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non-

InterspersedParitymodethePortAdatainputsusedbytheOffsetregistersare

(A10-A0), (A11-A0), or (A12-A0) for the IDT72V3654, IDT72V3664, or

IDT72V3674,respectively.ForInterspersedParitymodethePortAdatainputs

usedbytheOffsetregistersare(A11-A9,A7-A0),(A12-A9,A7-A0),or(A13-

A9,A7-A0)fortheIDT72V3654,IDT72V3664,orIDT72V3674,respectively.

The highest numbered input is used as the most significant bit of the binary

numberineachcase.Validprogrammingvaluesfortheregistersrangefrom

1to2,044fortheIDT72V3654;1to4,092fortheIDT72V3664;and1to8,188

fortheIDT72V3674.AfteralltheoffsetregistersareprogrammedfromPortA,

FollowingMasterReset,thelevelappliedtotheBE/FWFTinputtochoose

thedesiredtimingmodemustremainstaticthroughoutFIFOoperation.Refer

toFigure3(MasterReset)foraFirstWordFallThroughselecttimingdiagram.

PROGRAMMINGTHEALMOST-EMPTYANDALMOST-FULLFLAGS

FourregistersintheIDT72V3654/72V3664/72V3674areusedtoholdthe

offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags.ThePortBAlmost-

Emptyflag(AEB)Offsetregisteris labeledX1andthePortAAlmost-Empty

flag (AEA) Offset register is labeled X2. The Port A Almost-Full flag (AFA)

OffsetregisterislabeledY1andthePortBAlmost-Fullflag(AFB)Offsetregister

islabeledY2.TheindexofeachregisternamecorrespondstoitsFIFOnumber.

TheoffsetregisterscanbeloadedwithpresetvaluesduringtheresetofaFIFO,

programmedinparallelusingtheFIFO’sPortAdatainputs,orprogrammed

in serial using the Serial Data (SD) input (see Table 1).

FS0/SD,FS1/SENandFS2functionthesamewayinbothIDTStandard

andFWFTmodes.

— PRESET VALUES

ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith

oneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbeHIGH

TABLE 1 — FLAG PROGRAMMING

FS2

FS1/SEN

FS0/SD

MRS1

MRS2

X1 AND Y1 REGlSTERS⁽¹⁾

X2 AND Y2 REGlSTERS⁽²⁾

H

L

H

L

H

L

H

L

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

X

↑

64

X

H

X

64

H

16

X

H

L

X

16

H

L

8

X

H

X

8

L

256

X

L

X

256

L

1,024

X

1,024

L

X

L

H

SerialprogrammingviaSD

(3,5)

L

ParallelprogrammingviaPortA

IP Mode^{(4, 5)}

L

IP Mode^{(4, 5)}

NOTES:

1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.

2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.

3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.

4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.

5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.

12

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

thePortBFull/InputReadyflag(FFB/IRB)issetHIGH,andbothFIFOsbegin X1,Y2,andfinally,X2. Thefirst-bitwritestoresthemostsignificantbitoftheY1

normaloperation.RefertoFigure5foratimingdiagramillustrationofparallel registerandthelast-bitwritestorestheleastsignificantbitoftheX2register.Each

programmingoftheflagoffsetvalues.

registervaluecanbeprogrammedfrom1to2,044(IDT72V3654),1to4,092

(IDT72V3664), or 1 to 8,188 (IDT72V3674).

INTERSPERSED PARITY

Whentheoptiontoprogramtheoffsetregistersseriallyischosen,thePort

InterspersedParityisselectedduringaMasterResetoftheFIFO.Referto AFull/InputReady(FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.

Table1fortheset-upconfigurationofInterspersedParity.TheInterspersed FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit

Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword isloadedtoallownormalFIFO1operation.ThePortBFull/InputReady(FFB/

loadedintotheparallelport(A0-An)duringprogrammingoftheflagoffsetvalues. IRB)flagalsoremainsLOWthroughouttheserialprogrammingprocess,until

IfInterspersedParityisselectedthenduringparallelprogrammingoftheflag allregisterbitsarewritten.FFB/IRBissetHIGHbytheLOW-to-HIGHtransition

TABLE 2 — PORT A ENABLE FUNCTION TABLE

CSA

W/RA

ENA

MBA

CLKA

Data A (A0-A35) I/O

Port Function

H

L

X

H

L

X

L

X

L

X

↑

High-Impedance

Input

None

H

L

Input

FIFO1 write

Mail1write

H

L

↑

Input

X

↑

Output

None

L

H

L

FIFO2read

None

L

H

X

↑

L

H

Mail2 read (set MBF2 HIGH)

TABLE 3 — PORT B ENABLE FUNCTION TABLE

CSB

W/RB

ENB

MBB

CLKB

Data B (B0-B35) I/O

Port Function

H

L

X

L

X

L

X

L

X

↑

High-Impedance

Input

None

L

H

L

Input

FIFO2 write

Mail2write

L

H

L

↑

Input

H

X

↑

Output

None

H

L

FIFO1read

None

H

X

↑

H

Mail1 read (set MBF1 HIGH)

offsetvalues,thedevicewillignoredatalineA8.IfNon-InterspersedParityis ofCLKBafterthelastbitisloadedtoallownormalFIFO2operation. SeeFigure 6

selectedthendatalineA8willbecomeavalidbit.IfInterspersedParityisselected forSerialProgrammingoftheAlmost-FullFlagandAlmost-EmptyFlagOffset

serialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallelprogram- Values (IDT Standard and FWFT Modes) timing diagram.

ming can be done.

FIFO WRITE/READ OPERATION

— SERIAL LOAD

ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect

ToprogramtheX1,X2,Y1,andY2registersserially,initiateaMasterReset (CSA)andPortAWrite/Readselect(W/RA).TheA0-A35linesareintheHigh-

withFS2LOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGH impedance state wheneither CSA orW/RAis HIGH. The A0-A35lines are

transitionofMRS1andMRS2.Afterthisresetiscomplete,theXandYregister active outputs whenbothCSA andW/RAare LOW.

valuesareloadedbit-wisethroughtheFS0/SDinputoneachLOW-to-HIGH

Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH

transitionofCLKAthattheFS1/SENinputisLOW.Thereare44-,48-,or52- transitionofCLKAwhenCSAisLOW,W/RAisHIGH,ENAisHIGH,MBAis

bitwritesneededtocompletetheprogrammingfortheIDT72V3654,IDT72V3664, LOW,andFFA/IRAisHIGH.DataisreadfromFIFO2totheA0-A35outputs

or IDT72V3674, respectively. The four registers are written in the order Y1, by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW,

13

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)

Synchronized

to CLKB

Synchronized

to CLKA

Number of Words in FIFO Memory^(1,2)

(3)

IDT72V3654

IDT72V3664

IDT72V3674

EFB/ORB

AEB

AFA

FFA/IRA

0

1toX1

0

1toX1

0

1toX1

L

H

L

H

L

H

L

(X1+1)to[2,048-(Y1+1)]

(2,048-Y1)to2,047

2,048

(X1+1)to[4,096-(Y1+1)]

(4,096-Y1)to4,095

4,096

(X1+1)to[8,192-(Y1+1)]

(8,192-Y1)to8,191

8,192

H

L

NOTES:

1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read

operation necessary), it is not included in the FIFO memory count.

3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.

4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.

TABLE 5 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)

Synchronized

to CLKA

Synchronized

to CLKB

Number of Words in FIFO Memory^(1,2)

(3)

IDT72V3654

IDT72V3664

IDT72V3674

EFA/ORA

AEA

AFB

H

FFB/IRB

0

1toX2

0

L

H

L

H

L

1toX2

H

(X2+1)to[2,048-(Y2+1)]

(2,048-Y2)to2,047

2,048

(X2+1)to[4,096-(Y2+1)]

(4,096-Y2)to4,095

4,096

(X2+1)to[8,192-(Y2+1)]

(8,192-Y2)to8,191

8,192

H

L

NOTES:

1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read

operation necessary), it is not included in the FIFO memory count.

3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.

4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.

andarenotrelatedtohigh-impedancecontrolofthedataoutputs.Ifaportenable

isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay

changestates duringthesetupandholdtimewindowofthecycle.

WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,

thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe

LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.

WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput

registersonlywhenareadisselectedusingtheport’sChipSelect,Write/Read

select,Enable,andMailboxselect.

WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause

theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe

ReadClock. Thedatawordwillnotbeautomaticallysenttotheoutputregister.

Instead, data residing in the FIFO's memory array is clocked to the output

registeronlywhenareadisselectedusingtheport’sChipSelect,Write/Read

select,Enable,andMailboxselect.WriteandreadtimingdiagramsforPortA

canbefoundinFigure7and14. RelevantPortBwriteandreadcycle timing

diagrams togetherwithBus-MatchingandEndianselectoperations canbe

found in Figures 8 through 13.

ENA is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO

reads and writes on Port A are independent of any concurrent Port B

operation.

The Port B control signals are identical to those of Port A with the

exceptionthatthePortBWrite/Readselect(W/RB)istheinverseofthePort

A Write/Read select (W/RA). The state ofthe PortBdata (B0-B35)lines is

controlled by the Port B Chip Select (CSB) and Port B Write/Read select

(W/RB).TheB0-B35linesareinthehigh-impedancestatewheneitherCSB

isHIGHorW/RBisLOW.TheB0-B35linesareactiveoutputswhenCSBis

LOW and W/RB is HIGH.

Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH

transitionofCLKBwhenCSBisLOW,W/RBisLOW,ENBisHIGH,MBBis

LOW,andFFB/IRBisHIGH.DataisreadfromFIFO1totheB0-B35outputs

byaLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENB

isHIGH,MBBisLOW,andEFB/ORBisHIGH(seeTable3).FIFOreadsand

writes on Port B are independent of any concurrent Port A operation.

The setup and hold time constraints to the port clocks for the port Chip

SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations

14

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-

2.FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationis

readytobewrittentoinaminimumoftwocyclesoftheFull/InputReadyflag

synchronizingclock.Therefore,anFull/InputReadyflagisLOWiflessthan

twocyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsince

the nextmemorywrite locationhas beenread. The secondLOW-to-HIGH

transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets

the Full/InputReadyflagHIGH.

SYNCHRONIZED FIFO FLAGS

EachFIFOis synchronizedtoits portclockthroughatleasttwoflip-flop

stages.Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability

ofmetastableeventswhenCLKAandCLKBoperateasynchronouslytoone

another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.

EFB/ORB,AEB,FFB/IRB,andAFBaresynchronizedtoCLKB.Tables4and

5 show the relationship of each port flag to FIFO1 and FIFO2.

EMPTY/OUTPUTREADYFLAGS(EFA/ORA,EFB/ORB)

ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock

beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat

timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcycle

can be the first synchronization cycle (see Figures 19, 20, 21, and 22).

Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(ORA,

ORB)functionisselected.WhentheOutput-ReadyflagisHIGH,newdatais

presentintheFIFOoutputregister.WhentheOutputReadyflagisLOW,the

previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO

reads are ignored.

ALMOST-EMPTYFLAGS(AEA,AEB)

IntheIDTStandardmode,theEmptyFlag(EFA,EFB)functionisselected.

WhentheEmptyFlagisHIGH,dataisavailableintheFIFO’sRAMmemory

forreadingtotheoutputregister.WhentheEmptyFlagisLOW,theprevious

datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare

ignored.

TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock

thatreadsdatafromitsarray.ForboththeFWFTandIDTStandardmodes,

theFIFOreadpointeris incrementedeachtimeanewwordis clockedtoits

outputregister.ThestatemachinethatcontrolsanOutputReadyflagmonitors

a write pointer and read pointer comparator that indicates when the FIFO

memorystatusisempty,empty+1,orempty+2.

TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads

data from its array. The state machine that controls an Almost-Empty flag

monitorsawritepointerandreadpointercomparatorthatindicateswhenthe

FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.

Thealmost-emptystateisdefinedbythecontentsofregisterX1forAEBand

registerX2forAEA.Theseregistersareloadedwithpresetvaluesduringa

FIFOreset,programmedfromPortA,orprogrammedserially(seeAlmost-

Empty flag and Almost-Full flag offset programming section). An Almost-

EmptyflagisLOWwhenitsFIFOcontainsXorlesswordsandisHIGHwhen

itsFIFOcontains(X+1)ormorewords.AdatawordpresentintheFIFOoutput

registerhas beenreadfrommemory.

InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted

totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReady

flagsynchronizingclock. Therefore, anOutputReadyflagis LOWifa word

inmemoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles

oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime

thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntil

thethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simulta-

neouslyforcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFO

outputregister.

InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty

Flagwillindicatethepresenceofdataavailableforreadinginaminimumof

twocyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlag

isLOWifawordinmemoryisthenextdatatobesenttotheFlFOoutputregister

andtwocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsed

sincethetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOW

untilthesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,

forcing the Empty Flag HIGH; only then can data be read.

TwoLOW-to-HIGHtransitions ofthe Almost-Emptyflagsynchronizing

clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew

leveloffill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormore

wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed

sincethewritethatfilledthememorytothe(X+1)level.AnAlmost-Emptyflag

issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclock

after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH

transitionofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchro-

nizationcycleifitoccursattimet^SKEW2orgreaterafterthewritethatfillsthe

FIFOto(X+1)words.Otherwise,thesubsequentsynchronizingclockcycle

may be the first synchronization cycle. (See Figure 23 and 24).

ALMOST-FULL FLAGS (AFA, AFB)

TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites

datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitors

a write pointer and read pointer comparator that indicates when the FIFO

memorystatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate

isdefinedbythecontentsofregisterY1forAFAandregisterY2forAFB.These

registersareloadedwithpresetvaluesduringaFlFOreset,programmedfrom

PortA,orprogrammedserially(seeAlmost-EmptyflagandAlmost-Fullflag

offsetprogrammingsection).AnAlmost-FullflagisLOWwhenthenumberof

wordsinitsFIFOisgreaterthanorequalto(2,048-Y),(4,096-Y),or(8,192-Y)

fortheIDT72V3654,IDT72V3664,orIDT72V3674respectively.AnAlmost-

Fullflagis HIGHwhenthe numberofwords inits FIFOis less thanorequal

to [2,048-(Y+1)], [4,096-(Y+1)], or [8,192-(Y+1)] for the IDT72V3654,

IDT72V3664,orIDT72V3674respectively.Notethatadatawordpresentin

the FIFOoutputregisterhas beenreadfrommemory.

TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock

arerequiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewlevel

offill.Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-

(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave

notelapsedsince the readthatreducedthe numberofwords inmemoryto

[2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second

ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing

clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs

attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle

can be the first synchronization cycle (see Figures 15, 16, 17, and 18).

FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)

Thisisadualpurposeflag.InFWFTmode,theInputReady(IRAandIRB)

function is selected. In IDT Standard mode, the Full Flag (FFA and FFB)

functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis

HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory

locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites

to the FIFO are ignored.

TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat

writesdatatoitsarray.ForbothFWFTandIDTStandardmodes,eachtime

awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine

thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer

15

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

LOW-to-HIGHtransitionofits synchronizingclockafterthe FIFOreadthat BUS SIZING

reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. A

The Port B bus can be configured in a 36-bit long word, 18-bit word, or

LOW-to-HIGHtransitionofanAlmost-Fullflagsynchronizingclockbeginsthe 9-bit byte format for data read from FIFO1 or written to FIFO2. The levels

appliedtothePortBBusSizeselect(SIZE)andtheBus-Matchselect(BM)

determinethePortBbussize.TheselevelsshouldbestaticthroughoutFIFO

operation. Both bus size selections are implemented at the completion of

MasterReset,bythetimetheFull/InputReadyflagissetHIGH,asshownin

Figure 2.

firstsynchronizationcycleifitoccursattime tSKEW2 orgreateraftertheread

thatreducesthenumberofwordsinmemoryto[2,048/4,096/8,192-(Y+1)].

Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-

nization cycle (see Figure 25 and 26).

TwodifferentmethodsforsequencingdatatransferareavailableforPort

Bwhenthebussizeselectioniseitherbyte-orword-size.Theyarereferred

toasBig-Endian(mostsignificantbytefirst)andLittle-Endian(leastsignificant

bytefirst).ThelevelappliedtotheBig-Endianselect(BE)inputduringtheLOW-

to-HIGHtransitionofMRS1andMRS2selectstheendianmethodthatwillbe

active during FIFO operation. BE is a don’t care input when the bus size

selected for Port B is long word. The endian method is implemented at the

completionofMasterReset,bythetimetheFull/InputReadyflagissetHIGH,

as shown in Figure 2.

Only36-bitlongworddataiswrittentoorreadfromthetwoFIFOmemories

ontheIDT72V3654/72V3664/72V3674.Bus-matchingoperationsaredone

afterdataisreadfromtheFIFO1RAMandbeforedataiswrittentotheFIFO2

RAM. These bus-matching operations are not available when transferring

data via mailbox registers. Furthermore, both the word- and byte-size bus

selections limit the width of the data bus that can be used for mail register

operations.Inthiscase,onlythosebytelanesbelongingtotheselectedword-

orbyte-sizebus cancarrymailboxdata.Theremainingdataoutputs willbe

indeterminate. The remaining data inputs will be don’t care inputs. For

example, when a word-size bus is selected, then mailbox data can be

transmitted only between A0-A17 and B0-B17. When a byte-size bus is

selected,thenmailboxdatacanbetransmittedonlybetweenA0-A8andB0-

B8. (See Figures 27 and 28).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command and control

informationbetweenPortAandPortBwithoutputtingitinqueue.TheMailbox

select(MBA, MBB)inputs choose betweena mailregisteranda FIFOfora

port data transfer operation. The usable width of both the Mail1 and Mail2

registersmatchestheselectedbussizeforPortB.

ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen

a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the

selectedPortBbussizeisalso36bits,thentheusablewidthoftheMail1register

employsdatalinesA0-A35.IftheselectedPortBbussizeis18bits,thenthe

usablewidthoftheMail1RegisteremploysdatalinesA0-A17.(Inthiscase,

A18-A35aredon’tcareinputs.)IftheselectedPortBbus sizeis 9bits,then

theusablewidthoftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,

A9-A35 are don’t care inputs.)

A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2

RegisterwhenaPortBwriteisselectedbyCSB,W/RB,andENBwithMBB

HIGH.IftheselectedPortBbus sizeis also36bits,thentheusablewidthof

theMail2employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits,

thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthis

case,B18-B35aredon’tcareinputs.)IftheselectedPortBbussizeis9bits,

thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B8.(Inthis

case, B9-B35are don’tcare inputs.)

Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)

LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.

Whendataoutputsofaportareactive,thedataonthebuscomesfromthe

FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthe

mailregisterwhenthe portMailboxselectinputis HIGH.

TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition

onCLKBwhenaPortBreadisselectedbyCSB,W/RB,andENBwithMBB

HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.

Foran18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.(Inthis

case,B18-B35areindeterminate.)Fora9-bitbussize,9bitsofmailboxdata

are placed on B0-B8. (In this case, B9-B35 are indeterminate.)

TheMail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransition

onCLKAwhenaPortAreadisselectedbyCSA,W/RA,andENAwithMBA

HIGH.

Fora 36-bitbus size, 36bits ofmailboxdata are placedonA0-A35. For

an18-bitbussize,18bitsofmailboxdataareplacedonA0-A17.(Inthiscase,

A18-A35are indeterminate.)Fora 9-bitbus size, 9bits ofmailboxdata are

placedonA0-A8. (Inthis case, A9-A35are indeterminate.)

Thedatainamailregisterremainsintactafteritisreadandchangesonly

whennewdataiswrittentotheregister.TheEndianselectfeaturehasnoeffect

onmailboxdata.FormailregisterandMailRegisterFlagtimingdiagrams,see

Figure 27 and 28.

BUS-MATCHING FIFO1 READS

DataisreadfromtheFIFO1RAMin36-bitlongwordincrements.Ifalong

wordbus sizeis implemented,theentirelongwordimmediatelyshifts tothe

FIFO1outputregister.IfbyteorwordsizeisimplementedonPortB,onlythe

firstoneortwobytesappearontheselectedportionoftheFIFO1outputregister,

with the rest of the long word stored in auxiliary registers. In this case,

subsequentFIFO1readsoutputtherestofthelongwordtotheFIFO1output

register in the order shown by Figure 2.

WhenreadingdatafromFIFO1inbyteorwordformat,theunusedB0-B35

outputsareindeterminate.

BUS-MATCHING FIFO2 WRITES

DataiswrittentotheFIFO2RAMin36-bitlongwordincrements.Datawritten

toFIFO2withabyteorwordbussizestorestheinitialbytesorwordsinauxiliary

registers.TheCLKBrisingedgethatwritesthefourthbyteorthesecondword

oflongwordtoFIFO2alsostorestheentirelongwordintheFIFO2memory.

The bytes are arranged in the manner shown in Figure 2.

WhenwritingdatatoFIFO2inbyteorwordformat,theunusedB0-B35inputs

aredon'tcareinputs.

16

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

A35  A27

A26  A18

A17  A9

A8  A0

BYTE ORDER ON PORT A:

Write to FIFO1/

Read from FIFO2

D

A

B

C

B35  B27

B26  B18

B17  9

B8  B0

BYTE ORDER ON PORT B:

BE BM SIZE

Read from FIFO1/

Write to FIFO2

A

B

D

C

X

L

X

(a) LONG WORD SIZE

B35  B27

B26  B18

B17  B9

B8  B0

1st: Read from FIFO1/

Write to FIFO2

BE BM SIZE

A

B

H

L

B17  B9

B8  B0

2nd: Read from FIFO1/

Write to FIFO2

C

D

(b) WORD SIZE  BIG ENDIAN

B35  B27

B26  B18

B17  B9

B8  B0

1st: Read from FIFO1/

Write to FIFO2

BE BM SIZE

C

D

L

H

L

B26  B18

B17  B9

B8  B0

2nd: Read from FIFO1/

Write to FIFO2

A

B

(c) WORD SIZE  LITTLE-ENDIAN

B35  B27

B26  B18

B17  B9

B8  B0

BE BM SIZE

1st: Read from FIFO1/

Write to FIFO2

A

H

B8  B0

2nd: Read from FIFO1/

Write to FIFO2

B

B8  B0

3rd: Read from FIFO1/

Write to FIFO2

C

B8  B0

4th: Read from FIFO1/

Write to FIFO2

D

(d) BYTE SIZE  BIG-ENDIAN

B35  B27

B26  B18

B17  B9

B8  B0

BE BM SIZE

1st: Read from FIFO1/

Write to FIFO2

D

L

H

B8  B0

2nd: Read from FIFO1/

Write to FIFO2

C

B8  B0

3rd: Read from FIFO1/

Write to FIFO2

B

B8  B0

4th: Read from FIFO1/

Write to FIFO2

A

4664 drw 04

(e) BYTE SIZE  LITTLE-ENDIAN

Figure 2. Bus Sizing

17

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

CLKA

CLKB

t

RSTS

tRSTH

MRS1

tBEH

t

BES

tFWS

BE

0,1

BE/FWFT

FWFT

t

FSS

tFSH

FS2,

FS1,FS0

t

WFF

t

WFF

FFA/IRA

EFB/ORB

AEB

(3)

REF

t

RSF

t

RSF

AFA

t

RSF

MBF1

LOW

RTM

4664 drw 05

NOTES:

1. FIFO2 Master Reset (MRS2) is performed in the same manner to load X2 and Y2 with a preset value. For FIFO2 Master Reset, MRS1 must toggle simultaneously with MRS2.

2. PRS1 must be HIGH during Master Reset.

3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.

Figure 3. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight⁽¹⁾(IDT Standard and FWFT Modes)

CLKA

CLKB

t

RSTS

tRSTH

PRS1

t

WFF

t

WFF

FFA/IRA

(3)

tREF

EFB/ORB

t

RSF

AEB

AFA

t

RSF

t

RSF

MBF1

RTM

LOW

4664 drw 06

NOTES:

1. Partial Reset is performed in the same manner for FIFO2.

2. MRS1 must be HIGH during Partial Reset.

3. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.

Figure 4. FIFO1 Partial Reset⁽¹⁾(IDT Standard and FWFT Modes)

18

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

CLKA

2

1

4

MRS1,

MRS2

t

FSS

t

FSH

FS2

FS1,FS0

FFA/IRA

t

FSS

t

FSH

0,0

t

WFF

(1)

tSKEW1

tENS2

tENH

ENA

tDH

tDS

A0-A35

AEB Offset

AFA Offset

AFB Offset

(Y 2)

AEA Offset

(X 2)

First Word to FIFO1

(X1)

(Y1)

CLKB

1

2

t

WFF

FFB/IRB

4664 drw 07

NOTES:

1. t^SKEW1is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising

edge of CLKB is less than t^SKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.

2. CSA=LOW, W/RA=HIGH,MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.

Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)

CLKA

4

MRS1,

MRS2

t

FSS

tFSH

FS2

t

WFF

(1)

tSKEW

FFA/IRA

t

SENS

t

FSS

t

SENH

SDH

t

SENS

t

SENH

tSPH

FS1/SEN

tSDS

t

tSDH

tSDS

FS0/SD⁽³⁾

AFA Offset (Y1) MSB

AEA Offset (X2) LSB

CLKB

4

t

WFF

4664 drw 08

FFB/IRB

NOTES:

1. t^SKEW1is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising

edge of CLKB is less than t^SKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.

2. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA and FFB/IRB is set HIGH.

3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).

Figure 6. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (IDT Standard and FWFT Modes)

19

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

tCLK

tCLKH

tCLKL

CLKA

FFA/IRA HIGH

t

ENH

t

ENS1

CSA

t

ENS1

t

W/RA

t

ENS2

t

ENH

MBA

ENA

tENS2

tENH

tENS2

tENH

t

tDS

tDH

W1⁽¹⁾

W2⁽¹⁾

A0 - A35

No Operation

4664 drw09

NOTE:

1. Written to FIFO1.

Figure 7. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)

tCLK

tCLKH

tCLKL

CLKB

FFB/IRB HIGH

tENH

tENS1

CSB

tENH

tENS1

W/RB

tENH

tENS2

MBB

tENH

tENS2

ENB

tDH

t

DS

W1⁽¹⁾

W2⁽¹⁾

No Operation

B0-B35

4664 drw 10

NOTE:

1. Written to FIFO2.

DATA SIZE TABLE FOR LONG-WORD WRITES TO FIFO2

SIZE MODE⁽¹⁾

SIZE

DATA WRITTEN TO FIFO2

DATA READ FROM FIFO2

BM

BE

B35-B27

B26-B18

B17-B9

B8-B0

A35-A27

A26-A18

A17-A9

A8-A0

L

X

A

B

C

D

A

B

C

D

NOTE:

1. BE is selected at Master Reset: BM and SIZE must be static throughout device operation.

Figure 8. Port B Long-Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)

20

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

CLKB

FFB/IRB HIGH

tENH

t

ENS1

CSB

t

W/RB

t

ENH

t

ENH

t

ENS2

t

ENS2

MBB

t

ENH

t

ENH

t

ENS2

t

ENB

tDH

tDS

B0-B17

4664 drw 11

DATA SIZE TABLE FOR WORD WRITES TO FIFO2

SIZE MODE⁽¹⁾

WRITE

NO.

DATA WRITTEN

TO FIFO2

DATA READ FROM FIFO2

BM

SIZE

BE

B17-B9

B8-B0

A35-A27

A26-A18

A17-A9

A8-A0

1

2

1

2

A

C

A

B

D

B

H

L

H

A

B

C

D

H

L

B

C

D

NOTE:

1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

Figure 9. Port B Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)

CLKB

FFB/IRB HIGH

tENH

t

ENS1

CSB

t

W/RB

MBB

t

ENH

tENH

t

ENS2

t

tENH

tENS2

tENH

ENB

tDS

tDH

B0-B8

4664 drw 12

DATA SIZE TABLE FOR BYTE WRITES TO FIFO2

SIZE MODE⁽¹⁾

WRITE

NO.

DATA WRITTEN

TO FIFO2

DATA READ FROM FIFO2

BM

SIZE

BE

B8-B0

A35-A27

A26-A18

A17-A9

A8-A0

1

2

3

4

1

2

3

4

A

B

C

D

C

B

A

H

A

B

C

D

H

L

A

B

C

D

NOTE:

1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

Figure 10. Port B Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)

21

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

tCLK

tCLKH

tCLKL

CLKB

EFB/ORB

HIGH

CSB

W/RB

MBB

tENH

tENS2

ENB

t

MDV

No Operation

W2⁽¹⁾

tDIS

t

A

t

A

t

EN

W1⁽¹⁾

W2⁽¹⁾

Previous Data

B0-B35

(Standard Mode)

t

MDV

tDIS

tA

t

A

OR

tEN

W3⁽¹⁾

W1⁽¹⁾

B0-B35

(FWFT Mode)

4664 drw 13

NOTE:

1. Read From FIFO1.

DATA SIZE TABLE FOR FIFO LONG-WORD READS FROM FIFO1

SIZE MODE⁽¹⁾

SIZE

DATA WRITTEN TO FIFO1

DATA READ FROM FIFO1

BM

BE

A35-A27

A26-A18

A17-A9

A8-A0

B35-B27

B26-B18

B17-B9

B8-B0

L

X

A

B

C

D

A

B

C

D

NOTE:

1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .

Figure 11. Port B Long-Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)

CLKB

HIGH

EFB/ORB

CSB

W/RB

MBB

ENB

t

ENS2

tENH

No Operation

t

MDV

tDIS

t

A

tA

t

EN

B0-B17

Previous Data

(Standard Mode)

tDIS

t

MDV

OR

t

A

tA

t

EN

B0-B17

(FWFT Mode)

4664 drw 14

NOTE:

1. Unused word B18-B35 are indeterminate for word-size reads.

DATA SIZE TABLE FOR WORD READS FROM FIFO1

SIZE MODE⁽¹⁾

DATA WRITTEN TO FIFO1

READ

NO.

DATA READ FROM FIFO1

BM

SIZE

BE

A35-A27

A26-A18

A17-A9

A8-A0

B17-B9

B8-B0

H

L

H

A

B

C

D

1

2

1

2

A

C

A

B

D

B

H

L

A

B

C

D

NOTE:

1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation .

Figure 12. Port-B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)

22

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

CLKB

EFB/ORB HIGH

CSB

W/RB

MBB

tENS2

tENH

ENB

No Operation

t

DIS

t

MDV

t

A

t

A

t

A

t

A

t

EN

B0-B8

Previous Data

(Standard Mode)

t

MDV

t

OR

t

A

tA

t

A

t

EN

B0-B8

(FWFT Mode)

4664 drw 15

NOTE:

1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate for byte-size reads.

DATA SIZE TABLE FOR BYTE READS FROM FIFO1

SIZE MODE⁽¹⁾

DATA WRITTEN TO FIFO1

READ

NO.

DATA READ FROM FIFO1

B8-B0

BM

SIZE

BE

A35-A27

A26-A18

A17-A9

A8-A0

1

2

3

4

1

2

3

4

A

B

C

D

C

B

A

H

A

B

C

D

H

L

A

B

C

D

NOTE:

1. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.

Figure 13. Port-B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)

tCLK

tCLKL

tCLKH

CLKA

EFA/ORA HIGH

CSA

W/RA

MBA

tENH

tENS2

ENA

No Operation

W2⁽¹⁾

t

MDV

t

DIS

t

A

t

A

t

EN

A0-A35

Previous Data

W1⁽¹⁾

W2⁽¹⁾

(Standard Mode)

t

MDV

t

tA

t

A

OR

t

EN

A0-A35

W3⁽¹⁾

(1)

W1

(FWFT Mode)

4664 drw16

NOTE:

1. Read From FIFO2.

Figure 14. Port-A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)

23

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

tCLK

tCLKH

tCLKL

CLKA

CSA

LOW

WRA HIGH

t

ENS2

t

ENH

MBA

t

ENH

ENA

IRA HIGH

tDS

tDH

A0-A35

W1

t

^CLKtCLKL

(1)

tCLKH

tSKEW1

CLKB

ORB

1

2

3

t

REF

tREF

FIFO1 Empty

CSB LOW

W/RB HIGH

LOW

MBB

tENS2

tENH

ENB

tA

Old Data in FIFO1 Output Register

W1

B0-B35

4664 drw17

NOTES:

1. t^SKEW1is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.

If the time between the rising CLKA edge and rising CLKB edge is less than t^SKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB

cycle later than shown.

2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.

Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)

24

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

t

CLK

t

CLKL

t

CLKH

CLKA

CSA

LOW

HIGH

WRA

t

ENS2

t

ENH

MBA

t

tENS2

ENA

FFA

HIGH

tDS

tDH

A0-A35

W1

t

CLK

(1)

SKEW1

t

CLKH

t

tCLKL

CLKB

1

2

t

REF

t

REF

FIFO1 Empty

LOW

EFB

CSB

W/RB HIGH

LOW

MBB

tENH

tENS2

ENB

tA

W1

B0-B35

4664 drw18

NOTES:

1. t^SKEW1is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than t^SKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively.

Figure 16. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)

25

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

tCLK

tCLKH

tCLKL

CLKB

CSB

LOW

W/RB

tENS2

tENH

MBB

ENB

tENH

tENS2

IRB

HIGH

tDH

tDS

B0-B35

W1

t

CLK

(1)

SKEW1

tCLKH

t

CLKL

t

1

2

CLKA

ORA

3

t

REF

tREF

FIFO2 Empty

CSA

LOW

W/RA

LOW

MBA

ENA

tENS2

tENH

tA

Old Data in FIFO2 Output Register

W1

A0-A35

4664 drw19

NOTES:

1. t^SKEW1is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.

If the time between the CLKB edge and the rising CLKA edge is less than t^SKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA

cycle later than shown.

2. If Port B size is word or byte, t^SKEW1is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)

26

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

t

CLK

t

CLKL

t

CLKH

CLKB

CSB LOW

LOW

W/RB

tENS2

tENH

MBB

ENB

tENS2

tENH

FFB HIGH

B0-B35

tDH

tDS

W1

(1)

t

CLK

tSKEW1

t

CLKH

t

CLKL

1

2

CLKA

t

REF

t

REF

EFA

FIFO2 Empty

LOW

CSA

W/RA

MBA

tENS2

tENH

ENA

tA

W1

A0-A35

4664 drw20

NOTES:

1. t^SKEW1is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than t^SKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

2. If Port B size is word or byte, t^SKEW1is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

Figure 18. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)

27

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

tCLK

tCLKH

tCLKL

CLKB

CSB

LOW

W/RB

HIGH

LOW

MBB

tENS2

tENH

ENB

ORB

HIGH

tA

Previous Word in FIFO1 Output Register

Next Word From FIFO1

B0-B35

(1)

tCLK

tSKEW1

tCLKH

tCLKL

1

2

CLKA

t

WFF

t

WFF

FIFO1 Full

LOW

IRA

CSA

HIGH

W/RA

tENH

tENS2

MBA

tENS2

tENH

ENA

tDS

tDH

Write

A0-A35

4664 drw21

To FIFO1

NOTES:

1. t^SKEW1is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising

CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.

2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.

Figure 19. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)

tCLK

tCLKH

tCLKL

CLKB

LOW

CSB

W/RB

MBB

HIGH

LOW

tENS2

tENH

ENB

HIGH

EFB

tA

Previous Word in FIFO1 Output Register

Next Word From FIFO1

B0-B35

(1)

t

^CLKtCLKL

tSKEW1

tCLKH

CLKA

1

2

t

WFF

t

WFF

FFA

FIFO1 Full

CSA LOW

W/RA HIGH

t

ENH

t

ENS2

MBA

t

tENH

ENA

tDH

tDS

Write

A0-A35

4664 drw22

To FIFO1

NOTES:

1. t^SKEW1is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the

rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.

2. If Port B size is word or byte, t^SKEW1is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.

Figure 20. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)

28

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

tCLK

tCLKH

tCLKL

CLKA

CSA

LOW

W/RA

LOW

MBA

tENS2

tENH

ENA

ORA

HIGH

tA

Previous Word in FIFO2 Output Register

SKEW1

Next Word From FIFO2

A0-A35

(1)

tCLK

t

tCLKH

tCLKL

1

2

CLKB

t

WFF

t

WFF

IRB

CSB

FIFO2 FULL

LOW

W/RB

LOW

tENS2

tENH

MBB

ENB

tENS2

tENH

tDS

tDH

Write

B0-B35

4664 drw23

To FIFO2

NOTES:

1. t^SKEW1is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than t^SKEW1, then IRB may transition HIGH one CLKB cycle later than shown.

2. If Port B size is word or byte, IRB is set LOW by the last word or byte write of the long word, respectively.

Figure 21. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)

29

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

tCLK

tCLKH

tCLKL

CLKA

LOW

CSA

W/RA

MBA

tENS2

tENH

ENA

EFA

HIGH

tA

Previous Word in FIFO2 Output Register

Next Word From FIFO2

A0-A35

(1)

tCLK

tSKEW1

tCLKH

tCLKL

CLKB

1

2

t

WFF

t

WFF

FIFO2 Full

LOW

FFB

CSB

LOW

W/RB

t

ENS2

t

ENH

MBB

ENB

t

ENH

tDS

tDH

Write

B0-B35

4664 drw24

To FIFO2

NOTES:

1. t^SKEW1is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than t^SKEW1, then FFB may transition HIGH one CLKB cycle later than shown.

2. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.

Figure 22. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)

30

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

CLKA

tENS2

tENH

ENA

(1)

tSKEW2

1

2

CLKB

t

PAE

t

PAE

X1 Words in FIFO1

AEB

(X1+1) Words in FIFO1

ENS2

t

ENH

ENB

4664 drw 25

NOTES:

1. t^SKEW2is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than t^SKEW2, then AEB may transition HIGH one CLKB cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.

3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.

Figure 23. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)

CLKB

tENS2

tENH

ENB

(1)

tSKEW2

1

2

CLKA

t

PAE

t

PAE

AEA

X2 Words in FIFO2

(X2+1) Words in FIFO2

ENS2

t

tENH

ENA

4664 drw 26

NOTES:

1. t^SKEW2is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than t^SKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.

3. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

Figure 24. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)

(1)

tSKEW2

1

2

CLKA

ENA

tENH

tENS2

t

PAF

t

PAF

(D-Y1) Words in FIFO1

[D-(Y1+1)] Words in FIFO1

AFA

CLKB

tENS2

tENH

ENB

4664 drw 27

NOTES:

1. t^SKEW2is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than t^SKEW2, then AFA may transition HIGH one CLKA cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.

3. D = Maximum FIFO Depth = 2,048 for the IDT72V3654, 4,096 for the IDT72V3664, 8,192 for the IDT72V3674.

4. If Port B size is word or byte, t^SKEW2is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.

Figure 25. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)

31

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

(1)

tSKEW2

1

2

CLKB

ENB

tENH

tENS2

t

PAF

t

PAF

(D-Y2) Words in FIFO2

AFB

[D-(Y2+1)] Words in FIFO2

CLKA

tENH

tENS2

ENA

4664 drw 28

NOTES:

1. t^SKEW2is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than t^SKEW2, then AFB may transition HIGH one CLKB cycle later than shown.

2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.

3. D = Maximum FIFO Depth = 2,048 for the IDT72V3654, 4,096 for the IDT72V3664, 8,192 for the IDT72V3674.

4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.

Figure 26. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)

CLKA

t

ENH

t

ENS1

CSA

t

ENS1

W/RA

tENH

tENS2

MBA

tENH

tENS2

ENA

tDH

tDS

W1

A0-A35

CLKB

t

PMF

t

PMF

MBF1

CSB

W/RB

MBB

ENB

tENH

tENS2

t

PMR

tEN

t

MDV

tDIS

FIFO1 Output Register

W1 (Remains valid in Mail1 Register after read)

B0-B35

4664 drw29

NOTE:

1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35

will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will

have valid data (B9-B35 will be indeterminate).

Figure 27. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)

32

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

CLKB

tENH

tENS1

CSB

W/RB

MBB

ENB

t

ENH

t

ENS1

t

ENH

t

ENS2

t

ENH

t

DH

tDS

W1

B0-B35

CLKA

t

PMF

tPMF

MBF2

CSA

W/RA

MBA

ENA

tENH

tENS2

t

PMR

tEN

tDIS

t

MDV

A0-A35

W1 (Remains valid in Mail 2 Register after read)

FIFO2 Output Register

4664 drw30

NOTE:

1. If Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don’t care inputs). In this first case A0-A17 will have valid data

(A18-A35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-B8 (B9-B35 are don’t care inputs). In this second

case, A0-A8 will have valid data (A9-A35 will be indeterminate).

Figure 28. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)

33

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

CLKA

CLKB

4

1

2

3

2

3

4

1

tENS2

tENH

ENB

RT1

RTM

EFB

t

RSTS

t

RSTH

t

RTMS

t

RTMH

(2)

REF

(2)

tREF

t

tA

B0-Bn

Wx

W1

4664 drw31

NOTES:

1. CSB = LOW

2. Retransmit setup is complete after EFB returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.

4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit

setup procedure. D = 2,048, 4,096 and 8,192 for the IDT72V3654, IDT72V3664 and IDT72V3674 respectively.

Figure 29. Retransmit Timing for FIFO1 (IDT Standard Mode)

CLKB

CLKA

4

1

2

3

2

3

4

1

tENS2

tENH

ENA

RT2

RTM

t

RSTS

t

RSTH

t

RTMS

t

RTMH

(2)

REF

(2)

REF

t

EFA

A0-An

NOTES:

tA

Wx

W1

4664 drw32

1. CSA = LOW

2. Retransmit setup is complete after EFA returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO1 after Master Reset on FIFO2.

4. No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, FFB will be LOW throughout the Retransmit

setup procedure. D = 2,048, 4,096 and 8,192 for the IDT72V3654, IDT72V3664 and IDT72V3674 respectively.

Figure 30. Retransmit Timing for FIFO2 (IDT Standard Mode)

34

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

CLKA

CLKB

4

1

2

3

2

3

4

1

LOW

ENB

RT1

t

RSTS

tRSTH

t

RTMS

t

RTMH

RTM

ORB

(2)

REF

(2)

REF

t

tA

B0-Bn

Wx

W1

4664 drw33

NOTES:

1. CSB = LOW

2. Retransmit setup is complete after ORB returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.

4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, IRA will be LOW throughout the Retransmit

setup procedure. D = 2,049, 4,097 and 8,193 for the IDT72V3654, IDT72V3664 and IDT72V3674 respectively.

Figure 31. Retransmit Timing for FIFO1 (FWFT Mode)

CLKB

CLKA

4

1

2

3

2

3

4

1

LOW

RSTS

ENA

RT2

t

tRSTH

t

RTMS

t

RTMH

RTM

ORA

(2)

REF

(2)

REF

t

tA

A0-An

Wx

W1

4664 drw34

NOTES:

1. CSA = LOW

2. Retransmit setup is complete after ORA returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO2 after Master Reset on FIFO2.

4. No more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRB will be LOW throughout the Retransmit

setup procedure. D = 2,049, 4,097 and 8,193 for the IDT72V3654, IDT72V3664 and IDT72V3674 respectively.

Figure 32. Retransmit Timing for FIFO2 (FWFT Mode)

35

IDT72V3654/72V3664/72V36743.3VCMOSSyncBiFIFO^TMWITHBUS-MATCHING

2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2

COMMERCIALTEMPERATURERANGE

PARAMETER MEASUREMENT INFORMATION

3.3V

330

Ω

From Output

Under Test

30 pF ⁽¹⁾

510 Ω

PROPAGATION DELAY

LOAD CIRCUIT

3 V

Timing

Input

1.5 V

High-Level

1.5 V

Input

GND

1.5 V

GND

3 V

t

S

th

tW

3 V

Data,

Enable

Input

1.5 V

Low-Level

1.5 V

GND

Input

GND

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

3 V

Output

Enable

1.5 V

t

PZL

GND

tPLZ

3 V

≈3 V

Input

1.5 V

Low-Level

Output

GND

V

OL

tPD

t

PZH

tPD

V

OH

V

OH

≈O V

In-Phase

Output

1.5 V

High-Level

Output

1.5 V

V

t

PHZ

OL

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

4664 drw 35

NOTE:

1. Includes probe and jig capacitance.

Figure 33. Output Load and AC Test Conditions

36

ORDERING INFORMATION

IDT

X

XX

X

XXXXXX

Device Type Power

Speed

Package

Process/

Temperature

Range

Commercial (0°C to +70°C)

BLANK

PF

Thin Quad Flat Pack (TQFP, PK128-1)

Clock Cycle Time (tCLK

)

10

15

Commercial Only

Low Power

Speed in Nanoseconds

L

72V3654 2,048 x 36 x 2  3.3V SyncBiFIFO with Bus-Matching

72V3664

72V3674

4,096 x 36 x 2  3.3V SyncBiFIFO with Bus-Matching

8,192 x 36 x 2  3.3V SyncBiFIFO with Bus-Matching

4664 drw36

NOTE:

1. Industrial temperature range is available by special order.

DATASHEETDOCUMENTHISTORY

06/13/2000

09/25/2000

12/22/2000

02/08/2001

03/21/2001

11/03/2003

pgs. 1-3, 5, 6, 8-10, 12-14, 16, 19, 20, 23-33, and 37.

pgs. 7, 9, 10 and 37.

pgs. 4, 5 and 13.

pgs. 5 and 12.

pgs. 7 and 8.

pg. 1.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

408-360-1753

email:FIFOhelp@idt.com

www.idt.com

37


型号：	IDT72V3664L10PF9
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FIFO, 4KX36, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128 先进先出芯片
文件：	总37页 (文件大小：409K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT72V3664L10PF9 [IDT]

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