IDT72V3672L15PQF9 [IDT]
FIFO, 8KX36, 10ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132;
| 型号： | IDT72V3672L15PQF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 8KX36, 10ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132 先进先出芯片 存储 |
| 文件： | 总29页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncBiFIFOTM
2,048 x 36 x 2
4,096 x 36 x 2
IDT72V3652
IDT72V3662
IDT72V3672
8,192 x 36 x 2
• Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
• Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving
120-pin Thin Quad Flatpack (TQFP)
• Pin and functionally compatible versions of the 5V operating
IDT723652/723662/723672
• Pin compatible to the lower density parts, IDT72V3622/72V3632/
72V3642
FEATURES
• Memory storage capacity:
IDT72V3652
IDT72V3662
IDT72V3672
–
–
–
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
• Supports clock frequencies up to 100MHz
• Fast access times of 6.5ns
• Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
• Industrial temperature range (–40°C to +85°C) is available
• Two independent clocked FIFOs buffering data in opposite direc-
tions
DESCRIPTION
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
• FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
TheIDT72V3652/72V3662/72V3672arepinand functionallycompatible
versionsoftheIDT723652/723662/723672,designedtorunoffa3.3Vsupply
forexceptionallylow-powerconsumption. Thesedevicesaremonolithic,high-
speed,low-power,CMOSBidirectionalSyncFIFO(clocked)memorieswhich
supportclockfrequenciesupto100MHzandhavereadaccesstimesasfast
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
Port-A
Control
Logic
W/RA
RAM
ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
ENA
MBA
36
FIFO1,
Mail1
Reset
Logic
RST1
Write
Pointer
Read
Pointer
36
Status Flag
Logic
EFB/ORB
AEB
FFA/IRA
AFA
FIFO 1
FS
0
1
Programmable Flag
Offset Registers
Timing
Mode
FWFT
FS
A
0
- A35
13
B0 - B35
FIFO 2
Status Flag
EFA/ORA
FFB/IRB
AFB
Logic
AEA
36
Read
Pointer
Write
Pointer
36
FIFO2,
Mail2
Reset
Logic
RST2
RAM
ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
CLKB
CSB
Port-B
Control
Logic
W/RB
ENB
Mail 2
Register
MBB
4660 drw01
MBF2
IDTandtheIDTlogoareregisteredtrademarkofIntegratedDeviceTechnology,Inc. SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
NOVEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4660/3
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray.A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word(36-bitwide)writtentoanemptyFIFOappearsautomaticallyonthe
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the FWFT pin
duringFIFOoperationdetermines themodeinuse.
EachFIFOhas acombinedEmpty/OutputReadyFlag(EFA/ORAand
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/
IRB). The EF and FF functions are selected in the IDT Standard mode. EF
indicates whether or not the FIFO memory is empty. FF shows whether the
DESCRIPTION(CONTINUED)
as 6.5ns.Twoindependent2,048/4,096/8,192x36dual-portSRAMFIFOs
onboardeachchipbufferdatainoppositedirections.Communicationbetween
eachportmaybypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailbox
register has a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
PIN CONFIGURATION
NC
35
34
33
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
B
B
B
A
35
34
33
32
CC
31
30
GND
29
28
27
26
25
24
23
FWFT
22
CC
21
20
19
18
GND
17
16
15
14
13
CC
12
NC
A
A
A
V
A
A
B
32
GND
B
31
30
29
28
27
26
CC
25
24
GND
23
22
21
20
19
18
GND
17
16
CC
15
14
13
12
B
B
B
B
A
A
A
A
B
V
B
B
A
A
A
B
B
B
B
A
V
A
B
B
A
A
A
B
B
V
B
A
A
A
A
90
89
88
87
86
85
84
B
B
B
GND
NC
A
V
A
NC
7
5
4660 drw02
*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
NOTES:
1. NC – no internal connection
2. Uses Yamaichi socket IC51-1324-828
PQFP(2) (PQ132-1, order code: PQF)
TOP VIEW
2
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
thresholdcanbesetat8,16or64locationsfromtheemptyboundaryandthe
AFAandAFBthresholdcanbesetat8,16or64locationsfromthefullboundary.
Allthese choices are made usingthe FS0andFS1inputs duringReset.
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
TheIDT72V3652/72V3662/72V3672arecharacterizedforoperationfrom
0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by
specialorder.TheyarefabricatedusingIDT’shighspeed,submicronCMOS
technology.
memoryis fullornot.TheIRandORfunctions areselectedintheFirstWord
FallThroughmode.IRindicateswhetherornottheFIFOhasavailablememory
locations.ORshowswhethertheFIFOhasdataavailableforreadingornot.
Itmarksthepresenceofvaliddataontheoutputs.
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and
a programmable Almost-Full flag (AFA and AFB). AEA and AEB indicate
whenaselectednumberofwordsremainintheFIFOmemory. AFAandAFB
indicatewhentheFIFOcontainsmorethanaselectednumberofwords.
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the
portclockthatwritesdataintoitsarray.EFA/ORA,EFB/ORB,AEAandAEB
are two-stage synchronized to the port clock that reads data from its array.
Programmable offsets for AEA, AEB, AFA and AFB are loaded by using
Port A. Three default offset settings are also provided. The AEA and AEB
PINCONFIGURATION(CONTINUED)
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B
B
B
B
35
34
33
32
A
A
A
A
V
A
A
GND
35
34
33
32
CC
31
30
1
2
3
4
5
6
7
8
GND
B
B
B
B
B
B
V
B
31
30
29
28
27
26
CC
25
24
A
29
28
27
26
25
24
23
9
A
A
A
A
A
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
GND
B
23
22
21
20
19
18
FWFT
B
B
B
B
A
22
CC
21
20
19
18
V
A
A
B
A
GND
A
B
B
V
B
B
B
B
17
16
CC
15
14
13
12
GND
A
17
16
15
14
13
CC
12
A
A
A
A
V
GND
A
4660 drw03
TQFP (PN120-1, order code: PF)
TOP VIEW
3
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
PortAData
I/0
O
36-bitbidirectionaldataportforsideA.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwordsinFIFO2is
AEA
PortAAlmost-
EmptyFlag
(Port A) lessthanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberof words in FIFO1 is
(Port B) lessthanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty locationsin
(Port A) FIFO1is less thanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofempty locationsin
(Port B) FIFO2is less thanorequaltothevalueintheAlmost-FullBOffsetregister,Y2.
AEB
AFA
AFB
PortBAlmost-
EmptyFlag
O
PortAAlmost-
Full Flag
O
PortBAlmost-
Full Flag
O
B0 - B35
CLKA
PortBData
I/O
I
36-bitbidirectionaldataportforsideB.
PortAClock
CLKAis a continuous clockthatsynchronizes alldata transfers throughportAandcanbe asynchronous or
coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKB
PortBClock
I
CLKBisacontinuousclockthatsynchronizesalldatatransfersthroughportBand can be asynchronous or
coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH
transitionofCLKB.
CSA
Port A Chip
Select
I
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35
outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onportB. The
B0- B35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA
PortAEmpty/
OutputReady
Flag
O
This is adualfunctionpin. IntheIDTStandardmode,theEFA functionis selected.EFAindicates
whetherornotthe FIFO2memoryis empty. Inthe FWFTmode, the ORAfunctionis selected. ORA
indicates thepresenceofvaliddataonA0-A35outputs,availableforreading.EFA/ORAis synchronized
totheLOW-to-HIGHtransitionofCLKA.
EFB/ORB
PortBEmpty/
OutputReady
Flag
O
This is adualfunctionpin. IntheIDTStandardmode,theEFB functionis selected.EFBindicates
whetherornotthe FIFO1memoryis empty. Inthe FWFTmode, the ORBfunctionis selected. ORB
indicates the presence ofvaliddata onB0-B35outputs, available forreading. EFB/ORBis synchronizedto
theLOW-to-HIGHtransitionofCLKB.
ENA
PortAEnable
PortBEnable
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onportA.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onportB.
ENB
FFA/IRA
PortAFull/
Input Ready
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFA functionis selected. FFA indicates
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
indicates whetherornotthere is space available forwritingtothe FIFO1memory. FFA/IRAis
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
FFB/IRB
PortBFull/
Input Ready
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFB functionis selected. FFB indicates
whetherornotthe FIFO2memoryis full. Inthe FWFTmode, the IRBfunctionis selected. IRB
indicates whetherornotthere is space available forwritingtothe FIFO2memory. FFB/IRBis
synchronizedtotheLOW-to-HIGHtransitionofCLKB.
FWFT
FirstWordFall
Through Mode
I
I
This pinselects thetimingmode. AHIGHonFWFTselects IDTStandardmode,aLOWselects First
Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static
throughoutdeviceoperation.
FS1, FS0
FlagOffset
Selects
A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or
FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the
offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both
FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the Almost-
Empty and Almost-Full offsets for both FIFOs.
4
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
A0-A35outputs areactive,aHIGHlevelonMBAselects datafromthemail2registerforoutputanda
LOWlevelselectsFIFO2outputregisterdataforoutput.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35outputs are active, a HIGHlevelonMBBselects data fromthe mail1registeroroutputanda
LOWlevelselectsFIFO1outputregisterdataforoutput.
MBF1
Mail1Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1
isreset.
MBF2
Mail2Register
Flag
O
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdata tothemail2register.Writes
to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also set HIGH when
FIFO2is reset.
RST1
RST2
FIFO1Reset
FIFO2Reset
I
I
ToresetFIFO1,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for AFA
and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM.
ToresetFIFO2,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for AFB
and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM.
W/RA
W/RB
PortAWrite/
ReadSelect
I
I
A HIGHselects a write operationanda LOWselects a readoperationonportAfora LOW-to-HIGH
transitionofCLKA. The A0-A35outputs are inthe HIGHimpedance state whenW/RAis HIGH.
PortBWrite/
ReadSelect
A LOWselects a write operationanda HIGHselects a readoperationonportBfora LOW-to-HIGH
transitionofCLKB. The B0-B35outputs are inthe HIGHimpedance state when W/RBis LOW.
5
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
Rating
Commercial
–0.5to+4.6
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
(2)
VI
InputVoltageRange
V
VO(2)
OutputVoltageRange
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous OutputCurrent(VO =0toVCC)
ContinuousCurrentThroughVCC orGND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
IOUT
ICC
±50
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
Parameter
SupplyVoltagefor10ns
SupplyVoltagefor15ns
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
Min.
3.15
3.0
2
Typ.
3.3
3.3
—
Max.
3.45
3.6
Unit
V
(1)
VCC
VCC
VIH
VIL
IOH
IOL
TA
V
VCC+0.5
0.8
V
—
—
—
0
—
V
—
–4
mA
mA
°C
—
8
—
70
NOTE:
1. For 10ns speed grade: Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3652
IDT72V3662
IDT72V3672
Commercial
tCLK = 10, 15 ns(2)
Symbol
VOH
VOL
Parameter
OutputLogic"1"Voltage
OutputLogic"0"Voltage
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
Test Conditions
IOH = –4 mA
Min.
2.4
—
—
—
—
—
—
—
Typ.(1)
—
—
—
—
—
—
4
Max.
—
0.5
±10
±10
5
Unit
V
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
IOL = 8 mA
V
ILI
VI = VCC or 0
µ A
µ A
mA
mA
pF
ILO
VO = VCC or 0
VI = VCC –0.2V or 0V
VI = VCC –0.2V or 0V
f = 1 MHz
ICC2(3)
ICC3(3)
Standby Current (with CLKA & CLKB running) VCC = 3.6V,
StandbyCurrent(noclocksrunning)
InputCapacitance
VCC = 3.6V,
VI = 0,
1
(4)
CIN
—
—
(4)
COUT
OutputCapacitance
VO = 0,
f = 1 MHZ
8
pF
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. Commercial-10ns speed grade only: Vcc = 3.3V ± 0.15V, TA = 0° to +70°; JEDEC JESD8-A compliant.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
6
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3652/72V3662/72V3672 with
CLKAandCLKBsettofS. Alldatainputs anddataoutputs changestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputs were
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x ICC(f) + Σ(CL x VCC X fo)
N
where:
N = numberofoutputs=36
CL = outputcapacitanceload
fo = switchingfrequencyofanoutput
100
90
VCC = 3.6V
80
70
60
VCC = 3.0V
VCC = 3.3V
fdata = 1/2 fS
TA
= 25°C
CL
= 0 pF
50
40
30
20
10
0
100
0
10
20
30
40
50
Clock Frequency MHz
60
70
90
80
4660 drw03a
fS
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGEANDOPERATINGFREE-AIRTEMPERATURE
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70°C;JEDEC JESD8-A compliant)
IDT72V3652L10(1)
IDT72V3662L10(1)
IDT72V3672L10(1)
IDT72V3652L15
IDT72V3662L15
IDT72V3672L15
Symbol
fS
Parameter
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
PulseDuration, CLKAandCLKBLOW
Min.
Max.
Min.
—
15
6
Max.
Unit
MHz
ns
—
10
4.5
4.5
3
100
—
—
—
—
66.7
—
tCLK
tCLKH
tCLKL
tDS
—
ns
6
—
ns
SetupTime, A0-A35before CLKA↑andB0-B35
beforeCLKB↑
4
—
ns
tENS1
tENS2
tRSTS
SetupTime,CSA andW/RA,before
4
3
5
—
—
—
4.5
4.5
5
—
—
—
ns
ns
ns
CLKA↑; CSB, and W/RB before CLKB↑
SetupTime, ENAandMBA, before
CLKA↑; ENB, and MBB before CLKB↑
Setup Time, RST1 orRST2 LOWbefore CLKA↑
(2)
orCLKB↑
tFSS
tFWS
tDH
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
SetupTime,FWFTbeforeCLKA↑
7.5
0
—
—
—
—
7.5
0
—
—
—
—
ns
ns
ns
ns
HoldTime,A0-A35afterCLKA↑andB0-B35afterCLKB↑
0.5
0.5
1
tENH
HoldTime, CSA, W/RA, ENA, andMBAafterCLKA↑;
CSB, W/RB, ENB, andMBBafterCLKB↑
1
(2)
tRSTH
tFSH
Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑
4
2
—
—
—
4
2
—
—
—
ns
ns
ns
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
tSKEW1(3)
SkewTime,betweenCLKA↑andCLKB↑forEFA/ORA,
EFB/ORB, FFA/IRA, and FFB/IRB
7.5
7.5
tSKEW2(3,4) SkewTime,betweenCLKA↑andCLKB↑forAEA,
12
—
12
—
ns
AEB, AFA, and AFB
NOTES:
1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
8
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
(For 10ns speed grade only: Vcc = 3.3V ± 0.15V; TA = 0°C to +70°C;JEDEC JESD8-A compliant)
IDT72V3652L10(1)
IDT72V3662L10(1)
IDT72V3672L10(1)
IDT72V3652L15
IDT72V3662L15
IDT72V3672L15
Symbol
tA
Parameter
Min.
Max.
Min.
Max.
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B35
2
6.5
6.5
2
2
10
8
tPIR
PropagationDelayTime, CLKA↑ toFFA/IRAandCLKB↑to
FFB/IRB
2
ns
tPOR
PropagationDelayTime,CLKA↑toEFA/ORAandCLKB↑to
EFB/ORB
1
6.5
1
8
ns
tPAE
tPAF
tPMF
PropagationDelayTime,CLKA↑toAEA andCLKB↑toAEB
PropagationDelayTime, CLKA↑ toAFA andCLKB↑ toAFB
1
1
0
6.5
6.5
6.5
1
1
0
8
8
8
ns
ns
ns
PropagationDelayTime, CLKA↑ toMBF1 LOWor
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
tPMR
tMDV
tPRF
PropagationDelayTime, CLKA↑toB0-B35(2) and
2
2
1
8
2
2
1
10
10
15
ns
ns
ns
CLKB↑toA0-A35(3)
Propagation Delay Time, MBA to A0-A35 valid and
MBBtoB0-B35Valid
6.5
10
PropagationDelayTime, RST1 LOWtoAEB LOW,AFA
HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW,
AFB HIGH, and MBF2 HIGH
tEN
tDIS
EnableTime,CSA andW/RALOWtoA0-A35Active
and CSB LOW and W/RB HIGH to B0-B35 Active
2
1
6
6
2
1
10
8
ns
ns
Disable Time, CSA orW/RAHIGHtoA0-A35athigh-impedance
and CSB HIGH or W/RB LOW to B0-B35 at high-impedance
NOTES:
1. For 10ns speed grade: Vcc = 3.3V ± 0.15V; TA = 0° to +70°.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
9
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
readrequestnecessary. Subsequentwordsmustbeaccessedbyperforming
aformalreadoperation.
SIGNALDESCRIPTION
FollowingReset,thelevelappliedtotheFWFTinputtochoosethedesired
timingmodemustremainstaticthroughoutFIFOoperation.RefertoFigure2
(Reset)foraFirstWordFallThroughselecttimingdiagram.
RESET
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding
a LOW pulse to RST1 and RST2 simultaneously. Afterwards, the FIFO
memories of the IDT72V3652/72V3662/72V3672 are reset separately by
taking their Reset (RST1, RST2) inputs LOW for at least four port-A Clock
(CLKA)andfourport-BClock(CLKB)LOW-to-HIGHtransitions. TheReset
inputs can switch asynchronously to the clocks. A FIFO reset initializes the
internalreadandwritepointersandforcestheInputReadyflag(IRA,IRB)LOW,
theOutputReadyflag(ORA,ORB)LOW,theAlmost-Emptyflag(AEA,AEB)
LOW,andtheAlmost-Fullflag(AFA,AFB)HIGH. ResettingaFIFOalsoforces
theMailboxFlag(MBF1, MBF2)oftheparallelmailboxregisterHIGH. After
aFIFOisreset,itsInputReadyflagissetHIGHaftertwoclockcyclestobegin
normaloperation.
ALOW-to-HIGHtransitiononaFIFOReset(RST1,RST2)inputlatches
thevalueoftheFlagSelect(FS0,FS1)inputsforchoosingtheAlmost-Fulland
Almost-Empty offset programming method. (For details see Table 1, Flag
Programming,andtheProgrammingtheAlmost-EmptyandAlmost-FullFlags
section). The relevantFIFOResettimingdiagramcanbe foundinFigure 2.
ALMOST-EMPTYFLAGANDALMOST-FULLFLAGOFFSETPROGRAM-
MING
Fourregistersinthesedevicesareusedtoholdtheoffsetvaluesforthe
Almost-EmptyandAlmost-Fullflags.TheportBAlmost-Emptyflag(AEB)Offset
registerislabeledX1andtheportAAlmost-Emptyflag(AEA)Offsetregister
is labeledX2. The portAAlmost-Fullflag(AFA)Offsetregisteris labeledY1
andtheportBAlmost-Fullflag(AFB)OffsetregisterislabeledY2.Theindex
ofeachregisternamecorrespondstoitsFIFOnumber.Theoffsetregisterscan
be loaded with preset values during the reset of a FIFO or they can be
programmed from port A (see Table 1).
FS0 and FS1 function the same way in both IDT Standard and FWFT
modes.
— PRESET VALUES
ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisters
withoneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselect
inputsmustbeHIGHduringtheLOW-to-HIGHtransitionofitsresetinput.For
example,toloadthepresetvalueof64intoX1andY1,FS0andFS1mustbe
HIGH when FlFO1 Reset (RST1) returns HIGH. Flag offset registers
associatedwithFIFO2areloadedwithoneofthepresetvaluesinthesameway
withFIFO2Reset(RST2)toggledsimultaneouslywithFIFO1Reset(RST1).
For preset value loading timing diagram, see Figure 2.
FIRST WORD FALL THROUGH (FWFT)
AfterMasterReset,theFWFTselectfunctionisactive,permittingachoice
betweentwopossible timingmodes:IDTStandardmode orFirstWordFall
Through (FWFT) mode. Once the Reset (RST1, RST2) input is HIGH, a
HIGH on the FWFT input during the next LOW-to-HIGH transition of CLKA
(forFIFO1)andCLKB(forFIFO2)willselectIDTStandardmode.Thismode
uses the Empty Flag function (EFA, EFB) to indicate whether or not there
areanywordspresentintheFIFOmemory.ItusestheFullFlagfunction(FFA,
FFB) to indicate whether or not the FIFO memory has any free space for
writing.InIDTStandardmode,everywordreadfromtheFIFO,includingthe
first,mustberequestedusingaformalreadoperation.
OncetheReset(RST1,RST2)inputis HIGH,aLOWontheFWFTinput
duringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)andCLKB(for
FIFO2)willselectFWFTmode.This mode uses the OutputReadyfunction
(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedataoutputs
(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)toindicate
whetherornottheFIFOmemoryhasanyfreespaceforwriting.IntheFWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodataoutputs,no
— PARALLEL LOAD FROM PORT A
ToprogramtheX1,X2,Y1,andY2registersfromportA,bothFlFOsshould
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transitionoftheResetinputs.Itisimportanttonotethatonceparallelprogramming
hasbeenselectedduringaMasterResetbyholdingbothFS0&FS1LOW,these
inputsmustremainLOWduringallsubsequentFIFOoperation.Theycanonly
be toggled HIGH when future Master Resets are performed and other
programmingmethodsaredesired.
Afterthisresetiscomplete,thefirstfourwritestoFIFO1donotstoredata
inthe FIFOmemorybutloadthe offsetregisters inthe orderY1, X1, Y2, X2.
TABLE 1 — FLAG PROGRAMMING
FS1
FS0
RST1
RST2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H
H
H
H
L
H
H
L
↑
X
↑
X
↑
X
↑
X
↑
X
↑
X
↑
↑
64
X
16
X
8
X
64
X
16
X
8
L
H
H
L
L
X
(3)
(3)
L
ParallelprogrammingviaPortA
ParallelprogrammingviaPortA
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
3. If parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
10
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
TheportAdatainputsusedbytheoffsetregistersare(A7-A0),(A8-A0),or(A9- outputsareinthehigh-impedancestatewheneitherCSBisHIGHorW/RBis
A0) for the IDT72V3652, IDT72V3662, or IDT72V3672, respectively. The LOW.TheB0-B35outputsareactivewhenCSB isLOWandW/RBisHIGH.
highestnumberedinputisusedasthemostsignificantbitofthebinarynumber
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
ineachcase. Validprogrammingvaluesfortheregistersrangesfrom1to2,044 transition of CLKB whenCSB is LOW, W/RB is LOW, ENB is HIGH, MBB is
for the IDT72V3652; 1 to 4,092 for the IDT72V3662; and 1 to 8,188 for the LOW,andFFB/IRBis HIGH.Datais readfromFIFO1totheB0-B35outputs
IDT72V3672. AfteralltheoffsetregistersareprogrammedfromportA,theport byaLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENB
BFull/InputReadyflag(FFB/IRB)issetHIGH,andbothFIFOsbeginnormal isHIGH,MBBisLOW,andEFB/ORBisHIGH(seeTable3).FIFOreadsand
operation.SeeFigure3forrelevantoffsetregisterparallelprogrammingtiming writesonportBareindependentofanyconcurrentportAoperation.Writeand
diagram.
Read cycle timing diagrams for Port B can be found in Figure 5 and 6.
The setupandholdtime constraints tothe portClocks forthe portChip
SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations
FIFO WRITE/READ OPERATION
ThestateoftheportAdata(A0-A35)outputsiscontrolledbyportAChip andarenotrelatedtohigh-impedancecontrolofthedataoutputs.Ifaportenable
Select(CSA)andportAWrite/Readselect(W/RA).TheA0-A35outputsare isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay
inthehigh-impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35 changestatesduringthesetupandholdtimewindowofthecycle.
outputs are active when both CSA and W/RA are LOW.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe
transitionofCLKAwhenCSA is LOW,W/RAis HIGH,ENAis HIGH,MBAis LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
LOW,andFFA/IRAisHIGH. DataisreadfromFIFO2totheA0-A35outputs WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA registersonlywhenareadisselectedusingtheport’sChipSelect,Write/Read
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand select,Enable,andMailboxselect.
writesonportAareindependentofanyconcurrentportBoperation.Writeand
Read cycle timing diagrams for Port A can be found in Figure 4 and 7.
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause
theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe
TheportBcontrolsignalsareidenticaltothoseofportAwiththeexception ReadClock. Thedatawordwillnotbeautomaticallysenttotheoutputregister.
thattheportBWrite/Readselect(W/RB)istheinverseoftheportAWrite/Read Instead, data residing in the FIFO's memory array is clocked to the output
select(W/RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe registeronlywhenareadisselected usingtheport’sChipSelect,Write/Read
portBChipSelect(CSB)andportBWrite/Readselect(W/RB).TheB0-B35 select,Enable,andMailboxselect.
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
X
ENA
X
MBA
X
CLKA
Data A (A0-A35) I/O
High-Impedance
Input
Port Function
X
X
↑
None
None
H
L
X
L
H
H
L
Input
FIFO1write
Mail1write
L
H
H
H
↑
Input
L
L
L
L
X
↑
Output
None
L
L
H
L
Output
FIFO2 read
None
L
L
L
H
X
↑
Output
L
L
H
H
Output
Mail2 read (set MBF2 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
X
ENB
X
MBB
X
CLKB
Data B (B0-B35) I/O
High-Impedance
Input
Port Function
X
X
↑
None
None
L
L
X
L
L
H
L
Input
FIFO2write
Mail2write
L
L
H
H
↑
Input
L
H
L
L
X
↑
Output
None
L
H
H
L
Output
FIFO1 read
None
L
H
L
H
X
↑
Output
L
H
H
H
Output
Mail1 read (set MBF1 HIGH)
11
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
SYNCHRONIZED FIFO FLAGS
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flop thatreadsdatafromitsarray.ForboththeFWFTandIDTStandardmodes,
stages.Thisisdonetoimproveflagsignalreliabilitybyreducingtheprobability the FIFOreadpointeris incrementedeachtime a newwordis clockedtoits
ofmetastableeventswhenCLKAandCLKBoperateasynchronouslytoone outputregister.ThestatemachinethatcontrolsanOutputReadyflagmonitors
another.EFA/ORA,AEA,FFA/IRA,andAFAaresynchronizedtoCLKA.EFB/ a write pointer and read pointer comparator that indicates when the FIFO
ORB,AEB,FFB/IRB,andAFBaresynchronizedtoCLKB.Tables4and5show memorystatusisempty,empty+1,orempty+2.
the relationshipofeachportflagtoFIFO1andFIFO2.
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReady
flagsynchronizingclock.Therefore,anOutputReadyflagisLOWifawordin
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntil
thethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simulta-
neouslyforcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFO
outputregister.
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(ORA,
ORB)functionisselected.WhentheOutputReadyflagisHIGH,newdatais
presentintheFIFOoutputregister.WhentheOutputReadyflagisLOW,the
previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO
reads are ignored.
In the IDT Standard mode, the Empty Flag (EFA, EFB) function is
selected.WhentheEmptyFlagisHIGH,dataisavailableintheFIFO’sRAM
forreadingtotheoutputregister.WhentheEmptyFlagisLOW,theprevious
datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare
ignored.
InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlagisLOW
TABLE 4 — FIFO1 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKB
Synchronized
to CLKA
(1,2)
Number of Words in FIFO
IDT72V3652(3)
IDT72V3662(3)
IDT72V3672(3)
EFB/ORB
AEB
L
AFA
FFA/IRA
0
1toX1
0
1toX1
0
1toX1
L
H
H
H
H
H
H
H
L
H
H
H
H
L
L
(X1+1)to[2,048-(Y1+1)]
(2,048-Y1)to2,047
2,048
(X1+1)to[4,096-(Y1+1)]
(4,096-Y1)to4,095
4,096
(X1+1)to[8,192-(Y1+1)]
(8,192-Y1)to8,191
8,192
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from
port A.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
TABLE 5 — FIFO2 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKA
Synchronized
to CLKB
(1,2)
Number of Words in FIFO
IDT72V3652(3)
IDT72V3662(3)
IDT72V3672(3)
EFA/ORA
AEA
L
AFB
FFB/IRB
0
1toX2
0
1toX2
0
1toX2
L
H
H
H
H
H
H
H
L
H
H
H
H
L
L
(X2+1)to[2,048-(Y2+1)]
(2,048-Y2)to2,047
2,048
(X2+1)to[4,096-(Y2+1)]
(4,096-Y2)to4,095
4,096
(X2+1)to[8,192-(Y2+1)]
(8,192-Y2)to8,191
8,192
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from
port A.
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.
12
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
ifawordinmemoryisthenextdatatobesenttotheFlFOoutputregisterand ifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)words.
twocycles oftheportClockthatreads datafromtheFIFOhavenotelapsed Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
sincethetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOW nization cycle. (See Figures 16 and 17).
untilthesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,
forcing the Empty Flag HIGH; only then can data be read.
ALMOST-FULL FLAGS (AFA, AFB)
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsa
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
canbethefirstsynchronizationcycle(seeFigures8through11forEFA/ORA statusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstateisdefined
andEFB/ORBtimingdiagrams).
bythecontentsofregisterY1forAFAandregisterY2forAFB.Theseregisters
are loaded with preset values during a FlFO reset or programmed from port
A(seeAlmost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection).
FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)
Thisisadualpurposeflag.InFWFTmode,theInputReady(IRAandIRB) AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthan
function is selected. In IDT Standard mode, the Full Flag (FFA and FFB) orequalto(2,048-Y),(4,096-Y),or(8,192-Y)fortheIDT72V3652,IDT72V3662,
functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis orIDT72V3672respectively. AnAlmost-Fullflagis HIGHwhenthe number
HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory of words in its FIFO is less than or equal to [2,048-(Y+1)], [4,096-(Y+1)], or
locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites [8,192-(Y+1)] for the IDT72V3652, IDT72V3662, or IDT72V3672 respec-
to the FIFO are ignored.
tively. NotethatadatawordpresentintheFIFOoutputregisterhasbeenread
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat frommemory.
writes datatoits array.ForbothFWFTandIDTStandardmodes,eachtime
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine arerequiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewlevelof
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer fill.Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2. (Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready not elapsed since the read that reduced the number of words in memory to
to be written to in a minimum of two cycles of the Full/Input Ready flag [2,048/4,096/8,192-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-
synchronizingclock.Therefore,aFull/InputReadyflagisLOWiflessthantwo to-HIGHtransitionofitssynchronizingclockaftertheFIFOreadthatreduces
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe thenumberofwordsinmemoryto[2,048/4,096/8,192-(Y+1)]. ALOW-to-HIGH
next memory write location has been read. The second LOW-to-HIGH transitionofanAlmost-Fullflagsynchronizingclockbeginsthefirstsynchroni-
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets zationcycleifitoccursattimetSKEW2orgreaterafterthereadthatreducesthe
the Full/InputReadyflagHIGH.
number of words in memory to [2,048/4,096/8,192-(Y+1)]. Otherwise, the
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock subsequentsynchronizingclockcyclemaybethefirstsynchronizationcycle
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat (see Figures 18 and 19).
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcyclecan
bethefirstsynchronizationcycle(seeFigures12through15forFFA/IRAand
FFB/IRB timing diagrams).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
informationbetweenportAandportBwithoutputtingitinqueue.TheMailbox
select(MBA,MBB)inputschoosebetweenamailregisterandaFIFOforaport
datatransferoperation.ALOW-to-HIGHtransitiononCLKAwritesA0-A35data
tothemail1registerwhenaportAWriteisselectedbyCSA,W/RA,andENA
andwithMBAHIGH.ALOW-to-HIGHtransitiononCLKBwritesB0-B35data
tothemail2registerwhenaportBWriteisselectedbyCSB,W/RB,andENB
andwithMBBHIGH.Writingdatatoamailregistersetsitscorrespondingflag
(MBF1orMBF2)LOW.Attemptedwrites toamailregisterareignoredwhile
themailflagisLOW.
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthemail
registerwhentheportmailboxselectinputisHIGH.TheMail1RegisterFlag
(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhenaportBRead
isselectedbyCSB,W/RB,andENBandwithMBBHIGH.TheMail2Register
Flag(MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKAwhenaport
A read is selected by CSA, W/RA, and ENA and with MBA HIGH. The data
inamailregisterremainsintactafteritisreadandchangesonlywhennewdata
iswrittentotheregister.FormailregisterandMailRegisterFlagtimingdiagrams,
see Figure 20 and 21.
ALMOST-EMPTY FLAGS (AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
datafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX1forAEBandregister
X2forAEA.TheseregistersareloadedwithpresetvaluesduringaFIFOreset
orprogrammedfromportA(seeAlmost-EmptyflagandAlmost-Fullflagoffset
programmingsection).AnAlmost-EmptyflagisLOWwhenitsFIFOcontains
Xorless words andis HIGHwhenits FIFOcontains (X+1)ormore words. A
data wordpresentinthe FIFOoutputregisterhas beenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizing
clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew
leveloffill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormore
wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
sincethewritethatfilledthememorytothe(X+1)level. AnAlmost-Emptyflag
issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter
theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionof
anAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycle
13
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
tRSTH
t
RSTS
t
FSS
t
FSH
RST1
FWFT
tFWS
0,1
FS1,FS0
FFA/IRA
tPIR
tPIR
tPOR
EFB/ORB
AEB
t
t
PRF
PRF
AFA
t
PRF
MBF1
4660 drw04
NOTES:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
2. If FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where FWFT is LOW.
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)
CLKA
4
1
2
t
FSS
RST1,
RST2
t
FSH
0,0
FS1,FS0
tPIR
FFA/IRA
ENA
(1)
SKEW1
tENS2
tENH
t
tDH
tDS
A0 - A35
First Word to FIFO1
AFA Offset
AEB Offset
AFB Offset
AEA Offset
(Y1)
(X1)
(Y2)
(X2)
CLKB
1
2
tPIR
FFB/IRB
4660 drw05
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
14
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
FFA/IRA
HIGH
tENS1
tENH
CSA
t
ENS1
t
ENH
ENH
ENH
W/RA
MBA
ENA
t
ENS2
t
tENS2
tENS2
tENS2
t
tENH
tENH
tDS
tDH
W1(1)
W2(1)
No Operation
A0 - A35
4660 drw06
NOTE:
1. Written to FIFO1.
Figure 4. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
FFB/IRB HIGH
tENH
tENS1
CSB
t
ENH
t
ENS1
ENS2
W/RB
tENH
t
MBB
tENH
tENH
tENH
tENS2
tENS2
tENS2
ENB
tDH
t
DS
(1)
W2(1)
No Operation
B0 - B35
W1
4660 drw07
NOTE:
1. Written to FIFO2.
Figure 5. Port B Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
15
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
EFB/ORB HIGH
CSB
W/RB
tENS2
MBB
tENH
tENH
tENH
tENS2
tENS2
ENB
No Operation
W2(1)
t
t
MDV
MDV
t
DIS
t
A
t
A
A
t
EN
EN
B0-B35
W1(1)
W2(1)
Previous Data
(IDT Standard Mode)
t
DIS
OR
tA
t
t
B0-B35
W3(1)
W1(1)
(FWFT Mode)
4660 drw08
NOTE:
1. Read From FIFO1.
Figure 6. Port B Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKA
EFA/ORA HIGH
CSA
W/RA
MBA
ENA
t
ENS2
tENH
t
ENH
t
ENH
t
ENS2
t
ENS2
No Operation
W2(1)
t
MDV
t
DIS
DIS
t
A
t
A
t
EN
A0-A35
Previous Data
W1(1)
W2(1)
(Standard Mode)
t
t
MDV
t
A
OR
tA
t
EN
A0-A35
W3(1)
W1(1)
(FWFT Mode)
4660 drw09
NOTE:
1. Read From FIFO2.
Figure 7. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
16
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
tENS2
tENH
MBA
tENS2
tENH
ENA
HIGH
IRA
tDH
tDS
A0 - A35
W1
t
CLK
(1)
tSKEW1
tCLKH
tCLKL
1
2
3
CLKB
tPOR
tPOR
ORB FIFO1Empty
CSB LOW
W/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
tA
B0 -B35
Old Data in FIFO1 Output Register
W1
4660 drw10
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
17
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
t
ENS2
t
ENH
ENH
MBA
tENS2
t
ENA
FFA
HIGH
tDS
tDH
A0-A35
W1
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
CLKB
1
2
tPOR
tPOR
FIFO1 Empty
LOW
EFB
CSB
W/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
tA
W1
B0-B35
4660 drw11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Figure 9. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
18
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
LOW
CSB
W/RB
tENS2
tENS2
tENH
tENH
MBB
ENB
IRB
HIGH
tDS
tDH
B0 - B35
W1
tCLK
tCLKL
(1)
tSKEW1
tCLKH
1
2
3
CLKA
ORA
tPOR
tPOR
FIFO2 Empty
LOW
LOW
LOW
CSA
W/RA
MBA
tENS2
tENH
ENA
tA
Old Data in FIFO2 Output Register
W1
A0 -A35
4660 drw12
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 10. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
19
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKB
LOW
LOW
CSB
W/RB
t
ENS2
ENS2
tENH
MBB
ENB
t
tENH
HIGH
FFB
tDH
tDS
W1
B0-B35
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
1
2
CLKA
tPOR
tPOR
EFA
FIFO2 Empty
LOW
LOW
CSA
W/RA
MBA
LOW
tENS2
tENH
ENA
tA
A0-A35
W1
4660 drw13
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Figure 11. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
20
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
HIGH
ORB
tA
Previous Word in FIFO1 Output Register
SKEW1
Next Word From FIFO1
B0 -B35
(1)
tCLK
t
tCLKL
tCLKH
1
2
CLKA
tPIR
tPIR
FIFO1 Full
LOW
IRA
CSA
W/RA
HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
A0 - A35
NOTE:
tDS
tDH
Write
4660 drw14
To FIFO1
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 12. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
21
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
MBB
HIGH
LOW
tENS2
tENH
ENB
EFB
HIGH
tA
Previous Word in FIFO1 Output Register
Next Word From FIFO1
B0-B35
(1)
tCLK
tSKEW1
tCLKH
tCLKL
CLKA
1
2
tPIR
tPIR
FIFO1 Full
LOW
FFA
CSA
HIGH
W/RA
tENS2
tENH
MBA
tENS2
tENH
ENA
tDS
tDH
A0-A35
Write
4660 drw15
To FIFO1
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
Figure 13. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
22
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOW
CSA
W/RA LOW
LOW
MBA
ENA
tENH
tENS2
HIGH
ORA
tA
Previous Word in FIFO2 Output Register
SKEW1
Next Word From FIFO2
A0 -A35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKB
IRB
tPIR
tPIR
FIFO2 FULL
LOW
CSB
LOW
W/RB
tENS2
tENH
MBB
ENB
tENS2
tENH
tDS
tDH
Write
B0 - B35
4660 drw16
To FIFO2
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 14. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
23
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOW
LOW
LOW
CSA
W/RA
MBA
tENS2
tENH
ENA
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
A0-A35
(1)
tCLK
tSKEW1
tCLKH
tCLKL
CLKB
1
2
tPIR
tPIR
FIFO2 Full
LOW
FFB
CSB
W/RB
LOW
t
ENS2
ENS2
t
ENH
MBB
ENB
t
t
ENH
tDS
tDH
Write
B0-B35
4660 drw17
To FIFO2
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
Figure 15. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
CLKA
tENS2
tENH
ENA
(1)
tSKEW2
1
2
CLKB
t
PAE
t
PAE
AEB
X1 Words in FIFO1
(X1+1) Words in FIFO1
ENS2
t
tENH
ENB
4660 drw18
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
Figure 16. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
24
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENS2
tENH
ENB
(1)
tSKEW2
1
CLKA
2
t
PAE
t
PAE
AEA
X2 Words in FIFO2
(X2+1) Words in FIFO2
ENS2
t
tENH
ENA
4660 drw19
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
Figure 17. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
(1)
tSKEW2
1
2
CLKA
ENA
tENS2
tENH
t
PAF
t
PAF
(D-Y1) Words in FIFO1
[D-(Y1+1)] Words in FIFO1
AFA
CLKB
tENS2
tENH
ENB
4660 drw20
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3652, 4,096 for the IDT72V3662, 8,192 for the IDT72V3672.
Figure 18. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
25
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
(1)
tSKEW2
1
2
CLKB
tENS2
tENH
ENB
AFB
t
PAF
t
PAF
(D-Y2) Words in FIFO2
[D-(Y2+1)] Words in FIFO2
CLKA
tENS2
tENH
ENA
4660 drw21
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3652, 4,096 for the IDT72V3662, 8,192 for the IDT72V3672.
Figure 19. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
CLKA
tENH
tENS1
CSA
W/RA
MBA
t
ENS1
tENH
tENS2
tENH
tENS2
tENH
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENH
tENS2
t
MDV
tEN
t
PMR
tDIS
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
B0 - B35
4660 drw22
Figure 20. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
26
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENS1
tENH
CSB
t
ENS1
t
ENH
ENH
W/RB
tENS2
t
MBB
ENB
tENH
tENS2
tDH
tDS
W1
B0 - B35
CLKA
t
PMF
t
PMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS2
t
MDV
tEN
tDIS
t
PMR
W1 (Remains valid in Mail 2 Register after read)
FIFO2 Output Register
A0 - A35
4660 drw23
Figure 21. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
27
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
330
Ω
From Output
Under Test
30 pF (1)
510
Ω
PROPAGATION DELAY
LOAD CIRCUIT
3V
3V
Timing
Input
1.5V
High-Level
1.5V
Input
1.5V
GND
GND
3V
t
S
th
tW
3V
Data,
Enable
Input
1.5V
1.5V
Low-Level
1.5V
1.5V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5V
1.5V
t
PZL
GND
tPLZ
3V
GND
≈
3V
Input
1.5V
1.5V
1.5V
Low-Level
Output
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
In-Phase
Output
1.5V
1.5V
High-Level
Output
1.5V
t
PHZ
V
OL
≈ OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4660 drw24
NOTE:
1. Includes probe and jig capacitance.
Figure 22. Load Circuit and Voltage Waveforms
28
ORDERING INFORMATION
IDT
XXXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
Commercial (0°C to +70°C)
PF
PQF
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Clock Cycle Time (tCLK
)
10
15
Commercial Only
Low Power
Speed in Nanoseconds
L
72V3652
72V3662
72V3672
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
3.3V SyncBiFIFO
3.3V SyncBiFIFO
3.3V SyncBiFIFO
4660 drw 25
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
06/12/2000
09/25/2000
12/21/2000
03/21/2001
11/03/2003
pgs. 1,7 and 11.
pgs. 6, 8, 9 and 29.
pg. 11.
pgs. 6 and 7.
pg. 1.
CORPORATE HEADQUARTERS
for SALES:
for TECH SUPPORT:
2975StenderWay
Santa Clara, CA 95054
800-345-7015 or 408-727-6116
fax: 408-492-8674
408-330-1753
e-mail:FIFOhelp@idt.com
www.idt.com
29
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明