IDT72V3692L15PFG [IDT]
FIFO, 32KX36, 10ns, Synchronous, CMOS, PQFP120, TQFP-120;
| 型号： | IDT72V3692L15PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 32KX36, 10ns, Synchronous, CMOS, PQFP120, TQFP-120 先进先出芯片 |
| 文件： | 总29页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncBiFIFOTM
16,384 x 36 x 2
32,768 x 36 x 2
IDT72V3682
IDT72V3692
IDT72V36102
65,536 x 36 x 2
• Mailbox bypass register for each FIFO
FEATURES
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• Memory storage capacity:
IDT72V3682 – 16,384 x 36 x 2
• FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
• FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
• Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
• Available in space-saving 120-pin Thin Quad Flatpack (TQFP)
• Pin compatible to the lower density parts, IDT72V3622/72V3632/
72V3642/72V3652/72V3662/72V3672
IDT72V3692 – 32,768 x 36 x 2
IDT72V36102 – 65,536 x 36 x 2
• Supports clock frequencies up to 100MHz
• Fast access times of 6.5ns
• Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
• Two independent clocked FIFOs buffering data in opposite direc-
tions
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
Port-A
Control
Logic
W/RA
RAM
ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
ENA
MBA
36
FIFO1,
Mail1
Reset
Logic
RST1
Write
Pointer
Read
Pointer
36
Status Flag
Logic
EFB/ORB
AEB
FFA/IRA
AFA
FIFO 1
FS
0
1
Programmable Flag
Offset Registers
Timing
Mode
FWFT
FS
A
0
- A35
16
B0 - B35
FIFO 2
Status Flag
EFA/ORA
FFB/IRB
AFB
Logic
AEA
36
Read
Pointer
Write
Pointer
36
FIFO2,
Mail2
Reset
Logic
RST2
RAM
ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
CLKB
CSB
Port-B
Control
Logic
W/RB
ENB
Mail 2
Register
MBB
4679 drw 01
MBF2
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheSyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
NOVEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4679/3
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
DESCRIPTION
The IDT72V3682/72V3692/72V36102 are designed to run off a 3.3V
supplyforexceptionallylow-powerconsumption. Thesedevicesaremono-
lithic,high-speed,low-power,CMOSBidirectionalSyncFIFO(clocked)memo-
rieswhichsupportclockfrequenciesupto100MHzandhavereadaccesstimes
as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port
SRAMFIFOsonboardeachchipbufferdatainoppositedirections.Commu-
nication between each port may bypass the FIFOs via two 36-bit mailbox
registers.Eachmailboxregisterhasaflagtosignalwhen newmailhasbeen
stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
each port are independent of one another and can be asynchronous or
These devices have two modes of operation: In the IDT Standard mode,
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray.A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word(36-bitwide)writtentoanemptyFIFOappearsautomaticallyonthe
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the FWFT pin
duringFIFOoperationdetermines themodeinuse.
EachFIFOhasacombinedEmpty/OutputReadyFlag(EFA/ORAandEFB/
ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB). The
EF and FF functions are selected in the IDT Standard mode. EF indicates
PIN CONFIGURATION
B
B
B
B
35
34
33
32
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
A
A
A
A
35
34
33
32
1
2
3
4
GND
V
CC
5
B
B
B
B
B
B
V
B
B
31
30
29
28
27
26
CC
25
24
A
31
6
A30
7
GND
8
A
A
A
A
A
A
A
29
28
27
26
25
24
23
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
B
B
B
B
B
B
23
22
21
20
19
18
FWFT
A
22
CC
V
A
21
20
19
18
A
A
A
GND
B
B
V
B
B
B
B
17
16
CC
15
14
13
12
GND
A
A
A
A
A
17
16
15
14
13
V
CC
GND
A12
4679 drw 03
TQFP (PN120-1, order code: PF)
TOP VIEW
2
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
defaultoffsetsettingsarealsoprovided.TheAEAandAEBthresholdcanbe
set at 8, 16 or 64 locations from the empty boundary and the AFA and AFB
thresholdcanbesetat8,16or64locations fromthefullboundary.Allthese
choices are made using the FS0 and FS1 inputs during Reset.
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.If,
at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
The IDT72V3682/72V3692/72V36102 are characterized for operation
from0°Cto70°C.Industrialtemperaturerange(-40°Cto+85°C)isavailable
by special order. They are fabricated using IDT’s high speed, submicron
CMOStechnology.
whetherornottheFIFOmemoryisempty.FF showswhetherthememoryis
fullornot.TheIRandORfunctionsareselectedintheFirstWordFallThrough
mode.IRindicateswhetherornottheFIFOhasavailablememorylocations.
ORshowswhethertheFIFOhasdataavailableforreadingornot.Itmarksthe
presenceofvaliddataontheoutputs.
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)anda
programmableAlmost-Fullflag(AFAandAFB). AEAandAEB indicatewhen
aselectednumberofwordsremainintheFIFOmemory. AFAandAFBindicate
whenthe FIFOcontains more thana selectednumberofwords.
FFA/IRA, FFB/IRB, AFA andAFB aretwo-stagesynchronizedtotheport
clockthatwritesdataintoitsarray.EFA/ORA,EFB/ORB,AEAandAEBaretwo-
stagesynchronizedtotheportclockthatreadsdatafromitsarray.Program-
mableoffsetsforAEA,AEB,AFAandAFBareloaded byusingPortA.Three
3
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
PortAData
I/0
O
36-bitbidirectionaldataportforsideA.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwordsinFIFO2is
AEA
PortAAlmost-
EmptyFlag
(Port A) lessthanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberof words in FIFO1 is
(Port B) lessthanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty locationsin
(Port A) FIFO1is less thanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofempty locationsin
(Port B) FIFO2is less thanorequaltothevalueintheAlmost-FullBOffsetregister,Y2.
AEB
AFA
AFB
PortBAlmost-
EmptyFlag
O
PortAAlmost-
Full Flag
O
PortBAlmost-
Full Flag
O
B0 - B35
CLKA
PortBData
I/O
I
36-bitbidirectionaldataportforsideB.
PortAClock
CLKAis a continuous clockthatsynchronizes alldata transfers throughportAandcanbe asynchronous or
coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKB
PortBClock
I
CLKBisacontinuousclockthatsynchronizesalldatatransfersthroughportBand can be asynchronous or
coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH
transitionofCLKB.
CSA
Port A Chip
Select
I
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35
outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onportB. The
B0- B35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA
PortAEmpty/
OutputReady
Flag
O
This is adualfunctionpin. IntheIDTStandardmode,theEFA functionis selected.EFAindicates
whetherornotthe FIFO2memoryis empty. Inthe FWFTmode, the ORAfunctionis selected. ORA
indicates thepresenceofvaliddataonA0-A35outputs,availableforreading.EFA/ORAis synchronized
totheLOW-to-HIGHtransitionofCLKA.
EFB/ORB
PortBEmpty/
OutputReady
Flag
O
This is adualfunctionpin. IntheIDTStandardmode,theEFB functionis selected.EFBindicates
whetherornotthe FIFO1memoryis empty. Inthe FWFTmode, the ORBfunctionis selected. ORB
indicates the presence ofvaliddata onB0-B35outputs, available forreading. EFB/ORBis synchronizedto
theLOW-to-HIGHtransitionofCLKB.
ENA
PortAEnable
PortBEnable
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onportA.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onportB.
ENB
FFA/IRA
PortAFull/
Input Ready
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFA functionis selected. FFA indicates
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
indicates whetherornotthere is space available forwritingtothe FIFO1memory. FFA/IRAis
synchronizedtotheLOW-to-HIGHtransitionofCLKA.
FFB/IRB
PortBFull/
Input Ready
Flag
O
This is a dualfunctionpin. Inthe IDTStandardmode, the FFB functionis selected. FFB indicates
whetherornotthe FIFO2memoryis full. Inthe FWFTmode, the IRBfunctionis selected. IRB
indicates whetherornotthere is space available forwritingtothe FIFO2memory. FFB/IRBis
synchronizedtotheLOW-to-HIGHtransitionofCLKB.
FWFT
FirstWordFall
Through Mode
I
I
This pinselects thetimingmode. AHIGHonFWFTselects IDTStandardmode,aLOWselects First
Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static
throughoutdeviceoperation.
FS1, FS0
FlagOffset
Selects
A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or
FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the
offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both
FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the Almost-
Empty and Almost-Full offsets for both FIFOs.
4
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
A0-A35outputs areactive,aHIGHlevelonMBAselects datafromthemail2registerforoutputanda
LOWlevelselectsFIFO2outputregisterdataforoutput.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35outputs are active, a HIGHlevelonMBBselects data fromthe mail1registeroroutputanda
LOWlevelselectsFIFO1outputregisterdataforoutput.
MBF1
Mail1Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1
isreset.
MBF2
Mail2Register
Flag
O
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdata tothemail2register.Writes
to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also set HIGH when
FIFO2is reset.
RST1
RST2
FIFO1Reset
FIFO2Reset
I
I
ToresetFIFO1,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for AFA
and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM.
ToresetFIFO2,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for AFB
and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM.
W/RA
W/RB
PortAWrite/
ReadSelect
I
I
A HIGHselects a write operationanda LOWselects a readoperationonportAfora LOW-to-HIGH
transitionofCLKA. The A0-A35outputs are inthe HIGHimpedance state whenW/RAis HIGH.
PortBWrite/
ReadSelect
A LOWselects a write operationanda HIGHselects a readoperationonportBfora LOW-to-HIGH
transitionofCLKB. The B0-B35outputs are inthe HIGHimpedance state when W/RBis LOW.
5
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
Rating
Commercial
–0.5to+4.6
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
(2)
VI
InputVoltageRange
V
VO(2)
OutputVoltageRange
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous OutputCurrent(VO =0toVCC)
ContinuousCurrentThroughVCC orGND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
IOUT
ICC
±50
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
VCC
VIH
Parameter
SupplyVoltage
Min.
3.15
2
Typ.
3.3
—
Max.
3.45
VCC+0.5
0.8
Unit
V
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
V
VIL
—
—
—
0
—
V
IOH
—
–4
mA
mA
°C
IOL
—
8
TA
—
70
NOTE:
1. Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3682
IDT72V3692
IDT72V36102
Commercial
tCLK = 10, 15 ns(2)
Symbol
Parameter
OutputLogic"1"Voltage
Test Conditions
Min.
Typ.
Max.
Unit
VOH
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
IOH = –4 mA
2.4
—
—
V
VOL
ILI
OutputLogic"0"Voltage
IOL = 8 mA
—
—
—
—
—
—
—
—
—
—
—
—
4
0.5
±5
±5
5
V
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
VI = VCC or 0
VO = VCC or 0
µA
µA
mA
mA
pF
ILO
(3)
ICC2
Standby Current (with CLKA and CLKB running)
StandbyCurrent(noclocksrunning)
InputCapacitance
VI = VCC - 0.2V or 0
(3)
ICC3
VI = VCC - 0.2V or 0
f = 1 MHz
5
(4)
CIN
—
—
(4)
COUT
OutputCapacitance
VO = 0,
f = 1 MHZ
8
pF
NOTES:
1. All typical values are at VCC = 3.3V, TA = 25°C.
2. Vcc = 3.3V ± 0.15V, TA = 0° to +70°; JEDEC JESD8-A compliant
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
6
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3682/72V3692/72V36102 with
CLKAandCLKBsettofS. Alldatainputs anddataoutputs changestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputs were
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
WithICC(f) takenfromFigure 1, the maximumpowerdissipation(PT)ofthese FIFOs maybe calculatedby:
2
PT = VCC x ICC(f) + Σ(CL x VCC X fo)
N
where:
N
CL
fo
=
=
=
number of outputs = 36
output capacitance load
switchingfrequencyofanoutput
100
90
VCC = 3.6V
80
70
60
VCC = 3.0V
VCC = 3.3V
fdata = 1/2 fS
TA
= 25°C
CL
= 0 pF
50
40
30
20
10
0
100
0
10
20
30
40
50
Clock Frequency MHz
60
70
90
80
4679 drw 04
fS
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGEANDOPERATINGFREE-AIRTEMPERATURE
(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C;JEDEC JESD8-A compliant)
IDT72V3682L10
IDT72V3692L10
IDT72V36102L10
IDT72V3682L15
IDT72V3692L15
IDT72V36102L15
Symbol
fS
Parameter
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
PulseDuration, CLKAandCLKBLOW
Min.
—
10
Max.
Min.
—
15
6
Max.
Unit
MHz
ns
100
—
—
—
—
66.7
—
tCLK
tCLKH
tCLKL
tDS
4.5
4.5
3
—
ns
6
—
ns
SetupTime, A0-A35before CLKA↑andB0-B35
beforeCLKB↑
4
—
ns
tENS1
tENS2
tRSTS
SetupTime,CSA andW/RA,before
4
3
5
—
—
—
4.5
4.5
5
—
—
—
ns
ns
ns
CLKA↑; CSB, and W/RB before CLKB↑
SetupTime, ENAandMBA, before
CLKA↑; ENB, and MBB before CLKB↑
Setup Time, RST1 orRST2 LOWbefore CLKA↑
(1)
orCLKB↑
tFSS
tFWS
tDH
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
SetupTime,FWFTbeforeCLKA↑
7.5
0
—
—
—
—
7.5
0
—
—
—
—
ns
ns
ns
ns
Hold Time, A0-A35 after CLKA
↑
and B0-B35 after CLKB
↑
0.5
0.5
1
tENH
HoldTime, CSA, W/RA, ENA, andMBAafterCLKA↑;
CSB, W/RB, ENB, andMBBafterCLKB↑
1
(1)
tRSTH
tFSH
Hold Time, RST1 or RST2 LOW after CLKA
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
Skew Time, between CLKA and CLKB for EFA/ORA,
EFB/ORB, FFA/IRA, and FFB/IRB
↑
or CLKB
↑
4
2
—
—
—
4
2
—
—
—
ns
ns
ns
tSKEW1(2)
↑
↑
7.5
7.5
tSKEW2(2,3) SkewTime,betweenCLKA↑andCLKB↑forAEA,
12
—
12
—
ns
AEB, AFA, and AFB
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
8
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C;JEDEC JESD8-A compliant)
IDT72V3682L10
IDT72V3692L10
IDT72V36102L10
IDT72V3682L15
IDT72V3692L15
IDT72V36102L15
Symbol
tA
Parameter
Min.
Max.
Min.
Max.
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B35
2
6.5
6.5
2
2
10
tPIR
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to
FFB/IRB
2
8
ns
tPOR
Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to
EFB/ORB
1
6.5
1
8
ns
tPAE
tPAF
tPMF
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
1
1
0
6.5
6.5
6.5
1
1
0
8
8
8
ns
ns
ns
PropagationDelayTime, CLKA↑ toMBF1 LOWor
MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
tPMR
tMDV
tPRF
PropagationDelayTime, CLKA↑toB0-B35(1) and
2
2
1
8
2
2
1
10
10
15
ns
ns
ns
CLKB↑toA0-A35(2)
Propagation Delay Time, MBA to A0-A35 valid and
MBBtoB0-B35Valid
6.5
10
PropagationDelayTime, RST1 LOWtoAEB LOW,AFA
HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW,
AFB HIGH, and MBF2 HIGH
tEN
tDIS
EnableTime,CSA andW/RALOWtoA0-A35Active
and CSB LOW and W/RB HIGH to B0-B35 Active
2
1
6
6
2
1
10
8
ns
ns
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance
and CSB HIGH or W/RB LOW to B0-B35 at high-impedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
9
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
readrequestnecessary. Subsequentwordsmustbeaccessedbyperforming
aformalreadoperation.
SIGNALDESCRIPTION
FollowingReset,thelevelappliedtotheFWFTinputtochoosethedesired
timingmodemustremainstaticthroughoutFIFOoperation.RefertoFigure2
(Reset)foraFirstWordFallThroughselecttimingdiagram.
RESET
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding
a LOW pulse to RST1 and RST2 simultaneously. Afterwards, the FIFO
memories of the IDT72V3682/72V3692/72V36102 are reset separately by
taking their Reset (RST1, RST2) inputs LOW for at least four port-A Clock
(CLKA)andfourport-BClock(CLKB)LOW-to-HIGHtransitions. TheReset
inputs can switch asynchronously to the clocks. A FIFO reset initializes the
internalreadandwritepointersandforcestheInputReadyflag(IRA,IRB)LOW,
theOutputReadyflag(ORA,ORB)LOW,theAlmost-Emptyflag(AEA,AEB)
LOW,andtheAlmost-Fullflag(AFA,AFB)HIGH. ResettingaFIFOalsoforces
theMailboxFlag(MBF1, MBF2)oftheparallelmailboxregisterHIGH. After
aFIFOisreset,itsInputReadyflagissetHIGHaftertwoclockcyclestobegin
normaloperation.
ALMOST-EMPTYFLAGANDALMOST-FULLFLAGOFFSETPROGRAMMING
Four registers in these devices are used to hold the offset values for the
Almost-EmptyandAlmost-Fullflags.TheportBAlmost-Emptyflag(AEB)Offset
registerislabeledX1andtheportAAlmost-Emptyflag(AEA)Offsetregisteris
labeledX2.TheportAAlmost-Fullflag(AFA)OffsetregisterislabeledY1and
theportBAlmost-Fullflag(AFB)OffsetregisterislabeledY2.Theindexofeach
register name corresponds to its FIFO number. The offset registers can be
loadedwithpresetvaluesduringtheresetofaFIFOortheycanbeprogrammed
from port A (see Table 1).
ALOW-to-HIGHtransitiononaFIFOReset(RST1,RST2)inputlatchesthe
value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and
Almost-Empty offset programming method. (For details see Table 1, Flag
Programming,andtheProgrammingtheAlmost-EmptyandAlmost-FullFlags
section). The relevantFIFOResettimingdiagramcanbe foundinFigure 2.
FS0andFS1functionthesamewayinbothIDTStandardandFWFTmodes.
— PRESET VALUES
ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisterswith
oneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselectinputs
mustbeHIGHduringtheLOW-to-HIGHtransitionofitsresetinput.Forexample,
toloadthepresetvalueof64intoX1andY1,FS0andFS1mustbeHIGHwhen
FlFO1Reset(RST1)returnsHIGH.FlagoffsetregistersassociatedwithFIFO2
are loaded with one of the preset values in the same way with FIFO2 Reset
(RST2)toggledsimultaneouslywithFIFO1Reset(RST1). Forpresetvalue
loadingtimingdiagram,seeFigure2.
FIRST WORD FALL THROUGH (FWFT)
AfterMasterReset,theFWFTselectfunctionisactive,permittingachoice
betweentwopossible timingmodes:IDTStandardmode orFirstWordFall
Through(FWFT)mode.OncetheReset(RST1,RST2)inputisHIGH,aHIGH
on the FWFT input during the next LOW-to-HIGH transition of CLKA (for
FIFO1)andCLKB(forFIFO2)willselectIDTStandardmode.Thismodeuses
theEmptyFlagfunction(EFA,EFB)toindicatewhetherornotthereareany
wordspresentintheFIFOmemory.ItusestheFullFlagfunction(FFA,FFB)
toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.In
IDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must
be requestedusinga formalreadoperation.
Once the Reset(RST1, RST2)inputis HIGH, a LOWonthe FWFT input
duringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)andCLKB(for
FIFO2)willselectFWFTmode.This mode uses the OutputReadyfunction
(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedataoutputs
(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)toindicate
whetherornottheFIFOmemoryhasanyfreespaceforwriting.IntheFWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodataoutputs,no
— PARALLEL LOAD FROM PORT A
ToprogramtheX1,X2,Y1,andY2registersfromportA,bothFlFOsshould
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transitionoftheResetinputs.Itisimportanttonotethatonceparallelprogramming
hasbeenselectedduringaMasterResetbyholdingbothFS0&FS1LOW,these
inputsmustremainLOWduringallsubsequentFIFOoperation.Theycanonly
be toggled HIGH when future Master Resets are performed and other
programmingmethodsaredesired.
Afterthisresetiscomplete,thefirstfourwritestoFIFO1donotstoredatain
theFIFOmemorybutloadtheoffsetregistersintheorderY1,X1,Y2,X2.The
portAdatainputsusedbytheoffsetregistersare(A10-A0),(A11-A0),or(A12-
A0) for the IDT72V3682, IDT72V3692, or IDT72V36102, respectively. The
TABLE 1 — FLAG PROGRAMMING
FS1
FS0
RST1
RST2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H
H
H
H
L
H
H
L
↑
X
↑
X
↑
X
↑
X
↑
X
↑
X
↑
↑
64
X
16
X
8
X
64
X
16
X
8
L
H
H
L
L
X
(3)
(3)
L
ParallelprogrammingviaPortA
ParallelprogrammingviaPortA
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
3. If parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
10
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
highestnumberedinputisusedasthemostsignificantbitofthebinarynumber LOW.TheB0-B35outputsareactivewhenCSB isLOWandW/RBisHIGH.
ineachcase. Validprogrammingvaluesfortheregistersrangesfrom1to16,380 Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
fortheIDT72V3682;1to32,764fortheIDT72V3692;and1to65,532forthe transitionofCLKBwhenCSBisLOW,W/RBisLOW,ENBisHIGH,MBBisLOW,
IDT72V36102. AfteralltheoffsetregistersareprogrammedfromportA,theport andFFB/IRBisHIGH.DataisreadfromFIFO1totheB0-B35outputsbyaLOW-
BFull/InputReadyflag(FFB/IRB)issetHIGH,andbothFIFOsbeginnormal to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENBisHIGH,
operation.SeeFigure3forrelevantoffsetregisterparallelprogrammingtiming MBB is LOW, and EFB/ORB is HIGH (see Table 3) . FIFO reads and writes
diagram.
onportBareindependentofanyconcurrentportAoperation.WriteandRead
cycle timing diagrams for Port B can be found in Figure 5 and 6.
FIFO WRITE/READ OPERATION
ThesetupandholdtimeconstraintstotheportClocksfortheportChipSelects
ThestateoftheportAdata(A0-A35)outputsiscontrolledbyportAChipSelect andWrite/Readselectsareonlyforenablingwriteandreadoperationsandare
(CSA)andportAWrite/Readselect(W/RA).TheA0-A35outputsareinthehigh- notrelatedtohigh-impedancecontrolofthedataoutputs.IfaportenableisLOW
impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35outputsare duringaclockcycle,theport’sChipSelectandWrite/Readselectmaychange
active when both CSA and W/RAare LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
statesduringthesetupandholdtimewindowofthecycle.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
transitionofCLKAwhenCSA is LOW,W/RAis HIGH,ENAis HIGH,MBAis thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe
LOW,andFFA/IRAisHIGH. DataisreadfromFIFO2totheA0-A35outputs LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand registersonlywhenareadisselectedusingtheport’sChipSelect,Write/Read
writesonportAareindependentofanyconcurrentportBoperation.Writeand select,Enable,andMailboxselect.
Read cycle timing diagrams for Port A can be found in Figure 4 and 7.
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause
TheportBcontrolsignalsareidenticaltothoseofportAwiththeexception theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe
thattheportBWrite/Readselect(W/RB)istheinverseoftheportAWrite/Read ReadClock. Thedatawordwillnotbeautomaticallysenttotheoutputregister.
select(W/RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe Instead, data residing in the FIFO's memory array is clocked to the output
portBChipSelect(CSB)andportBWrite/Readselect(W/RB).TheB0-B35 registeronlywhenareadisselected usingtheport’sChipSelect,Write/Read
outputsareinthehigh-impedancestatewheneitherCSBisHIGHorW/RBis select,Enable,andMailboxselect.
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
X
ENA
X
MBA
X
CLKA
Data A (A0-A35) I/O
High-Impedance
Input
Port Function
X
X
↑
None
None
H
L
X
L
H
H
L
Input
FIFO1write
Mail1write
L
H
H
H
↑
Input
L
L
L
L
X
↑
Output
None
L
L
H
L
Output
FIFO2 read
None
L
L
L
H
X
↑
Output
L
L
H
H
Output
Mail2 read (set MBF2 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
X
ENB
X
MBB
X
CLKB
Data B (B0-B35) I/O
High-Impedance
Input
Port Function
X
X
↑
None
None
L
L
X
L
L
H
L
Input
FIFO2write
Mail2write
L
L
H
H
↑
Input
L
H
L
L
X
↑
Output
None
L
H
H
L
Output
FIFO1 read
None
L
H
L
H
X
↑
Output
L
H
H
H
Output
Mail1 read (set MBF1 HIGH)
11
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
SYNCHRONIZED FIFO FLAGS
outputregister.ThestatemachinethatcontrolsanOutputReadyflagmonitors
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flopstages. a write pointer and read pointer comparator that indicates when the FIFO
This is done to improve flag signal reliability by reducing the probability of memorystatusisempty,empty+1,orempty+2.
metastable events when CLKA and CLKB operate asynchronously to one
InFWFTmode,fromthetimeawordis writtentoaFIFO,itcanbeshifted
another.EFA/ORA,AEA,FFA/IRA,andAFAaresynchronizedtoCLKA.EFB/ totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReady
ORB,AEB,FFB/IRB,andAFBaresynchronizedtoCLKB.Tables4and5show flagsynchronizingclock.Therefore,anOutputReadyflagisLOWifawordin
the relationshipofeachportflagtoFIFO1andFIFO2.
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntil
thethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simulta-
neouslyforcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFO
outputregister.
InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlagisLOW
ifawordinmemoryisthenextdatatobesenttotheFlFOoutputregisterand
twocycles oftheportClockthatreads datafromtheFIFOhavenotelapsed
sincethetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOW
untilthesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,
forcing the Empty Flag HIGH; only then can data be read.
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(ORA,
ORB)functionisselected.WhentheOutputReadyflagisHIGH,newdatais
presentintheFIFOoutputregister.WhentheOutputReadyflagisLOW,the
previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO
reads are ignored.
IntheIDTStandardmode,theEmptyFlag(EFA,EFB)functionisselected.
WhentheEmptyFlagisHIGH,dataisavailableintheFIFO’sRAMforreading
totheoutputregister.WhentheEmptyFlagisLOW,thepreviousdatawordis
presentinthe FIFOoutputregisterandattemptedFIFOreads are ignored.
TheEmpty/OutputReadyflagofaFIFOis synchronizedtotheportclock
thatreadsdatafromitsarray.ForboththeFWFTandIDTStandardmodes,
the FIFOreadpointeris incrementedeachtime a newwordis clockedtoits
TABLE 4 — FIFO1 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKB
Synchronized
to CLKA
(1,2)
Number of Words in FIFO
IDT72V3682(3)
IDT72V3692(3)
IDT72V36102(3)
EFB/ORB
AEB
L
AFA
FFA/IRA
0
1toX1
0
1toX1
0
1toX1
L
H
H
H
H
H
H
H
L
H
H
H
H
L
L
(X1+1)to[16,384-(Y1+1)]
(16,384-Y1)to16,383
16,384
(X1+1)to[32,768-(Y1+1)]
(32,768-Y1)to32,767
32,768
(X1+1)to[65,536-(Y1+1)]
(65,536-Y1)to65,535
65,536
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from
port A.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
TABLE 5 — FIFO2 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKA
Synchronized
to CLKB
(1,2)
Number of Words in FIFO
IDT72V3682(3)
IDT72V3692(3)
IDT72V36102(3)
EFA/ORA
AEA
L
AFB
FFB/IRB
0
0
0
L
H
H
H
H
H
H
H
L
H
H
H
H
L
1toX2
1toX2
1toX2
L
(X2+1)to[16,384-(Y2+1)]
(16,384-Y2)to16,383
16,384
(X2+1)to[32,768-(Y2+1)]
(32,768-Y2)to32,767
32,768
(X2+1)to[65,536-(Y2+1)]
(65,536-Y2)to65,535
65,536
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from
port A.
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.
12
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing ALMOST-FULL FLAGS (AFA, AFB)
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwritesdata
attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle toitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsawrite
canbethefirstsynchronizationcycle(seeFigures8through11forEFA/ORA pointer and read pointer comparator that indicates when the FIFO memory
andEFB/ORBtimingdiagrams).
statusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstateisdefined
bythecontentsofregisterY1forAFAandregisterY2forAFB.Theseregisters
are loaded with preset values during a FlFO reset or programmed from port
FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)
Thisisadualpurposeflag.InFWFTmode,theInputReady(IRAandIRB) A(seeAlmost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection).
function is selected. In IDT Standard mode, the Full Flag (FFA and FFB) AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthan
functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis or equal to (16,384-Y), (32,768-Y), or (65,536-Y) for the IDT72V3682,
HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory IDT72V3692,orIDT72V36102respectively. AnAlmost-FullflagisHIGHwhen
locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites the number of words in its FIFO is less than or equal to [16,384-(Y+1)],
to the FIFO are ignored.
[32,768-(Y+1)], or [65,536-(Y+1)] for the IDT72V3682, IDT72V3692, or
The Full/InputReadyflagofa FlFOis synchronizedtothe portclockthat IDT72V36102respectively. NotethatadatawordpresentintheFIFOoutput
writes datatoits array.ForbothFWFTandIDTStandardmodes,eachtime registerhas beenreadfrommemory.
awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclockare
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer requiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewleveloffill.
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2. Therefore,theAlmost-FullflagofaFIFOcontaining[16,384/32,768/65,536-
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready (Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
to be written to in a minimum of two cycles of the Full/Input Ready flag not elapsed since the read that reduced the number of words in memory to
synchronizingclock.Therefore,aFull/InputReadyflagisLOWiflessthantwo [16,384/32,768/65,536-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecond
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe LOW-to-HIGH transition of its synchronizing clock after the FIFO read that
next memory write location has been read. The second LOW-to-HIGH reducesthenumberofwordsinmemoryto[16,384/32,768/65,536-(Y+1)]. A
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets LOW-to-HIGHtransitionofanAlmost-Fullflagsynchronizingclockbeginsthe
the Full/InputReadyflagHIGH.
firstsynchronizationcycleifitoccursattimetSKEW2orgreaterafterthereadthat
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock reduces the number of words in memory to [16,384/32,768/65,536-(Y+1)].
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcyclecan nization cycle (see Figures 18 and 19).
bethefirstsynchronizationcycle(seeFigures12through15forFFA/IRAand
FFB/IRBtimingdiagrams).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
informationbetweenportAandportBwithoutputtingitinqueue.TheMailbox
select(MBA,MBB)inputschoosebetweenamailregisterandaFIFOforaport
datatransferoperation.ALOW-to-HIGHtransitiononCLKAwritesA0-A35data
tothemail1registerwhenaportAWriteisselectedbyCSA,W/RA,andENA
andwithMBAHIGH.ALOW-to-HIGHtransitiononCLKBwritesB0-B35data
tothemail2registerwhenaportBWriteisselectedbyCSB,W/RB,andENB
andwithMBBHIGH.Writingdatatoamailregistersetsitscorrespondingflag
(MBF1orMBF2)LOW.Attemptedwrites toamailregisterareignoredwhile
themailflagisLOW.
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthemail
registerwhentheportmailboxselectinputisHIGH.TheMail1RegisterFlag
(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhenaportBRead
isselectedbyCSB,W/RB,andENBandwithMBBHIGH.TheMail2Register
Flag(MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKAwhenaport
AreadisselectedbyCSA,W/RA,andENAandwithMBAHIGH.Thedatain
amailregisterremainsintactafteritisreadandchangesonlywhennewdata
iswrittentotheregister.FormailregisterandMailRegisterFlagtimingdiagrams,
see Figure 20 and 21.
ALMOST-EMPTY FLAGS (AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
datafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX1forAEBandregister
X2forAEA.TheseregistersareloadedwithpresetvaluesduringaFIFOreset
orprogrammedfromportA(seeAlmost-EmptyflagandAlmost-Fullflagoffset
programmingsection).AnAlmost-EmptyflagisLOWwhenitsFIFOcontains
Xorless words andis HIGHwhenits FIFOcontains (X+1)ormore words. A
data wordpresentinthe FIFOoutputregisterhas beenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel
offill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormorewords
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe
writethatfilledthememorytothe(X+1)level. AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO
writethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionofanAlmost-
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figures 16 and 17).
13
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
tRSTH
t
RSTS
t
FSS
t
FSH
RST1
FWFT
tFWS
0,1
FS1,FS0
FFA/IRA
tPIR
tPIR
tPOR
EFB/ORB
AEB
t
t
PRF
PRF
AFA
t
PRF
MBF1
4679 drw 05
NOTES:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
2. If FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where FWFT is LOW.
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)
CLKA
4
1
2
t
FSS
RST1,
RST2
t
FSH
0,0
FS1,FS0
tPIR
FFA/IRA
ENA
(1)
SKEW1
tENS2
tENH
t
tDH
tDS
A0 - A35
First Word to FIFO1
AFA Offset
AEB Offset
AFB Offset
AEA Offset
(Y1)
(X1)
(Y2)
(X2)
CLKB
1
2
tPIR
FFB/IRB
4679 drw 06
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(IDT Standard and FWFT Modes)
14
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
FFA/IRA
HIGH
tENS1
tENH
CSA
t
ENS1
t
ENH
ENH
ENH
W/RA
MBA
ENA
t
t
ENS2
t
tENS2
tENS2
tENH
tENS2
tENH
tDH
tDS
W1(1)
W2(1)
No Operation
A0 - A35
4679 drw 07
NOTE:
1. Written to FIFO1.
Figure 4. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
FFB/IRB HIGH
tENH
tENS1
CSB
t
ENH
t
ENS1
ENS2
W/RB
tENH
t
MBB
tENH
tENH
tENH
tENS2
tENS2
tENS2
ENB
tDH
t
DS
(1)
W2(1)
No Operation
B0 - B35
W1
4679 drw 08
NOTE:
1. Written to FIFO2.
Figure 5. Port B Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
15
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
EFB/ORB HIGH
CSB
W/RB
tENS2
MBB
tENH
tENH
tENH
tENS2
tENS2
ENB
No Operation
W2(1)
t
t
MDV
MDV
t
DIS
t
A
t
A
A
t
EN
EN
B0-B35
W1(1)
W2(1)
Previous Data
(IDT Standard Mode)
t
DIS
OR
tA
t
t
B0-B35
W3(1)
W1(1)
(FWFT Mode)
4679 drw 09
NOTE:
1. Read From FIFO1.
Figure 6. Port B Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKA
EFA/ORA HIGH
CSA
W/RA
MBA
ENA
t
ENS2
tENH
t
ENH
t
ENH
t
ENS2
t
ENS2
No Operation
W2(1)
t
MDV
t
DIS
DIS
t
A
t
A
t
EN
A0-A35
Previous Data
W1(1)
W2(1)
(Standard Mode)
t
t
MDV
t
A
OR
tA
t
EN
A0-A35
W3(1)
W1(1)
(FWFT Mode)
4679 drw 10
NOTE:
1. Read From FIFO2.
Figure 7. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
16
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
tENS2
tENH
MBA
tENS2
tENH
ENA
HIGH
IRA
tDH
tDS
A0 - A35
W1
t
CLK
(1)
tSKEW1
tCLKH
tCLKL
1
2
3
CLKB
tPOR
tPOR
ORB FIFO1Empty
CSB LOW
W/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
tA
B0 -B35
Old Data in FIFO1 Output Register
W1
4679 drw 11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
17
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
t
ENS2
t
ENH
ENH
MBA
t
tENS2
ENA
FFA
HIGH
tDS
tDH
A0-A35
W1
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
CLKB
1
2
tPOR
tPOR
FIFO1 Empty
LOW
EFB
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
tA
W1
B0-B35
4679 drw 12
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Figure 9. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
18
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
LOW
CSB
W/RB
tENS2
tENH
MBB
ENB
tENH
tENS2
IRB
HIGH
tDS
tDH
B0 - B35
W1
t
CLK
(1)
SKEW1
t
tCLKH
t
CLKL
1
2
3
CLKA
ORA
t
POR
tPOR
FIFO2 Empty
LOW
LOW
LOW
CSA
W/RA
MBA
tENS2
tENH
ENA
t
A
Old Data in FIFO2 Output Register
W1
A0 -A35
4679 drw 13
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 10. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
19
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
t
CLK
t
CLKL
t
CLKH
CLKB
LOW
LOW
CSB
W/RB
tENS2
tENH
MBB
ENB
tENS2
tENH
HIGH
FFB
tDH
tDS
W1
B0-B35
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
1
2
CLKA
tPOR
tPOR
EFA
FIFO2 Empty
LOW
LOW
CSA
W/RA
MBA
LOW
tENS2
tENH
ENA
tA
A0-A35
W1
4679 drw 14
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Figure 11. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
20
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
HIGH
ORB
tA
Previous Word in FIFO1 Output Register
SKEW1
Next Word From FIFO1
B0 -B35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKA
tPIR
tPIR
FIFO1 Full
LOW
IRA
CSA
W/RA
HIGH
tENH
tENS2
MBA
tENS2
tENH
ENA
A0 - A35
NOTE:
tDS
tDH
Write
4679 drw 15
To FIFO1
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 12. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
21
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
MBB
HIGH
LOW
tENS2
tENH
ENB
EFB
HIGH
tA
Previous Word in FIFO1 Output Register
Next Word From FIFO1
B0-B35
(1)
t
CLK tCLKL
tSKEW1
tCLKH
CLKA
1
2
tPIR
tPIR
FIFO1 Full
LOW
FFA
CSA
HIGH
W/RA
tENH
tENS2
MBA
tENS2
tENH
ENA
tDH
tDS
A0-A35
Write
4679 drw 16
To FIFO1
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
Figure 13. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
22
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOW
CSA
W/RA LOW
LOW
MBA
ENA
tENS2
tENH
HIGH
ORA
tA
Previous Word in FIFO2 Output Register
SKEW1
Next Word From FIFO2
A0 -A35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKB
IRB
tPIR
tPIR
FIFO2 FULL
LOW
CSB
LOW
W/RB
tENS2
tENH
MBB
ENB
tENS2
tENH
tDS
tDH
Write
B0 - B35
4679 drw 17
To FIFO2
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 14. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
23
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOW
LOW
LOW
CSA
W/RA
MBA
tENS2
tENH
ENA
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
A0-A35
(1)
tCLK
tSKEW1
tCLKH
tCLKL
CLKB
1
2
tPIR
tPIR
FIFO2 Full
LOW
FFB
CSB
W/RB LOW
t
ENS2
ENS2
t
ENH
MBB
ENB
t
t
ENH
tDS
tDH
Write
B0-B35
4679 drw 18
To FIFO2
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
Figure 15. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
CLKA
tENS2
tENH
ENA
(1)
tSKEW2
1
2
CLKB
t
PAE
t
PAE
AEB
X1 Words in FIFO1
(X1+1) Words in FIFO1
ENS2
t
tENH
ENB
4679 drw 19
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
Figure 16. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
24
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENS2
tENH
ENB
(1)
tSKEW2
1
CLKA
2
t
PAE
t
PAE
AEA
X2 Words in FIFO2
(X2+1) Words in FIFO2
ENS2
t
tENH
ENA
4679 drw 20
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
Figure 17. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
(1)
tSKEW2
1
2
CLKA
ENA
tENS2
tENH
t
PAF
t
PAF
(D-Y1) Words in FIFO1
[D-(Y1+1)] Words in FIFO1
AFA
CLKB
tENH
tENS2
ENB
4679 drw 21
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 16,384 for the IDT72V3682, 32,768 for the IDT72V3692, 65,536 for the IDT72V36102.
Figure 18. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
25
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
(1)
tSKEW2
1
2
CLKB
tENS2
tENH
ENB
AFB
t
PAF
t
PAF
(D-Y2) Words in FIFO2
[D-(Y2+1)] Words in FIFO2
CLKA
tENS2
tENH
ENA
4679 drw 22
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 16,384 for the IDT72V3682, 32,768 for the IDT72V3692, 65,536 for the IDT72V36102.
Figure 19. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
CLKA
t
ENH
t
ENS1
ENS1
CSA
W/RA
MBA
tENH
t
tENS2
tENH
tENS2
tENH
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENH
tENS2
t
MDV
tEN
t
PMR
tDIS
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
B0 - B35
4679 drw 23
Figure 20. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
26
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENH
tENS1
CSB
t
ENH
ENH
t
ENS1
ENS2
W/RB
t
t
MBB
ENB
tENH
tENS2
tDH
tDS
W1
B0 - B35
CLKA
t
PMF
t
PMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS2
t
MDV
tEN
t
PMR
tDIS
W1 (Remains valid in Mail 2 Register after read)
FIFO2 Output Register
A0 - A35
4679 drw 24
Figure 21. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
27
IDT72V3682/72V3692/72V361023.3VCMOSSyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
330
Ω
From Output
Under Test
30 pF (1)
510
Ω
PROPAGATION DELAY
LOAD CIRCUIT
3V
3V
Timing
Input
1.5V
High-Level
1.5V
Input
1.5V
1.5V
GND
GND
t
S
th
tW
3V
3V
Data,
Enable
Input
1.5V
1.5V
Low-Level
1.5V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5V
1.5V
t
PZL
GND
tPLZ
3V
GND
≈
3V
Input
1.5V
1.5V
1.5V
Low-Level
Output
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
In-Phase
Output
1.5V
1.5V
High-Level
Output
1.5V
t
PHZ
V
OL
≈ OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4679 drw 25
NOTE:
1. Includes probe and jig capacitance.
Figure 22. Load Circuit and Voltage Waveforms
28
ORDERING INFORMATION
IDT
XXXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
PF
Commercial (0°C to +70°C)
Thin Quad Flat Pack (TQFP, PN120-1)
10
15
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
Speed in Nanoseconds
L
72V3682
72V3692
72V36102
16,384 x 36 x 2
32,768 x 36 x 2
65,536 x 36 x 2
3.3V SyncBiFIFO
3.3V SyncBiFIFO
3.3V SyncBiFIFO
4679 drw 26
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
10/30/2000
03/27/2001
11/04/2003
pgs. 1, 2, 3, 6, 8, 9, 11 and 29.
pgs. 6 and 7.
pg. 1.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for TECH SUPPORT:
408-330-1753
e-mail:FIFOhelp@idt.com
www.idt.com
29
相关型号：
©2020 ICPDF网 联系我们和版权申明