IDT72V70810TF9 [IDT]
Digital Time Switch, PQFP64, STQFP-64;
| 型号： | IDT72V70810TF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Digital Time Switch, PQFP64, STQFP-64 电信 电信集成电路 |
| 文件： | 总22页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
1,024 x 1,024
IDT72V70810
64-pin Small Thin Quad Flatpack (STQFP)
3.3V Power Supply
Operating Temperature Range -40°C to +85°C
3.3V I/O with 5V Tolerant Inputs
FEATURES:
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1,024 x 1,024 channel non-blocking switching at 8.192 Mb/s
Per-channel variable or constant throughput delay
Automatic identification of ST-BUS®/GCI interfaces
Accepts 8 Serial Data Streams of 8.192 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel Processor Mode
DESCRIPTION:
The IDT72V70810 is a non-blocking digital switch that has a capacity of
1,024 x 1,024 channels at a serial bit rate of 8.192 Mb/s. Some of the main
features are: programmable stream and channel control, Processor Mode,
inputoffsetdelayandhigh-impedanceoutputcontrol.
Per-streaminputdelaycontrolis providedformanaginglarge multi-chip
switchesthattransportbothvoicechannelandconcatenateddatachannels.In
addition,inputstreamscanbeindividuallycalibratedforinputframeoffset.
Control interface compatible to Intel/Motorola CPUs
Connection memory block programming
Available in 64-pin Thin Plastic Quad Flatpack (TQFP) and
FUNCTIONALBLOCKDIAGRAM
RESET
VCC GND
ODE
Loopback
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
Output
MUX
Data Memory
Transmit
Serial Data
Streams
Receive
Serial Data
Streams
Connection
Memory
Internal
Registers
Timing Unit
Microprocessor Interface
DS/
RD
DTA
CLK F0i FE/
HCLK
WFPS
AS/ IM
ALE
A0-A7
CCO
CS R/W/
D8-D15/
AD0-AD7
WR
5710 drw01
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.TheST-BUS isatrademarkofMitelCorp.
DECEMBER 2004
1
2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5710/5
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
PIN 1
D13
48
GND
RX0
1
2
3
4
5
6
D12
47
D11
46
RX1
D10
45
D9
44
RX2
RX3
RX4
D8
43
42
41
RX5
GND
VCC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
7
RX6
8
RX7
9
40
39
38
37
36
F0i
10
11
12
13
14
15
16
FE/HCLK
GND
CLK
VCC
DNC
DNC
35
34
33
5710 drw02
TQFP 0.80mm pitch, 14mm x 14mm (PN64-1, order code: PF)
STQFP 0.50 pitch, 10mm x 10mm (PP64-1, order code: TF)
TOP VIEW
NOTES:
1. DNC - Do Not Connect.
2. All I/O pins are 5V tolerant.
2
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION
SYMBOL
NAME
I/O
DESCRIPTION
GND
Ground.
Vcc
Ground Rail.
Vcc
+3.3 Volt Power Supply.
TX0-7
TX Output 0 to 7
O
Serial data output stream. These streams have a data rate of 8.192 Mb/s.
(Three-state Outputs)
RX0-7
RX Input 0 to 7
Frame Pulse
I
I
Serial data input stream. These streams have a data rate of 8.192 Mb/s.
F0i
WhentheWFPSpinisLOW,thisinputacceptsandautomaticallyidentifiesframesynchronizationsignalsformatted
according to ST-BUS® and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame
pulse which conforms to WFPS formats.
FE/HCLK Frame Evaluation/
HCLK Clock
I
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK
(4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.
CLK
Clock
I
I
Serial clock for shifting data in/out on the serial streams (RX/TX 0-7). This input accepts a 16.384 MHz clock.
RESET
Device Reset
(Schmitt Trigger Input)
This input (active LOW) puts the IDT72V70810 in its reset state that clears the device internal counters, registers
and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a power
up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the
RESET pin must be held LOW for a minimum of 100ns to reset the device.
WFPS
A0-7
Wide Frame
Pulse Select
I
I
I
When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in
ST-BUS®/GCI mode.
Address 0-7
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
DS/RD
Data Strobe/Read
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with CS
to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This
active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus
operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
R/W / WR Read/Write / Write
I
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs.
CS
Chip Select
I
I
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70810.
AS/ALE Address Strobe or
Latch Enable
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
bus operation, connect this pin to ground.
IM
CPU Interface Mode
I
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
AD0-7
Address/Data Bus 0 to 7 I/O These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
D8-15
Data Bus 8-15
I/O These pins are the eight most significant data bits of the microprocessor port.
DTA
Data Transfer
Acknowledgment
O
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
CCO
ODE
Control Output
O
I
This is a 16.384 Mb/s output containing 2.048 bits per frame respectively. The level of each bit is determined
by the CCO bit in the connection memory. See External Drive Control Section.
Output Drive Enable
This is the output enable control for the TX0 to TX7 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-7 are in a high-impedance state. If this input is HIGH, the TX0-7
output drivers are enabled. However, each channel may still be put into a high-impedance state by using
the per channel control bit in the connection memory.
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IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
serialconverteronetime-slotbeforeitistobeoutput.Thisdatawillbeoutput
ontheTXstreamsineveryframeuntilthedataischangedbythemicroprocessor.
AstheIDT72V70810canbeusedinawidevarietyofapplications,thedevice
alsohas memorylocations tocontrolthe outputs basedonoperatingmode.
Specifically, the IDT72V70810provides five per-channelcontrolbits forthe
followingfunctions:processororconnectionmode,constantorvariabledelay,
enables/three-statetheTXoutputdriversandenables/disabletheloopback
function.Inaddition,oneofthesebitsallowstheusertocontroltheCCOoutput.
Ifanoutputchannelissettoahigh-impedancestatethroughtheconnection
memory,theTXoutputwillbeinahigh-impedancestateforthedurationofthat
channel.Inadditiontotheper-channelcontrol,allchannelsontheST-BUS®
outputscanbeplacedinahighimpedancestatebyeitherpullingtheODEinput
pinloworprogrammingtheOutputStand-By(OSB)bitintheinterfacemode
selectionregister.Thisactionoverridestheper-channelprogramminginthe
connectionmemorybits.
FUNCTIONALDESCRIPTION
The IDT72V70810 is capable of switching up to 1,024 x 1,024, 64 Kbit/s
PCMorNx64Kbit/schanneldata.Thedevicemaintainsframeintegrityindata
applications and minimum throughput delay for voice applications on a per
channelbasis.
TheserialinputstreamsoftheIDT72V70810haveabitrateof8.192Mb/s
andarearrangedin125mswideframes,whichcontain128channels.Thedata
ratesoninputandoutputstreamsareidentical.
InProcessorMode,themicroprocessorcanaccessinputandoutputtime-
slotsonaperchannelbasisallowingfortransferofcontrolandstatusinformation.
TheIDT72V70810automaticallyidentifiesthepolarityoftheframesynchroni-
zationinputsignalandconfigurestheserialstreamstoeitherST-BUS® orGCI
formats.
Withthevarietyofdifferentmicroprocessorinterfaces,IDT72V70810has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessorbasedenvironments:Non-multiplexedorMultiplexed.These
interfacesprovidecompatibilitywithmultiplexedandMotorolanon-multiplexed
buses. Thedevicecanalsoresolvedifferentcontrolsignalseliminatingtheuse
ofglue logicnecessarytoconvertthe signals (R/W/WR, DS/RD, AS/ALE).
Theframeoffsetcalibrationfunctionallowsuserstomeasuretheframeoffset
delay using a frame evaluation pin (FE). The input offset delay can be
programmedforindividualstreamsusinginternalframeinputoffsetregisters,see
Table 8.
The connection memory data can be accessed via the microprocessor
interface.Theaddressingofthedevicesinternalregisters,dataandconnection
memoriesisperformedthroughtheaddressinputpinsandtheMemorySelect
(MS)bitofthecontrolregister.Fordetailsondeviceaddressing,seeSoftware
ControlandControlRegisterbits description(Table 3and5).
SERIAL DATA INTERFACE TIMING
Themasterclockfrequencymustalwaysbetwicethedatarate.Forserial
dataratesof8.192Mb/s,themasterclock(CLK)mustbe16.384MHz.Theinput
andoutputstreamdatarateswillalwaysbeidentical.
TheIDT72V70810providestwodifferentinterfacetimingmodesST-BUS®/
GCIandWFP(wideframepulse). IftheWFPSpinishigh,theIDT72V70810
isinthewideframepulse(WFP)framealignmentmode.
In ST-BUS®/GCI mode, the input 8 KHz frame pulse can be in either
ST-BUS® orGCIformat.TheIDT72V70810automaticallydetectsthepresence
ofaninputframepulseandidentifiesitaseitherST-BUS® orGCI.InST-BUS®
format,everysecondfallingedgeofthemasterclockmarksabitboundaryand
thedataisclockedinontherisingedgeofCLK,threequartersofthewayinto
thebitcell,seeFigure7.InGCIformat,everysecondrisingedgeofthemaster
clockmarksthebitboundaryanddataisclockedinonthefallingedgeofCLK
at three quarters of the way into the bit cell, see Figure 8.
TheinternalloopbackallowstheTXoutputdatatobeloopedaroundtothe
RXinputsfordiagnosticpurposes.
AfunctionalBlockDiagramofthe IDT72V70810is showninFigure 1.
DATAANDCONNECTIONMEMORY
Thereceivedserialdatais convertedtoparallelformatbyinternalserial-
to-parallelconvertersandstoredsequentiallyinthedatamemory.The8KHz
inputframepulse(F0i)isusedtogeneratechannelandframeboundariesof
theinputserialdata. Dependingontheinterfacemodeselect(IMS)register,
the usable data memory may be as large as 1,024 bytes.
Datatobeoutputontheserialstreams(TX0-7)maycomefromeitherthe
data memory or connection memory. For data output from data memory
(connectionmode),addressesintheconnectionmemoryareused.Fordata
tobeoutputfromconnectionmemory,theconnectionmemorycontrolbitsmust
settheparticularTXoutputinProcessorMode. Onetime-slotbeforethedata
is tobe output, data fromeitherconnectionmemoryordata memoryis read
internally. Thisallowsenoughtimeformemoryaccessandparallel-to-serial
conversion.
WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING
WhenthedeviceisinWFPframealignmentmode,theCLKinputmustbe
at16.384MHz, the FE/HCLKinputis 4.096MHzandthe 8KHzframe pulse
isinST-BUS®format.ThetimingrelationshipbetweenCLK,HCLKandtheframe
pulse is shown in Figure 9.
Clockisrequiredfordataandconnectionmemoryaccess.
WhenWFPSpinishigh,theframealignmentevaluationfeatureisdisabled.
However,theframeinputoffsetregistersmaystillbeprogrammedtocompensate
forthevaryingframedelays ontheserialinputstreams.
CONNECTION AND PROCESSOR MODES
IntheConnectionMode,theaddressesoftheinputsourcedataforalloutput
channels are stored in the connection memory. The connection memory is
mappedinsuchawaythateachlocationcorrespondstoanoutputchannelon
theoutputstreams.Fordetailsontheuseofthesourceaddressdata(CABand
SABbits),seeTable10.Oncethesourceaddressbitsareprogrammedbythe
microprocessor,thecontentsofthedatamemoryattheselectedaddressare
transferredtotheparallel-to-serialconvertersandthenontoaTXoutputstream.
By having the each location in the connection memory specify an input
channel,multipleoutputscanspecifythesameinputaddress. Thiscanbea
powerfultoolusedforbroadcastingdata.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.F0i).
Althoughallinputdatacomesinatthesamespeed,delayscanbecausedby
variable path serial backplanes and variable path lengths which may be
implementedinlargecentralizedanddistributedswitchingsystems. Because
dataisoftendelayed,thisfeatureisusefulincompensatingfortheskewbetween
clocks.
Eachinputstreamcanhaveitsowndelayoffsetvaluebyprogrammingthe
frameinputoffsetregisters(FOR).Themaximumallowableskewis+4.5master
clock(CLK)periodsforwardwithresolutionof½clockperiod.Theoutputframe
In Processor Mode, the microprocessor writes data to the connection
memory. Eachlocationintheconnectionmemorycorrespondstoaparticular
outputstreamandchannelnumberandistransferreddirectlytotheparallel-to-
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IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
offsetcannotbeoffsetoradjusted.SeeFigure5,Table8and9fordelayoffset beoutputinthefollowingframe(channeln,framep+1).Thesameistrueifinput
programming.
channel n is switched to output channel n+1 or n+2. If the input channel n is
switchedtooutputchanneln+3,n+4,...,thenewoutputdatawillappearinthe
same frame. Table 1shows the possible delays forthe IDT72V70810inthe
variable delay mode.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
TheIDT72V70810providestheframeevaluation(FE)inputtodetermine
differentdatainputdelayswithrespecttotheframepulseF0i.
Ameasurementcycleisstartedbysettingthestartframeevaluation(SFE)
bitlowforatleastoneframe.WhentheSFEbitintheIMSregisterischanged
CONSTANT DELAY MODE (V/C BIT = 1)
Inthismode,frameintegrityismaintainedinallswitchingconfigurationsby
fromlowtohigh,theevaluationstarts.Twoframeslater,thecompleteframe makinguseofamultipledatamemorybuffer.Inputchanneldataiswritteninto
evaluation(CFE)bitoftheframealignmentregister(FAR)changesfromlow thedatamemorybuffers duringframenwillbereadoutduringframen+2.In
tohightosignalthatavalidoffsetmeasurementisreadytobereadfrombits0 theIDT72V70810,theminimumthroughputdelayachievableintheconstant
to 11 of the FAR register. The SFE bit must be set to zero before a new delaymodewillbeoneframe. SeeTable2forpossibledelaysinconstantdelay
measurementcyclestarted.
mode.
InST-BUS® mode,thefallingedgeoftheframemeasurementsignal(FE)
isevaluatedagainstthefallingedgeoftheST-BUS® framepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
SeeTable7&Figure4forthedescriptionoftheframealignmentregister.
This feature is not available when the WFP Frame Alignment mode is
enabled (i.e., when the WFPS pin is connected to VCC).
MICROPROCESSORINTERFACE
TheIDT72V70810providesaparallelmicroprocessorinterfaceformulti-
plexed or non-multiplexed bus structures. This interface is compatible with
Motorolanon-multiplexedandmultiplexedbuses.
IftheIMpinislowaMotorolanon-multiplexedbusshouldbeconnectedto
thedevice.IftheIMpinishigh,thedevicemonitorstheAS/ALEandDS/RDto
determinewhatmodetheIDT72V70810shouldoperatein.
MEMORYBLOCKPROGRAMMING
TheIDT72V70810providesuserswiththecapabilityofinitializingtheentire
connectionmemoryblockintwoframes.Tosetbits11to15ofeveryconnection
memorylocation,firstprogramthedesiredpatterninbits5to9oftheIMSregister.
The block programming mode is enabled by setting the memory block
program(MBP)bitofthecontrolregisterhigh.Whentheblockprogramming
enable(BPE)bitoftheIMSregisterissettohigh,theblockprogrammingdata
willbeloadedintothebits11to15ofeveryconnectionmemorylocation.The
otherconnectionmemorybits(bit0tobit10)areloadedwithzeros.Whenthe
memoryblockprogrammingiscomplete,thedeviceresetstheBPEbittozero.
IfDS/RDislowattherisingedgeofAS/ALE,thenthemode1multiplexed
timingisselected.IfDS/RDishighattherisingedgeofAS/ALE,thenthemode
2multiplexedbustimingisselected.
For multiplexed operation, the required signals are the 8-bit data and
address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch
enable(AS/ALE),Datastrobe/Read(DS/RD),Read/Write/Write(R/W/WR),
Chip select (CS) and Data transfer acknowledge (DTA). See Figure 12 and
Figure13formultiplexedparallelmicroporttiming.
FortheMotorolanon-multiplexedbus,therequiredsignalsarethe16-bit
data bus (AD0-AD7, D8-D15), 8-bitaddress bus (A0-A7)and4controllines
(CS,DS,R/WandDTA).SeeFigure14and15forMotorolanon-multiplexed
microporttiming.
The IDT72V70810 microport provides access to the internal registers,
connectionanddatamemories.Alllocationsprovideread/writeaccessexcept
forthe data memoryandthe frame alignmentregisterwhichare readonly.
LOOPBACKCONTROL
Theloopbackcontrol(LPBK)bitofeachconnectionmemorylocationallows
theTXoutputdatatobeloopedbackedinternallytotheRXinputfordiagnostic
purposes.
IftheLPBKbitishigh,theassociatedTXoutputchanneldataisinternally
loopedbacktotheRXinputchannel(i.e.,datafromTXnchannelmroutesto
the RXnchannelminternally);ifthe LPBKbitis low, the loopbackfeature is
disabled. Forproperper-channelloopbackoperation, thecontents offrame
delayoffsetregistersmustbesettozero.
MEMORYMAPPING
The address bus on the microprocessor interface selects the internal
registersandmemoriesoftheIDT72V70810.
IftheA7addressinputislow,thenA6throughA0areusedtoaddressthe
interfacemodeselection(IMS),control(CR),framealignment(FAR)andframe
inputoffset(FOR)registers(Table4).IftheA7ishigh,thenA6throughA0are
usedtoselect128locationscorrespondingtodatarateoftheST-BUS®.The
addressinputlinesandthestreamaddressbits(STA)ofthecontrolregisterallow
access to the entire data and connection memories. The control and IMS
registerstogethercontrolallthemajorfunctionsofthedevice,seeFigure3.
AsexplainedintheSerialDataInterfaceTimingandSwitchingConfigura-
tionssections,aftersystempower-up,theIMSregistershouldbeprogrammed
immediatelytoestablishthedesiredswitchingconfiguration.
Thedatainthecontrolregisterconsistsofthememoryblockprogramming
bit(MBP),thememoryselectbit(MS)andthestreamaddressbits(STA).As
explainedintheMemoryBlockProgrammingsection,theMBPbitallowsthe
entireconnectionmemoryblocktobeprogrammed. Thememoryselectbitis
used to designate the connection memory or the data Memory. The stream
addressbitsselectinternalmemorysubsectionscorrespondingtoinputoroutput
serialstreams.
DELAYTHROUGHTHEIDT72V70810
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesontheper-channelbasis.Forvoiceapplications,variablethroughputdelay
isbestasitensuresminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
informationismaintainedthroughtheswitch.
The delay through the device varies according to the type of throughput
delayselectedintheV/Cbitoftheconnectionmemory.
VARIABLE DELAY MODE (V/C BIT = 0)
Inthismode,thedelayisdependentonlyonthecombinationofsourceand
destination channels and is independent of input and output streams. The
minimumdelayachievableintheIDT72V70810isthreetime-slots.Iftheinput
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
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IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
The data in the IMS register consists of block programming bits (BPD0- thechanneladdressbit(CAB)oftheconnectionmemorydefinesthesource
BPD4),blockprogrammingenablebit(BPE),outputstandbybit(OSB)andstart information(streamandchannel)ofthetime-slotthatwillbeswitchedtotheoutput
frameevaluationbit(SFE).Theblockprogrammingandtheblockprogramming fromdatamemory.
enablebitsallowsuserstoprogramtheentireconnectionmemory(seeMemory
TheV/C(Variable/ConstantDelay)bitineachconnectionmemorylocation
BlockProgrammingsection).IftheODEpinislow,theOSBbitenables(ifhigh) allows theper-channelselectionbetweenvariableandconstantthroughput
ordisables(iflow)allST-BUS® outputdrivers.IftheODEpinishigh,thecontents delaymodes.
of the OSB bit is ignored and all TX output drivers are enabled.
IftheLPBKbitishigh,theassociatedTXoutputchanneldataisinternally
loopedbacktotheRXinputchannel(i.e.,RXnchannelmdatacomesfromthe
TXnchannelm). Ifthe LPBKbitis low, the loopbackfeature is disabled. For
properper-channelloopbackoperation,thecontentsoftheframedelayoffset
registersmustbesettozero.
CONNECTIONMEMORYCONTROL
TheCCOpinisa16.384Mb/soutput,whichcarries2,048bits.Thecontents
oftheCCObitofeachconnectionmemorylocationareoutputontheCCOpin
onceeveryframe. ThecontentsoftheCCObitsoftheconnectionmemoryare
transmittedsequentiallyontotheCCOpin(2bitcellsforeachbitinconnection INITIALIZATIONOFTHEIDT72V70810
memory) andaresynchronouswiththedataratesontheotherserialstreams.
TheCCObitis outputonechannelbeforethecorrespondingchannelonthe
serialstreams.
IftheODEpinortheOSBbitishigh,theOEbitofeachconnectionmemory
locationcontrols the outputdrivers-enables (ifhigh)ordisables (iflow). See
Table 4fordetail.
Afterpowerup,thestateoftheconnectionmemoryisunknown.Assuch,
theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe
ODEis low, the microprocessorcaninitialize the device, programthe active
paths,anddisableunusedoutputsbyprogrammingtheOEbitinconnection
memory. Oncethedeviceisconfigured,theODEpin(orOSBbitdepending
oninitialization)canbeswitched.
Theprocessorchannel(PC)bitoftheconnectionmemoryselectsbetween
ProcessorModeandConnectionMode. Ifhigh,thecontentsoftheconnection
memoryareoutputontheTXstreams. Iflow,thestreamaddressbit(SAB)and
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IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
CR 7 CR 6 CR 5 CR 4 CR 3 CR 2 CR 1 CR 0
Control Register
b
b
b
b
b
b
b
b
CR 4
b
1
0
The Control Register is only accessed when A7-A0
are all zeroed. When A7 =1, up to 128 bytes are
randomly accessable via A0-A6 at any one instant.
Of which stream these bytes (channels) are accessed
is determined by the state of CR 2 -CR 0.
b
b
Connection Memory
Data Memory
CR 2 CR 1 CR 0
Stream
b
b
b
0
1
2
3
4
5
6
7
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 127
Channel 127
Channel 127
Channel 127
Channel 127
Channel 127
Channel 127
Channel 127
0
0
0
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
10000000
External Address Bits A7-A0
10000001
10000010
11111111
5710 drw03
Figure 3. Addressing Internal Memories
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IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
TABLE1—VARIABLETHROUGHPUT TABLE2—CONSTANTTHROUGHPUT
DELAYVALUE DELAYVALUE
Delay for Constant Throughput Delay Mode
Delay for Variable Throughput Delay Mode
Input Rate
(m – output channel number)
(n – input channel number)
128 + (128 – n) + m time-slots
Input Rate
(m – output channel number)
(n – input channel number)
m < n
m = n, n+1, n+2
m > n+2
8.192Mb/s
8.192Mb/s 128–(n-m)time-slots m-n+128time-slots m-ntime-slots
TABLE 3 —INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
(1)
A7
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
.
1
1
0
0
.
0
0
0
0
0
0
0
.
1
1
0
0
.
0
0
0
0
1
0
0
.
1
1
0
0
.
0
0
1
1
0
0
0
.
1
1
0
0
.
0
1
0
1
0
0
1
.
0
1
0
1
.
ControlRegister,CR
InterfaceModeSelectionRegister,IMS
FrameAlignmentRegister,FAR
FrameInputOffsetRegister0,FOR0
FrameInputOffsetRegister1,FOR1
Ch0
Ch1
.
Ch30
Ch31
Ch32
Ch33
.
Ch62
Ch63
Ch64
Ch65
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
0
1
0
1
.
1
1
1
1
1
1
1
1
1
1
1
0
1
Ch126
Ch127
1
NOTE:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
TABLE 4 —OUTPUT HIGH IMPEDANCE CONTROL
OE bit in Connection
ODE pin
OSB bit in IMS
Register
TX Output Driver
Status
Memory
0
Don’tCare
Don’tCare
Per Channel
High-Impedance
1
1
1
1
0
0
1
1
0
1
1
0
High-Impedance
Enable
Enable
Enable
8
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
TABLE 5—CONTROL REGISTER (CR) BITS
Read/WriteAddress:
ResetValue:
00H,
0000H.
12
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
MBP MS
0
STA2 STA1 STA0
Bit
15-6
5
Name
Unused
Description
Mustbezerofornormaloperation.
MBP
When1,theconnectionmemoryblockprogrammingfeatureisreadyfortheprogrammingofConnection
(MemoryBlockProgram) Memoryhighbits,bit11tobit15.When0,this featureis disabled.
4
MS
When0,connectionmemoryisselectedforreadorwriteoperations.When1,thedatamemoryisselected
(MemorySelect)
forreadoperationsandconnectionmemoryisselectedforwriteoperations.
(Nomicroprocessorwriteoperationis allowedforthedatamemory.)
3
Unused
Mustbezerofornormaloperation.
2-0
STA2-0
(StreamAddressBits)
The binaryvalue expressedbythese bits refers tothe inputoroutputdata stream, whichcorresponds
tothesubsectionofmemorymadeaccessibleforsubsequentoperations.(STA2=MSB,STA0=LSB)
TABLE 6—INTERFACE MODE SELECTION (IMS) REGISTER BITS
Read/WriteAddress:
ResetValue:
01H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BPD4 BPD3 BPD2 BPD1 BPD0 BPE OSB SFE
1
0
Bit
Name
Description
15-10 Unused
Mustbezerofornormaloperation.
9-5
BPD4-0
(BlockProgrammingData)
These bits carrythe value tobe loadedintothe connectionmemoryblockwheneverthe memoryblock
programmingfeatureisactivated.AftertheMBPbitinthecontrolregisterissetto1andtheBPEbitis
setto1,thecontents ofthebits BPD4-0areloadedintobit15and11oftheconnectionmemory.Bit10to
bit0oftheconnectionmemoryaresetto0.
4
BPE
Azerotoonetransitionofthisbitenablesthememoryblockprogrammingfunction.TheBPEand
BPD4-0bits inthe IMSregisterhave tobe definedinthe same write operation. Once the BPEbitis set
HIGH,thedevicerequirestwoframestocompletetheblockprogramming.Aftertheprogrammingfunction
has finished,theBPEbitreturns tozerotoindicatetheoperationis completed. WhentheBPE=1, theBPE
or MBP can be set to 0 to abort to ensure proper operation. When BPE = 1, the other bit in the IMS register
mustnotbechangedfortwoframes toensureproperoperation.
(BeginBlockProgramming
Enable)
3
2
OSB
(OutputStandBy)
When ODE = 0 and OSB = 0, the output drivers of TX0 to TX7 are in high impedance mode. When
ODE= 0 and OSB = 1, the output driver of TX0 to TX7 function normally. When ODE = 1, TX0 to TX7
outputdriversfunctionnormally.
SFE
Azerotoone transitioninthis bitstarts the frame evaluationprocedure. Whenthe CFEbitinthe FAR
registerchangesfromzerotoone,theevaluationprocedurestops. Tostartanotherfameevaluation
cycle,setthisbittozeroforatleastoneframe.
(StartFrameEvaluation)
1-0
Unused
For normal operation, bit 1 = 1 and bit 0 = 0.
9
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
TABLE 7—FRAME ALIGNMENT REGISTER (FAR) BITS
Read/WriteAddress:
ResetValue:
02H,
0000H.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
Bit
15-13 Unused
Name
Description
Mustbezerofornormaloperation.
12
CFE
WhenCFE=1,theframeevaluationiscompletedandbitsFD10toFD0bitscontainsavalidframealignment
(CompleteFrameEvaluation) offset. This bitis resettozero, whenSFEbitinthe IMSregisteris changedfrom1to0.
11
FD11
(Frame Delay Bit 11)
The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)
or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
10-0 FD10-0
(Frame DelayBits)
The binaryvalue expressedinthese bits refers tothe measuredinputoffsetvalue. These bits are restto
zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
ST-BUS Frame
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16
Offset Value
FE Input
(FD[10:0] = 06
H)
(FD11 = 0, sample at CLK LOW phase)
GCI Frame
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
Offset Value
FE Input
(FD[10:0] = 09
H)
(FD11 = 1, sample at CLK HIGH phase)
5710 drw04
Figure 4. Example for Frame Alignment Measurement
10
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
TABLE 8— FRAME INPUT OFFSET REGISTER (FOR) BITS
Read/WriteAddress:
ResetValue:
03H for FOR0 register,
04H for FOR1 register,
0000H forallFORregisters.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
FOR0 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
FOR1 Register
Name(1)
Description
OFn2, OFn1, OFn0
(OffsetBits2,1&0)
These three bits define howlongthe serialinterface receivertakes torecognize andstore bit0fromthe RXinputpin:i.e., to
startanewframe.Theinputframeoffsetcanbeselectedto+4.5clockperiodsfromthepointwheretheexternalframepulse
inputsignalis appliedtothe F0i inputofthe device. See Figure 5.
DLEn
(DataLatchEdge)
ST-BUS® mode:
GCImode:
DLEn=0, ifclockrisingedge is atthe ¾pointofthe bitcell.
DLEn=1, ifwhenclockfallingedge is atthe ¾ofthe bitcell.
DLEn=0,ifclockfallingedgeis atthe¾pointofthebitcell.
DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.
NOTE:
1. n denotes an input stream number from 0 to 7.
11
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
TABLE 9—OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELAY BITS
(FD11,FD2-0)
MeasurementResultfrom
FrameDelayBits
Corresponding
OffsetBits
InputStream
Offset
FD11
FD2
0
FD1
0
FD0
0
OFn2
OFn1
OFn0
DLEn
Noclockperiodshift(Default)
+0.5clockperiodshift
+1.0clockperiodshift
+1.5clockperiodshift
+2.0clockperiodshift
+2.5clockperiodshift
+3.0clockperiodshift
+3.5clockperiodshift
+4.0clockperiodshift
+4.5clockperiodshift
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
ST-BUS F0i
CLK
RX Stream
Bit 7
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
Bit 7
offset = 0, DLE = 1
offset = 1, DLE = 1
Bit 7
RX Stream
RX Stream
Bit 7
denotes the 3/4 point of the bit cell
GCI F0i
CLK
RX Stream
Bit 0
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
RX Stream
RX Stream
Bit 0
offset = 0, DLE = 1
offset = 1, DLE = 1
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
5710 drw05
Figure 5. Examples for Input Offset Delay Timing
12
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
TABLE 10—CONNECTIONMEMORYBITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LPBK V/C
PC
CCO
OE
0
SAB2 SAB1 SAB0 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
Bit
Name
Description
15
LPBK
When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback
operations,setthedelayoffsetregisterbitsOFn[2:0]tozeroforthestreamswhichareintheloopbackmode.
(Per Channel Loopback)
14
V/C
This bitis usedtoselectbetweenthe variable (LOW)andconstantdelay(HIGH)mode ona
per-channelbasis.
(Variable/Constant
Throughput Delay)
13
PC
When1,thecontentsoftheconnectionmemoryareoutputonthecorrespondingoutputchannelandstream.
Onlythe lowerbyte (bit7–bit0)willbe outputtothe TXoutputpins. When0, the contents ofthe connection
memoryarethedatamemoryaddressoftheswitchedinputchannelandstream.
(ProcessorChannel)
12
11
10
CCO
This bitis outputonthe CCOpinone channelearly. The CCObitforstream0is outputfirst.
(ControlChannelOutput)
OE
This bitenables the TXoutputdrivers ona per-channelbasis. When1, the outputdriverfunctions
normally.When0,theoutputdriverisinahigh-impedancestate.
(OutputEnable)
Unused
Mustbezerofornormaloperation.
9,8,7(1) SAB2-0
(SourceStreamAddressBits)
6-0(1) CAB6-0
(SourceChannelAddressBits)
The binaryvalue is the numberofthe data streamforthe source ofthe connection.
The binary value is the number of the channel for the source of the connection.
NOTE:
1. If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel
and stream associated with this location.
13
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDDC OPERATING
CONDITIONS
Symbol Parameter
Min.
Max.
Unit
Symbol
VCC
Parameter
Min.
3.0
Typ.
Max. Units
VCC
Vi
SupplyVoltage
-0.3
5.0
5.5
20
V
V
Positive Supply
Input HIGH Voltage
InputLOWVoltage
3.6
Vcc
0.8
V
V
VoltageonDigitalInputs
CurrentatDigitalOutputs
StorageTemperature
GND -0.3
VIH
2.0
IO
mA
°C
W
VIL
GND
-40
V
TS
-65
+125
1
TOP
OperatingTemperature
Commercial
+85
°C
PD
PackagePowerDissapation
NOTE:
NOTE:
1.Voltagesarewithrespecttogroundunlessotherwisestated.
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
DCELECTRICALCHARACTERISTICS
Symbol
Characteristics
Min.
2.4
Typ.
30
Max.
45
Units
mA
µA
µA
pF
(1)
ICC
SupplyCurrent
IIL
IBL
InputLeakage(inputpins)
InputLeakage(I/Opins)
InputPinCapacitance
High-impedanceLeakage
OutputHIGHVoltage
OutputLOWVoltage
OutputPinCapacitance
15
50
CI
10
IOZ
VOH
VOL
CO
5
µA
V
0.4
10
V
pF
NOTE:
1. Outputs Unloaded.
Test Point
VCC
RL
Output
Pin
S1isopencircuitexceptwhentestingoutput
levelsorhighimpedancestates.
S2
S
1
CL
S2 is switched to VCC or GND when testing
outputlevelsorhighimpedancestates.
GND
GND
5710 drw06
Figure 6. Output Load
14
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK
Symbol
tFPW
tFPS
Characteristics
Frame Pulse Width (ST-BUS®, GCI)
Frame Pulse Setup time before CLK falling (ST-BUS® or GCI)
Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI)
Min.
26
Typ.
Max.
80
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bit rate = 8.192 Mb/s
5
tFPH
tCP
10
CLK Period
CLK Pulse Width HIGH
CLK Pulse Width LOW
Bit rate = 8.192 Mb/s
55
20
20
70
tCH
Bit rate = 8.192 Mb/s
Bit rate = 8.192 Mb/s
40
tCL
40
tr,tf
ClockRise/FallTime
195
5
10
tHFPW
tHFPS
tHFPH
tHCP
WideFramePulseWidth
Bit rate = 8.192 Mb/s
295
150
150
300
150
150
10
FramePulseSetupTimebeforeHCLKfalling
Frame Pulse Hold Time from HCLK falling
HCLK (4.096 MHz) Period
HCLK (4.096 MHz) Pulse Width HIGH
HCLK (4.096 MHz) Pulse Width LOW
HCLK Rise/Fall Time
10
Bit rate = 8.192 Mb/s
Bit rate = 8.192 Mb/s
Bit rate = 8.192 Mb/s
190
85
tHCH
tHCL
85
tHr,tHf
tDIF
-10
Delaybetweenfallingedge ofHCLKandfallingedge ofCLK
10
AC ELECTRICAL CHARACTERISTICS - SERIAL STREAMS (1)
Symbol
tSIS
Characteristics
Min.
0
Typ.
Max.
Unit
ns
Test Conditions
RXSetupTime
tSIH
RXHoldTime
10
ns
tSOD
TX Delay – Active to Active
30
40
ns
ns
CL = 30pF
CL = 200pF
tDZ
tZD
TX Delay – Active to High-Z
TX Delay – High-Z to Active
Output Driver Enable (ODE) Delay
CCO Output Delay
32
32
32
ns
ns
ns
RL = 1KΩ, CL = 200pF
RL = 1KΩ, CL = 200pF
RL = 1KΩ, CL = 200pF
tODE
tXCD
30
40
ns
ns
CL = 30pF
CL = 200pF
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
15
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
tFPW
F0i
tCH
tFPS
t
r
t
f
tFPH
tCL
tCP
CLK
tSOD
(1)
TX
RX
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
Bit 0, Last Ch
tSIH
tSIS
(1)
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
Bit 0, Last Ch
5710 drw07
NOTE:
1. last channel = ch 127.
Figure 7. ST-BUS® Timing when WFPS pin = 0.
tFPW
F0i
tCL
tCH
tFPH
tFPS
t
r
t
f
tCP
CLK
tSOD
Bit 7, Last Ch(1)
Bit 7, Last Ch(1)
TX
RX
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
tSIS
tSIH
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
5710 drw08
NOTE:
1. last channel = ch 127.
Figure 8. GCI Timing when WFPS pin = 0
16
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
tHFPW
tHFPS
tHFPH
F0i
tHCP
tHCH
tHCL
HCLK
4.096 MHz
tHr
t
Hf
t
tr
tf
tDIF
CP
tCL
tCH
CLK
16.384 MHz
tSOD
Bit 0, Ch 127
Bit 7, Ch 0
Bit 1, Ch 127
Bit 6, Ch 0
Bit 5, Ch 0
Bit 4, Ch 0
TX
RX
tSIH
t
SIS
Bit 5, Ch 0
Bit 6, Ch 0
Bit 7, Ch 0
Bit 1, Ch 127
Bit 0, Ch 127
Bit 4, Ch 0
5710 drw09
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Figure 9. WFP Bus Timing for High Speed Serial Interface (8.192 Mb/s), when WFPS pin = 1
CLK
(ST-BUSor
WFPS mode)
CLK
(GCI mode)
tDZ
VALID DATA
TX
TX
tZD
ODE
TX
VALID DATA
tODE
tODE
tXCD
VALID DATA
CCO
5710 drw11
5710 drw10
Figure 11. Output Driver Enable (ODE)
Figure 10. Serial Output and External Control
17
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL)
Symbol
tALW
tADS
Parameter
Min.
20
3
Typ.
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
ALE Pulse Width
AddressSetupfromALEfalling
Address HoldfromALEfalling
RD Active afterALEfalling
Data SetupfromDTA LOWonRead
CS Hold after RD/WR
tADH
3
tALRD
tDDR
3
5
CL = 150pF
tCSRW
tRW
5
RDPulseWidth(FastRead)
CS Setup from RD
45
0
tCSR
(1)
tDHR
DataHoldafterRD
10
45
3
20
CL = 150pF, RL = 1K
tWW
WRPulseWidth(FastWrite)
WRDelayafterALEfalling
CS Setup from WR
tALWR
tCSW
tDSW
tSWD
tDHW
tAKD
0
DataSetupfromWR(FastWrite)
ValidData DelayonWrite (SlowWrite)
DataHoldafterWR Inactive
AcknowledgmentDelay:
Reading/WritingRegisters
Reading/WritingMemory
AcknowledgmentHoldTime
20
122
5
43/43
220/210
22
ns
ns
ns
CL = 150pF
CL = 150pF
(1)
tAKH
CL = 150pF, RL = 1K
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
tALW
ALE
tADS
tADH
AD0-AD7
D8-D15
ADDRESS
DATA
tALRD
tCSRW
CS
tDHR
tCSR
tRW
RD
WR
tWW
tDHW
tCSW
tDSW
tAKH
tDDR
tALWR
tSWD
tAKD
DTA
5710 drw12
Figure 12. Multiplexed Bus Timing (Intel Mode)
18
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MULTIPLEXEDBUSTIMING(MOTOROLA)
Symbol
tASW
tADS
Parameter
Min.
20
3
Typ.
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
ALE Pulse Width
AddressSetupfromASfalling
Address HoldfromASfalling
Data SetupfromDTA LOWonRead
CS HoldafterDSfalling
tADH
3
tDDR
5
CL = 150pF
tCSH
0
tCSS
CS Setup from DS rising
DataHoldafterWrite
0
tDHW
tDWS
tSWD
tRWS
tRWH
5
DataSetupfromDS–Write(FastWrite)
ValidData DelayonWrite (SlowWrite)
R/W Setup from DS Rising
R/W Hold from DS Rising
DataHoldafterRead
20
122
20
60
5
(1)
tDHR
10
10
CL = 150pF, RL = 1K
tDSH
tAKD
DS Delay after AS falling
AcknowledgmentDelay:
Reading/WritingRegisters
Reading/WritingMemory
AcknowledgmentHoldTime
43/43
220/210
22
ns
ns
ns
CL = 150pF
CL = 150pF
(1)
tAKH
CL = 150pF, RL = 1K
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
tRWH
tRWS
R/W
tASW
tDSH
AS
tADS
tDHW
tSWD
tADH
tDWS
AD0-AD7
D8-D15
WR
ADDRESS
ADDRESS
DATA
tDHR
AD0-AD7
D8-D15
RD
DATA
tCSH
tCSS
CS
tDDR
tAKD
tAKH
DTA
5710 drw13
Figure 13. Multiplexed Bus Timing (Motorola Mode)
19
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MOTOROLANON-MULTIPLEXEDBUSMODE
Symbol
tCSS
Parameter
Min.
0
Typ.
Max.
Units
ns
Test Conditions
CS Setup from DS falling
R/WSetupfromDSfalling
AddressSetupfromDSfalling
CS Hold after DS rising
R/W Hold after DS Rising
Address HoldafterDSRising
DataSetupfromDTALOWonRead
DataHoldonRead
tRWS
tADS
10
2
ns
ns
tCSH
0
ns
tRWH
tADH
2
ns
2
ns
tDDR
2
ns
CL = 150pF
tDHR
10
5
20
ns
CL = 150pF, RL = 1K
tDSW
tSWD
tDHW
tAKD
DataSetuponWrite(FastWrite)
ValidData DelayonWrite (SlowWrite)
DataHoldonWrite
ns
122
ns
5
ns
AcknowledgmentDelay:
Reading/WritingRegisters
Reading/WritingMemory
AcknowledgmentHoldTime
43/43
220/210
22
ns
ns
ns
CL = 150pF
CL = 150pF
(1)
tAKH
CL = 150pF, RL = 1K
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
tCSS
tCSH
tCSS
tCSH
CS
tRWS
tRWH
tRWS
tRWH
R/W
tADH
tADH
tADS
tADS
A0-A7
VALID READ ADDRESS
VALID WRITE ADDRESS
tDSW
tDHR
VALID READ DATA
tDDR
tDHW
AD0-AD7/
D8-D15
VALID WRITE
DATA
tAKH
tAKD
tAKH
tAKD
DTA
5710 drw14
Figure 14. Motorola Non-Multiplexed Asyncronous Bus Timing
20
IDT72V708103.3VTIMESLOTINTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
COMMERCIALTEMPERATURERANGE
CLK GCI
CLK ST-BUS
t
DSS
tDSS
t
DSPW
DS
CS
tCSS
tCSS
tCSH
tCSH
tRWH
tRWS
tRWH
tRWS
R/W
tADH
tADH
tADS
tADS
VALID READ
ADDRESS
VALID WRITE
ADDRESS
A0-A7
tDHW
tSWD
tDHR
VALID
WRITE
DATA
VALID READ
DATA
AD0-AD7/
D8-D15
tDDR
t
CKAK
t
CKA
K
tAKH
tAKH
DTA
5710 drw15
Figure 15. Motorola Non-Multiplexed Syncronous Bus Timing
21
ORDERINGINFORMATION
IDT
XXXXXX
XX
X
Device Type
Package
Process/
Temperature
Range
Commercial (-40°C to +85°C)
BLANK
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Small Thin Quad Flat Pack (STQFP, PP64-1)
PF
TF
72V70810
1,024 x 1,024 3.3V Time Slot Interchange Digital Switch
5710 drw16
DATASHEETDOCUMENTHISTORY
5/02/2000
1/04/2001
1/25/2001
08/06/2001
03/24/2003
12/07/2004
pg.1
pgs. 4, 5, 10, 11, 14, 17, 19 and 20.
pgs. 14 and 20.
pg. 1
pg. 1
pgs. 4 and 7.
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22
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