IDT72V70840BC [IDT]
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH; 3.3伏时隙交换数字开关
| 型号： | IDT72V70840BC |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH |
| 文件： | 总21页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
IDT72V70840
4,096 x 4,096
•
•
Internal Loopback for testing
Available in 144-pin Thin Quad Flatpack (TQFP) and
144-pin Ball Grid Array (BGA) packages
Operating Temperature Range -40°C to +85°C
3.3V I/O with 5V tolerant inputs and TTL compatible outputs
ꢀEATURES:
•
•
•
•
•
32 serial input and output streams
4,096 x 4,096 channel non-blocking switching at 8.192 Mb/s
Accepts data streams at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
Per-channel Variable Delay Mode for low-latency applications
Per-channel Constant Delay Mode for frame integrity applica-
tions
•
•
DESCRIPTION:
•
•
•
•
•
Automatic identification of ST-BUS® and GCI serial streams
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel processor mode to allow microprocessor writes to
TXstreams
The IDT72V70840 has a non-blocking switch capacity of 1,024 x 1,024
channels at 2.048 Mb/s, 2,048 x 2,048 channels at 4.096 Mb/s, and 4,096 x
4,096channelsat8.192Mb/s. With32inputsand32outputs,programmable
per stream control, and a variety of operating modes the IDT72V70840 is
designed for the TDM time slot interchange function in either voice or data
applications.
•
•
•
Direct microprocessor access to all internal memories
Memory block programming for quick set-up
IEEE-1149.1 (JTAG) Test Port
Some of the main features of the IDT72V70840 are low power 3.3 Volt
operation,automaticST-BUS®/GCIsensing,memoryblockprogramming,
simplemicroprocessorinterface,onecycledirectinternalmemoryaccesses,
ꢀUNCTIONAL BLOCK DIAGRAM
Vcc GND
RESET
TRST
TMS TDI
TDO TCK
ODE
Test Port
Loopback
RX0
RX1
TX0
TX1
TX2
RX2
RX3
TX3
RX4
TX4
RX5
TX5
RX6
TX6
RX7
RX8
TX7
TX8
Output
MUX
RX9
TX9
RX10
RX11
RX12
RX13
RX14
RX15
RX16
RX17
RX18
RX19
RX20
RX21
RX22
RX23
RX24
RX25
RX26
RX27
RX28
RX29
RX30
RX31
TX10
TX11
TX12
TX13
TX14
TX15
TX16
TX17
TX18
TX19
TX20
TX21
TX22
TX23
TX24
TX25
TX26
TX27
TX28
TX29
TX30
TX31
Data Memory
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Connection
Memory
Internal
Registers
Timing Unit
Microprocessor Interface
5715 drw01
F0i
DS
CS
DTA
CLK
FE/ WFPS
HCLK
R/W A0-A13
D0-D15
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS isatrademarkofMitelCorp.
JANUARY 2002
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5715/3
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
PIN CONꢀIGURATIONS
A1 BALL PAD CORNER
A
RX0
CLK
F0i
RX1
ODE
RX3
RX2
RESET
TDI
RX6
RX5
RX4
GND
VCC
VCC
VCC
VCC
D15
D9
TX1
TX0
RX7
VCC
GND
GND
GND
GND
VCC
D6
TX4
TX3
TX2
VCC
GND
GND
GND
GND
VCC
D3
TX7
TX6
TX5
VCC
GND
GND
GND
GND
VCC
D0
RX10
RX9
RX8
VCC
GND
GND
GND
GND
VCC
TX29
TX30
TX31
8
RX12
RX13
RX11
VCC
VCC
VCC
VCC
VCC
GND
TX26
TX27
TX28
9
RX15
RX14
TX8
TX10
TX9
TX11
TX12
TX14
RX17
B
C
FE/HCLK
WFPS
TCK
TX13
RX16
RX20
RX23
TX17
TX20
RX24
RX25
RX28
RX31
11
D
E
TMS
TD0
DS
TX15
RX19
RX22
TX16
TX19
TX22
RX27
TX24
TX25
10
TRST
R/W
A2
RX21
RX18
TX18
TX21
TX23
RX26
RX29
RX30
F
CS
G
A0
A3
A1
A4
H
J
A5
A6
A7
A8
K
L
DTA
A9
A10
A12
D14
2
A11
A13
1
D12
D13
3
D4
D11
D10
4
D7
D8
5
D1
D2
7
M
D5
6
12
5715 drw 02
NOTE:
1. All I/O pins are 5V tolerant except for TMS, TDI and TRST.
BGA: 1mm pitch, 13mm x 13mm (BC144-1, order code: BC)
TOP VIEW
2
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
PINCONꢀIGURATIONS(CONTINUED)
109
V
CC
72
71
TX11
TX24
TX25
GND
TX26
TX27
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
TX10
GND
TX9
70
69
TX8
68
67
66
65
V
CC
RX15
RX14
RX13
RX12
RX11
RX10
RX9
RX8
GND
TX7
VCC
TX28
TX29
GND
TX30
TX31
V
D0
D1
64
63
62
61
60
59
58
57
CC
GND
D2
D3
V
D4
D5
GND
D6
TX6
56
55
54
53
52
51
V
CC
CC
TX5
TX4
GND
TX3
TX2
50
49
48
47
46
45
V
CC
D7
TX1
TX0
GND
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
VCC
D08
D09
GND
D10
D11
V
D12
D13
44
43
42
41
40
138
139
140
141
142
143
144
CC
GND
D14
D15
39
38
37
V
CC
5715 drw 03
NOTE:
1. All I/O pins are 5V tolerant except for TMS, TDI and TRST.
TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA)
TOP VIEW
3
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION
SYMBOL
GND
NAME
I/O
DESCRIPTION
Ground.
VCC
Ground Rail.
VCC
+3.3 Volt Power Supply.
TX0-31
TX Output 0 to 31
O
Serial data output stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
(Three-state Outputs)
RX0-31 RX Input 0 to 31
F0i Frame Pulse
I
I
Serial data input stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUS® and GCI specifications.
FE/HCLK Frame Evaluation/
HCLK Clock
I
I
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the
HCLK (4.096 MHZ clock) is required for frame alignment in the wide frame pulse (WFP) mode.
CLK
Clock
Serial clock for shifting data in/out on the serial streams (RX/TX 0-31). This input accepts a 4.096 MHz clock
when data streams @ 2.048 Mb/s, a 8.192 MHz clock when data streams @ 4.096 Mb/s, a 16.384 MHz
clock when data streams @ 8.192 Mb/s.
TMS
TDI
Test Mode Select
Test Serial Data In
Test Serial Data Out
I
I
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
TDO
O
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.
TCK
Test Clock
Test Reset
I
I
Provides the clock to the JTAG test logic.
TRST
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
to ensure that the IDT72V70840 is in the normal functional mode.
RESET
Device Reset
(Schmitt Trigger Input)
I
This input (active LOW) puts the IDT72V70840 in its reset state that clears the device internal counters,
registers and brings TX0-31 and microport data outputs to a high-impedance state. The time constant for a
power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation,
the RESET pin must be held LOW for a minimum of 100ns to reset the device.
WFPS
Wide Frame Pulse Select
I
When 1, enables the wide frame pulse (SFP) Frame Alignment interface. When 0, the device operates in
ST-BUS® /GCI mode.
DS
R/W
CS
A0-13
D0-15
DTA
Data Strobe
I
I
I
I
This active LOW input works in conjunction with CS to enable the read and write operations.
This input controls the direction of the data bus lines during a microprocessor access.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70840.
These pins allow direct access to Connection Memory, Data Memory and internal control registers.
Read/Write
Chip Select
Address Bus 0 to 13
Data Bus 0-15
I/O These pins are the data bits of the microprocessor port.
Data Transfer
Acknowledgment
O
This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
ODE
Output Drive Enable
I
This is the output enable control for the TX0-31 serial outputs. When ODE input is LOW and the OSB bit of
the CR register is LOW, TX0-31 are in a high-impedance state. If this input is HIGH, the TX0-31 output
drivers are enabled. However, each channel may still be put into a high-impedance state by using the per
channel control bit in the connection memory.
4
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
SERIAL DATA INTERFACE TIMING
DECRIPTION(CONTINUED)
Themasterclockfrequencymustalwaysbetwicethedatarate,e.g.fora
serialdataratesof2.048Mb/s,themasterclock(CLK)mustbeat4.096MHz.
The input and output stream data rates will always be identical. See control
registerbitsDR1-0description(Table5)fordataandclockrateselections.
TheIDT72V70840providestwodifferentinterfacetimingmodes,ST-BUS®
orGCI.TheIDT72V70840automaticallydetectsthepresenceofaninputframe
pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® format, every
secondfallingedgeofthemasterclockmarks abitboundaryandthedatais
clockedinontherisingedgeofCLK,threequartersofthewayintothebitcell.
In GCI format, every second rising edge of the master clock marks the bit
boundaryanddata is clockedinonthe fallingedge ofCLKatthree quarters
ofthewayintothebitcell.
JTAGTestAccessPort(TAP)andperstreamprogrammableinputoffsetdelay,
variableorconstantthroughputmodes,internalloopback,outputenable,and
ProcessorMode.
The IDT72V70840 is capable of switching up to 4,096 x 4,096 channels
withoutblocking. Designedtoswitch64Kbit/sPCMorNx64Kbit/sdata,the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delay for voice applications on a per channel basis.
The 32 serial input streams (RX) of the IDT72V70840 can be run up to
8.192Mb/sallowing128channelsper125µsframe.Thedataratesontheoutput
streams(TX)areidenticaltothoseontheinputstream.
Withtwomainoperatingmodes,ProcessorModeandConnectionMode,
theIDT72V70840caneasilyswitchdatafromincomingserialstreams(Data
Memory) or from the controlling microprocessor (Connection Memory). As
controlandstatusinformationiscriticalindatatransmission,theProcessorMode
isespeciallyusefulwhentherearemultipledevicessharingtheinputandoutput
streams.
Withdatacomingfrommultiplesourcesandthroughdifferentpaths,data
enteringthedeviceisoftendelayed. Tohandlethisproblem,theIDT72V70840
hasaframeevaluationfeaturetoallowindividualstreamstobeoffsetfromthe
framepulseinhalfclock-cycleintervalsupto+4.5clockcycles.
The IDT72V70840 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface andautomaticST-BUS®/GCIsensingtoshorten setuptime, aidin
debuggingandeaseuseofthedevicewithoutsacrificingcapabilities.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.F0i).
Althoughallinputdatacomesinatthesamespeed,delayscanbecausedby
variable path serial backplanes and variable path lengths which may be
implementedinlargecentralizedanddistributedswitchingsystems.Because
dataisoftendelayedthisfeatureisusefulincompensatingfortheskewbetween
clocks.
Eachinputstreamcanhaveitsowndelayoffsetvaluebyprogrammingthe
frameinputoffsetregisters(FOR,Table8).Themaximumallowableskewis
+4masterclock(CLK)periodsforwardwitharesolutionof1/2clockperiod.The
outputframeoffsetcannotbeoffsetoradjusted.
ꢀUNCTIONALDESCRIPTION
DATAANDCONNECTIONMEMORY
AlldatathatcomesinthroughtheRXinputsgothroughaserial-to-parallel
conversionbeforebeingstoredintointernalDataMemory. The8KHzframe
pulse (F0i) is used to mark the 125µs frame boundaries and to sequentially
addresstheinputchannelsinDataMemory.
DataoutputontheTXstreamsmaycomefromeithertheSerialInputStreams
(DataMemory)orfromthemicroprocessor(ConnectionMemory). Inthecase
thatRXinputdataistobeoutput,theaddressesinconnectionmemoryareused
tospecifyastreamandchanneloftheinput.Theconnectionmemoryissetup
in such a way that each location corresponds to an output channel for each
particularstream. Inthatway, morethanonechannelcanoutputthesamedata.
In Processor Mode, the microprocessor writes data to the connection
memorylocationscorrespondingtothestreamandchannelthatistobeoutput.
Thelowerhalf(8leastsignificantbits)oftheconnectionmemoryisoutputevery
frameuntilthemicroprocessorchangesthedataormodeofthechannel. By
usingthisProcessorModecapability,themicroprocessorcanaccessinputand
outputtime-slotsonaperchannelbasis.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
TheIDT72V70840providestheframeevaluation(FE)inputtodetermine
differentdatainputdelayswithrespecttotheframepulseF0i.
Ameasurementcycleisstartedbysettingthestartframeevaluation(SFE)
bitlowforatleastoneframe.WhentheSFEbitintheControlRegisterischanged
fromlowtohigh,theevaluationstarts.Twoframeslater,thecompleteframe
evaluation(CFE)bitoftheframealignmentregister(FAR)changesfromlow
tohightosignalthatavalidoffsetmeasurementisreadytobereadfrombits0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurementcycleisstarted.
InST-BUS® mode,thefallingedgeoftheframemeasurementsignal(FE)
isevaluatedagainstthefallingedgeoftheST-BUS® framepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
SeeTable7andFigure1forthedescriptionoftheframealignmentregister.
MEMORYBLOCKPROGRAMMING
TheIDT72V70840providesuserswiththecapabilityofinitializingtheentire
Thefourmostsignificantbitsoftheconnectionmemoryareusedtocontrol connectionmemoryblockintwoframes.Tosetbits12to15ofeveryconnection
per channel functions of the out put streams. Specifically, there are bits for memorylocation,firstprogramthedesiredpatterninbits5to8oftheControl
Processor or Connection mode, Constant or Variable delay, enables or Register.
disablesofoutputdrivers,andcontrolsfortheLoopbackfunction.
The block programming mode is enabled by setting the memory block
IftheperchannelOEissettozero,onlythatparticularchannel(8-bits)will program(MBP)bitofthecontrolregisterhigh.Whentheblockprogramming
beinthehigh-impedancestate. Ifhowever,theODEinputpinislowortheOutput enable(BPE)bitoftheControlRegisterissettohigh,theblockprogramming
StandbyBit(OSB)intheControlRegisteris low,alloftheoutputs willbeina datawillbeloadedintothebits12to15ofeveryconnectionmemorylocation.
high-impedancestateevenifaparticularchannelinconnectionmemoryhas Theotherconnectionmemorybits(bit0tobit11)areloadedwithzeros.When
enabledtheoutputforthatchannel. Inotherwords,theODEpinandOSBcontrol thememoryblockprogrammingiscomplete,thedeviceresetstheBPEbitto
bitare masteroutputenables forthe device (Table 3).
zero.
5
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
LOOPBACKCONTROL
MEMORYMAPPING
The address bus on the microprocessor interface selects the internal
Theloopbackcontrol(LPBK)bitofeachconnectionmemorylocationallows
theTXoutputdatatobeloopedbackedinternallytotheRXinputfordiagnostic registersandmemoriesoftheIDT72V70840.
purposes. Thetwomostsignificantbitsoftheaddressselectbetweentheregisters,Data
IftheLPBKbitishigh,theassociatedTXoutputchanneldataisinternally Memory,andConnectionMemory. IfA13andA12areHIGH,A11-A0areused
loopedbacktotheRXinputchannel(i.e.,datafromTXnchannelmroutesto toaddresstheDataMemory. IfA13isHIGHandA12isLOW,A11-A0areused
the RXn channel m internally); if the LPBK bit is low, the loopback feature is toaddressConnectionMemory. IfA13isLOWandA12isHIGHA11-A0are
disabled. Forproperper-channelloopbackoperation, thecontents offrame usedtoselecttheControlRegister,FrameAlignmentRegister,andFrameOffset
delayoffsetregistersmustbesettozero.
Registers. See Table 4formappings.
AsexplainedintheSerialDataInterfaceTimingandSwitchingConfigura-
tions sections, after system power-up, the Control Register should be pro-
grammedimmediatelytoestablishthedesiredswitchingconfiguration.
ThedataintheControlRegisterconsistsoftheMemoryBlockProgramming
bit(MBP),theBlockProgrammingData(BPE)bits,theBeginBlockProgram-
mingEnable(BPE),theOutputStandBy,StartFrameEvaluation,andDataRate
Selectbits. AsexplainedintheMemoryBlockProgrammingsection,theBPE
begins the programming if the MBP bit is enabled. This allows the entire
connectionmemoryblocktobeprogrammedwiththeBlockProgrammingData
bits. IftheODEpinis low,theOSBbitenables (ifhigh)ordisables (iflow)all
TXoutputdrivers.IftheODEpinishigh,thecontentsoftheOSBbitisignored
and all TX output drivers are enabled.
DELAYTHROUGHTHEIDT72V70840
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesonaper-channelbasis.Forvoiceapplications,variablethroughputdelay
isbestasitensureminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
informationismaintainedthroughtheswitch.
The delay through the device varies according to the type of throughput
delayselectedintheV/Cbitoftheconnectionmemory.
VARIABLE DELAY MODE (V/C BIT = 0)
CONNECTIONMEMORYCONTROL
Inthismode,thedelayisdependentonlyonthecombinationofsourceand
destination channels and is independent of input and output streams. The
minimumdelayachievableintheIDT72V70840isthreetime-slots.Iftheinput
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
beoutputinthefollowingframe(channeln,framep+1).Thesameistrueifthe
inputchannelnisswitchedtooutputchanneln+1orn+2.Iftheinputchannel
nisswitchedtooutputchanneln+3,n+4,...,thenewoutputdatawillappearin
thesameframe.Table2showsthepossibledelaysfortheIDT72V70840inthe
variable delay mode.
IftheODEpinortheOSBbitishigh,theOEbitofeachconnectionmemory
locationcontrols the outputdrivers-enables (ifhigh)ordisables (iflow). See
Table 3fordetail.
TheProcessorChannel(PC)bitoftheConnectionMemoryselectsbetween
ProcessorModeandConnectionMode. Ifhigh,thecontentsoftheConnection
MemoryareoutputontheTXstreams. Iflow,theStreamAddress Bit(SAB)
and the Channel Address Bit (CAB) of the Connection Memory defines the
sourceinformation(streamandchannel)ofthetime-slotthatwillbeswitchedto
theoutputfromDataMemory.
AlsointheConnectionMemoryis theV/C(Variable/ConstantDelay)bit.
EachConnectionMemorylocationallowstheper-channelselectionbetween
variableandconstantthroughputdelaymodes.
IftheLPBKbitishigh,theassociatedTXoutputchanneldataisinternally
loopedbacktotheRXinputchannel(i.e.,RXnchannelmdatacomesfromthe
TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For
properper-channelloopbackoperation,thecontentsoftheframedelayoffset
registersmustbesettozero.
CONSTANT DELAY MODE (V/C BIT = 1)
Inthismode,frameintegrityismaintainedinallswitchingconfigurationsby
makinguseofamultipledatamemorybuffer.Inputchanneldataiswritteninto
thedatamemorybuffers duringframenwillbereadoutduringframen+2.In
theIDT72V70840,theminimumthroughputdelayachievableintheconstant
delaymodewillbeoneframe.Forexample,wheninputtime-slot31isswitched
tooutputtime-slot0.Themaximumdelayof94time-slotsofdelayoccurswhen
time-slot0inaframeisswitchedtotime-slot31intheframe.
INITIALIZATIONOꢀTHEIDT72V70840
Afterpowerup,thestateoftheconnectionmemoryisunknown.Assuch,
theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe
ODEis low, the microprocessorcaninitialize the device, programthe active
paths,anddisableunusedoutputsbyprogrammingtheOEbitinconnection
memory. Oncethedeviceisconfigured,theODEpin(orOSBbitdepending
oninitialization)canbeswitched.
MICROPROCESSORINTERꢀACE
TheIDT72V70840’smicroprocessorinterfacelookslikeastandardRAM
interfacetoimproveintegrationintoasystem. Witha12-bitaddressbusand
a16-bitdatabus,readandwritesaremappeddirectlyintoDataandConnection
memories and require only one cycle to access. By allowing the internal
memoriestoberandomlyaccessedinonecycle,thecontrollingmicroprocessor
has more time tomanage otherperipheraldevices andcanmore easilyand
quicklygatherinformationandsetuptheswitchpaths.
Table4showsthemappingoftheaddressesintointernalmemoryblocks
andTable5showstheControlRegisterinformation.
6
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE1CONSTANT THROUGHPUT
DELAYVALUE
Delay for Constant Throughput Delay Mode
InputRate
(m – output channel number)
(n – input channel number)
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
32 + (32 – n) +m time-slots
64 + (64 – n) +m time-slots
128 + (128 – n) +m time-slots
TABLE 2 VARIABLE THROUGHPUT DELAY VALUE
Delay for Variable Throughput Delay Mode
InputRate
(m – output channel number; n – input channel number)
m < n
m = n, n+1, n+2
(m-n+32)time-slots
(m-n+64)time-slots
(m-n+128)time-slots
m > n+2
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
32–(n-m)time-slots
64–(n-m)time-slots
128–(n-m)time-slots
(m-n)time-slots
(m-n)time-slots
(m-n)time-slots
TABLE 3 OUTPUT HIGH IMPEDANCE CONTROL
OE bit in Connection
Memory
ODE pin
OSB bit in CR
Register
TX Stream Output
Status
0
Don’tCare
Don’tCare
PerChannel
High-Impedance
1
1
1
1
0
0
1
1
0
1
0
1
High-Impedance
Enable
Enable
Enable
TABLE 4 INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
A13
A12 A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R/W
Location
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
STA4
STA3 STA2 STA1 STA0
STA3 STA2 STA1 STA0
CH6 CH5
CH6 CH5
CH4
CH3 CH2
CH3 CH2
CH1 CH0
CH1 CH0
R
Data Memory
Connect. Memory
Control Register
Frame Align Register
FOR0
STA4
CH4
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
FOR1
x
FOR2
x
FOR3
x
FOR4
x
FOR5
x
FOR6
x
FOR7
7
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 5 CONTROL REGISTER (CR) BITS
ResetValue:
0000H.
12
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
MBP
BPD3 BPD2 BPD1 BPD0
BPE
OSB
SFE
DR1
DR0
Bit
Name
Unused
MBP
Description
Mustbezerofornormaloperation.
When1,theconnectionmemoryblockprogrammingfeatureisreadyfortheprogrammingofConnectionMemoryhighbits,
15-10
9
(Memory Block Program) bit11tobit15.When0,thisfeatureisdisabled.
8-5
4
BPD3-0
Thesebitscarrythevaluetobeloadedintotheconnectionmemoryblockwheneverthememoryblockprogrammingfeature
(BlockProgrammingData) is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD3-0 are
loadedintobit15and12oftheconnectionmemory.Bit11tobit0oftheconnectionmemoryaresetto0.
BPE
Azerotoonetransitionofthis bitenables thememoryblockprogrammingfunction.TheBPEandBPD4-0bits intheCR
register have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to
completetheblockprogramming.Aftertheprogrammingfunctionhasfinished,theBPEbitreturnstozerotoindicatethe
operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort to ensure proper operation. When
BPE=1,theotherbitintheCRregistermustnotbechangedfortwoframes toensureproperoperation.
(BeginBlock
ProgrammingEnable)
3
2
OSB
(OutputStandBy)
When ODE = 0 and OSB = 0, the output drivers of TX0 to TX31 are in high impedance mode. When ODE = 0 and OSB = 1,
theoutputdriverofTX0toTX31functionnormally. WhenODE=1,TX0 toTX31outputdriversfunctionnormally.
SFE
Azerotoonetransitioninthisbitstartstheframeevaluationprocedure. WhentheCFEbitintheFARregisterchangesfrom
zerotoone,theevaluationprocedurestops. Tostartanotherfameevaluationcycle,setthisbittozeroforatleastoneframe.
(StartFrameEvaluation)
1-0
DR1-0
(DataRateSelect)
DR1
0
0
1
1
DR0
0
1
0
1
DataRate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Reserved
Master Clock
4.096 MHz
8.192 MHz
16.384 MHz
Reserved
TABLE 6 CONNECTION MEMORY BITS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LPBK V/C
PC
OE
SAB4 SAB3 SAB2 SAB1 SAB0 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
Bit
Name
Description
15
14
13
LPBK
(PerChannelLoopback)
When1,theRXnchannelmdatacomesfromtheTXnchannelm.Forproperperchannelloopbackoperations,setthedelay
offsetregisterbitsOFn[2:0]tozeroforthestreamswhichareintheloopbackmode.
V/C(Variable/Constant
ThroughputDelay)
This bitis usedtoselectbetweenthevariable(LOW)andconstantdelay(HIGH)modeonaper-channelbasis.
PC
When1,thecontentsoftheconnectionmemoryareoutputonthecorrespondingoutputchannelandstream.Onlythelower
byte(bit7–bit0)willbeoutputtotheTXoutputpins.When0,thecontentsoftheconnectionmemoryarethedatamemory
addressoftheswitchedinputchannelandstream.
(ProcessorChannel)
12
OE
ThisbitenablestheTXoutputdriversonaper-channelbasis.When1,theoutputdriverfunctionsnormally.When0,theoutput
driverisinahigh-impedancestate.
(OutputEnable)
11-7 SAB4-0 (Source Stream
AddressBits)
Thebinaryvalueisthenumberofthedatastreamforthesourceoftheconnection.
6-0
CAB6-0 (Source Channel Thebinaryvalueisthenumberofthechannelforthesourceoftheconnection.
AddressBits)
8
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 7 ꢀRAME ALIGNMENT REGISTER (ꢀAR) BITS
ResetValue:
0000H.
12
15
14
13
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
CFE
FD11 FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
Bit
Name
Description
Mustbezerofornormaloperation
15-13 Unused
12
11
CFE (Complete
FrameEvaluation)
WhenCFE=1,theframeevaluationis completedandbits FD10toFD0bits contains avalidframealignmentoffset.This bitis resetto
zero, when SFE bit in the CR register is changed from 1 to 0.
FD11
The fallingedge ofFE(orrisingedge forGCImode)is sampledduringthe CLK-highphase (FD11=1)orduringthe CLK-lowphase
(Frame Delay Bit 11) (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
10-0 FD10-0 Thebinaryvalueexpressedinthesebitsreferstothemeasuredinputoffsetvalue.ThesebitsareresttozerowhentheSFEbitofthe
(Frame DelayBits) CR register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
ST-BUS Frame
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16
Offset Value
FE Input
(FD[10:0] = 06
H)
(FD11 = 0, sample at CLK LOW phase)
GCI Frame
CLK
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
Offset Value
FE Input
(FD[10:0] = 09
H)
(FD11 = 1, sample at CLK HIGH phase)
5715 drw 04
Figure 1. Example for Frame Alignment Measurement
9
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 8 ꢀRAME INPUT OꢀꢀSET REGISTER (ꢀOR) BITS
Reset Value:
0000H forallFORregisters.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF32
OF31
OF30
DLE3
OF22
OF21
OF20
DLE2
OF12
OF11
OF10
DLE1
OF02
OF01
OF00
DLE0
FOR0Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF72
OF71
OF70
DLE7
OF62
OF61
OF60
DLE6
OF52
OF51
OF50
DLE5
OF42
OF41
OF40
DLE4
FOR1Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF112
OF111
OF110
DLE11
OF102
OF101
OF100
DLE10
OF92
OF91
OF90
DLE9
OF82
OF81
OF80
DLE8
FOR2Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF312
OF311
OF310
DLE31
OF142
OF141
OF140
DLE14
OF132
OF131
OF130
DLE13
OF122
OF121
OF120
DLE12
FOR3Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF192
OF191
OF190
DLE19
OF182
OF181
OF180
DLE18
OF172
OF171
OF170
DLE17
OD162
OD161
OF160
DLE16
FOR4Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF232
OF231
OF230
DLE23
OF222
OF221
OF220
DLE22
OF212
OF211
OF210
DLE21
OF202
OF201
OF200
DLE20
FOR5Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF272
OF271
OF270
DLE27
OF262
OF261
OF260
DLE26
OF252
OF251
OF250
DLE25
OF242
OF241
OF240
DLE24
FOR6Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OF312
OF311
OF310
DLE31
OF302
OF301
OF300
DLE30
OF292
OF291
OF290
DLE29
OF282
OF281
OF280
DLE28
FOR7Register
Name(1)
OFn2, OFn1, OFn0
Description
Thesethreebitsdefinehowlongtheserialinterfacereceivertakestorecognizeandstorebit0fromtheRXinputpin:i.e.,tostartanewframe.
Theinputframeoffsetcanbeselectedto+4.5clockperiodsfromthepointwheretheexternalframepulseinputsignalisappliedtotheF0i
inputofthe device. See Figure 1.
(Offset Bits 2, 1 & 0)
DLEn
ST-BUS® mode:
(DataLatchEdge)
DLEn = 0, if clock rising edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock falling edge is at the ¾ of the bit cell.
GCI mode:
DLEn = 0, if clock falling edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.
NOTE:
1. n denotes an input stream number from 0 to 31.
10
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 9 OꢀꢀSET BITS (Oꢀn2, Oꢀn1, Oꢀn0, DLEn) & ꢀRAME DELAY BITS
(ꢀD11,ꢀD2-0)
MeasurementResultfrom
Frame Delay Bits
Corresponding
OffsetBits
InputStream
Offset
FD11
FD2
0
FD1
0
FD0
0
OFn2
OFn1
OFn0
DLEn
Noclockperiodshift(Default)
+0.5clockperiodshift
+1.0clockperiodshift
+1.5clockperiodshift
+2.0clockperiodshift
+2.5clockperiodshift
+3.0clockperiodshift
+3.5clockperiodshift
+4.0clockperiodshift
+4.5clockperiodshift
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
ST-BUS F0i
CLK
RX Stream
Bit 7
offset = 0, DLE = 0
offset = 1, DLE = 0
RX Stream
Bit 7
offset = 0, DLE = 1
offset = 1, DLE = 1
Bit 7
RX Stream
RX Stream
Bit 7
denotes the 3/4 point of the bit cell
GCI F0i
CLK
RX Stream
RX Stream
RX Stream
RX Stream
Bit 0
offset = 0, DLE = 0
offset = 1, DLE = 0
Bit 0
offset = 0, DLE = 1
offset = 1, DLE = 1
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
5715 drw 05
Figure 2. Examples for Input Offset Delay Timing
11
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
INSTRUCTION REGISTER
JTAGSUPPORT
In accordance with the IEEE-1149.1 standard, the IDT72V70840 uses
public instructions. The IDT72V70840 JTAG Interface contains a two-bit
instructionregister.Instructionsareseriallyloadedintotheinstructionregister
fromtheTDIwhentheTAPControllerisinitsshifted-IRstate.Subsequently,
theinstructionsaredecodedtoachievetwobasicfunctions:toselectthetestdata
registerthatmayoperatewhiletheinstructioniscurrent,andtodefinetheserial
testdataregisterpath,whichisusedtoshiftdatabetweenTDIandTDOduring
dataregisterscanning.SeeTablebelowforInstructiondecoding.
TheIDT72V70840JTAGinterfaceconformstotheBoundary-Scanstan-
dardIEEE-1149.1.Thisstandardspecifiesadesign-for-testabilitytechnique
called Boundary-Scan test (BST). The operation of the boundary-scan
circuitryis controlledbyanexternaltestaccess port(TAP)Controller.
TEST ACCESS PORT (TAP)
The TestAccess Port(TAP)provides access tothe testfunctions ofthe
IDT72V70840.Itconsistsofthreeinputpinsandoneoutputpin.
•Test Clock Input (TCK)
TCKprovidestheclockforthetestlogic.TheTCKdoesnotinterferewith
anyon-chipclockandthusremainindependent.TheTCKpermitsshiftingof
testdataintooroutoftheBoundary-Scanregistercellsconcurrentlywiththe
operationofthedeviceandwithoutinterferingwiththeon-chiplogic.
•TestMode SelectInput(TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controllertocontrolthetestoperations.TheTMSsignalsaresampledatthe
risingedgeoftheTCKpulse.ThispinisinternallypulledtoVCCwhenitisnot
driven from an external source.
Value Instruction
Function
11
10
01
00
Bypass
SelectBypassRegister
Sample/Preload
Sample/Preload
EXTEST
SelectBoundaryScanRegister
SelectBoundaryScanRegister
SelectBoundaryScanRegister
JTAG Instruction Register Decoding
•Test Data Input (TDI)
TESTDATAREGISTER
Serialinputdataappliedtothisportisfedeitherintotheinstructionregister
orintoatestdataregister,dependingonthesequencepreviouslyappliedto
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.
•TestDataOutput(TDO)
AsspecifiedinIEEE-1149.1,theIDT72V70840JTAGInterfacecontains
twotestdataregisters:
•The Boundary-Scan register
TheBoundary-ScanregisterconsistsofaseriesofBoundary-Scancells
arrangedtoformascanpatharoundtheboundaryoftheIDT72V70840core
logic.
Depending on the sequence previously applied to the TMS input, the
contentsofeithertheinstructionregisterordataregisterareseriallyshiftedout
towardstheTDO.ThedataoutoftheTDOisclockedonthefallingedgeofthe
TCKpulses.Whennodataisshiftedthroughtheboundaryscancells,theTDO
driverissettoahighimpedancestate.
•The Bypass Register
TheBypassregisterisasinglestageshiftregisterthatprovidesaone-bit
pathfromTDItoitsTDO.TheIDT72V70840boundaryscanregisterbitsare
showninTable10.Bit0isthefirstbitclockedout.Allthree-stateenablebitsare
activehigh.
•Test Reset (TRST)
Resetthe JTAGscanstructure. This pinis internallypulledtoVCC.
12
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
TABLE 10 BOUNDARY SCAN REGISTER BITS
Boundary Scan Bit 0 to bit 167
Boundary Scan Bit 0 to bit 167
Device Pin
Three-State
Control
Output
Scan Cell
Input
Scan Cell
Device Pin
Three-State
Control
Output
Scan Cell
Input
Scan Cell
RX27
RX26
RX25
RX24
TX23
TX22
TX21
TX20
TX19
TX18
TX17
TX16
RX23
RX22
RX21
RX20
RX19
RX18
RX17
RX16
TX15
TX14
TX13
TX12
TX11
TX10
TX9
92
93
94
95
ODE
RESET
CLK
F0i
FE/HCLK
WFPS
DS
CS
R/W
A0
A1
A2
A3
A4
0
1
2
3
4
5
6
7
8
96
98
97
99
100
102
104
106
108
110
101
103
105
107
109
111
9
10
11
12
13
14
15
16
17
18
19
20
21
22
112
113
114
115
116
117
118
119
A5
A6
A7
A8
A9
A10
A11
A12
A13
DTA
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
120
122
124
126
128
130
132
134
121
123
125
127
129
131
133
135
23
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
70
73
75
77
79
81
83
85
87
24
27
30
33
36
39
42
45
48
51
54
57
60
63
66
69
72
74
76
78
80
82
84
86
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
TX8
RX15
RX14
RX13
RX12
RX11
RX10
RX9
RX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
RX7
RX6
RX5
136
137
138
139
140
141
142
143
144
146
148
150
152
154
156
158
145
147
149
151
153
155
157
159
D0
TX31
TX30
TX29
TX28
TX27
TX26
TX25
TX24
RX31
RX30
RX29
RX28
160
161
162
163
164
165
166
167
RX4
RX3
RX2
RX1
88
89
90
91
RX0
13
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
side, however Device #1 is used to switch data out on to TX0-31 where as
Device#2isusedtoswitchoutonTX32-63.LikewiseDevice#3andDevice#4
are used in the same way as Device #1 and Device #2 but switch RX32-63,
toTX0-31andTX32-63.Withthisconfigurationallpossiblecombinationsofinput
andoutputstreamsarepossible.Inshort,Device#1isusedtoswitchRX0-31
toTX0-31,Device#2toswitchRX0-31toTX32-63,Device#3toswitchRX32-
63 to TX0-31, and Device #4 to switch RX32-63 to TX32-63.
APPLICATIONS
CREATING LARGE SWITCH MATRICES
TocreateaswitchmatrixwithtwicethecapacityofagivenTSISdevice,
four devices must be used. In the example below, four IDT72V70840,
4096 x 4096 channel capacity devices are used to create an 8192 x 8192
channelswitchmatrix.
Ascanbeseen,Device#1andDevice#2willreceivethesameincoming
RX0-31dataandthushavethesamecontentsinDataMemory.Ontheoutput
RX0-31
Device 1
TX0-31
IDT72V70840
Device 2
IDT72V70840
TX32-63
RX32-63
Device 3
IDT72V70840
Device 4
IDT72V70840
5715 drw06
Figure 3. Creating Larger Switch Matrices
14
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATING
CONDITIONS(1)
Symbol Parameter
Min.
Max.
Unit
Symbol
Parameter
Min.
3.0
Typ.
Max.
3.6
Unit
V
VCC
Vi
SupplyVoltage
3.0
GND -0.3
-50
3.6
5.3
50
V
V
VCC
Positive Supply
Input HIGH Voltage
InputLOWVoltage
3.3
VoltageonDigitalInputs
CurrentatDigitalOutputs
StorageTemperature
VIH
2.0
5.3
V
IO
mA
° C
W
VIL
0.8
V
TS
-55
+125
2
TOP
OperatingTemperature
Commercial
-40
25
+85
°C
PD
PackagePowerDissapation
NOTE:
NOTE:
1.Voltages are with respect to Ground unless otherwise stated.
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
DCELECTRICALCHARACTERISTICS
Symbol
Parameter
Min.
Typ.
Max.
Units
(2)
ICC
SupplyCurrent
@ 2.048 Mb/s
@ 4.096 Mb/s
@ 8.192 Mb/s
-
-
-
15
25
47
20
35
70
mA
mA
mA
(3,4)
IIL
InputLeakage(inputpins)
High-impedanceLeakage
OutputHIGHVoltage
OutputLOWVoltage
-
-
-
-
-
-
50
50
-
µA
µA
V
(3,4)
IOZ
(5)
VOH
2.4
-
(6)
VOL
0.4
V
NOTES:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Outputs unloaded.
3. 0 ≤ V ≤ VCC.
4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V).
5. IOH = 10 mA.
6. IOL = 10 mA.
ACELECTRICALCHARACTERISTICS-TIMINGPARAMETER
MEASUREMENTVOLTAGELEVELS
Symbol Rating
Level Unit
VTT
VHM
VLM
TTLThreshold
1.5
2.0
0.8
V
V
V
TTLRise/FallThresholdVoltageHIGH
TTLRise/FallThresholdVoltageLOW
Test Point
VCC
R
L
S1isopencircuitexceptwhentestingoutput
levelsorhighimpedancestates.
Output
Pin
S
2
S
1
C
L
GND
GND
S2isswitchedtoVCCorGNDwhentesting
outputlevelsorhighimpedancestates.
5715 drw07
Figure 4. Output Load
15
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS - ꢀRAME PULSE AND CLK
Typ.
Symbol
Parameter
Min.
Max.
Units
Frame Pulse Width (ST-BUS®, GCI)
Bit rate = 2.048 Mb/s
(1)
tFPW
26
26
26
295
145
80
ns
ns
ns
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
tFPS(1)
Frame Pulse Setup time before CLK falling (ST-BUS® or GCI)
Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI)
5
ns
ns
(1)
tFPH
10
tCP(1)
CLK Period
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
190
110
58
300
150
70
ns
ns
ns
(1)
tCH
CLK Pulse Width HIGH
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
85
50
20
150
75
40
ns
ns
ns
(1)
tCL
CLK Pulse Width LOW
Bit rate = 2.048 Mb/s
Bit rate = 4.096 Mb/s
Bit rate = 8.192 Mb/s
85
50
20
150
75
40
ns
ns
ns
tr,tf
ClockRise/FallTime
10
ns
(2)
tHFPW
WideFramePulseWidth
Bit rate = 8.192 Mb/s
195
5
295
150
150
ns
ns
ns
tHFPS(2)
FramePulseSetupTimebeforeHCLKfalling
Frame Pulse Hold Time from HCLK falling
(2)
tHFPH
10
tHCP(2)
HCLK (4.096 MHz) Period
Bit rate = 8.192 Mb/s
190
85
300
150
ns
ns
(2)
tHCH
HCLK (4.096 MHz) Pulse Width HIGH
Bit rate = 8.192 Mb/s
(2)
tHCL
HCLK (4.096 MHz) Pulse Width LOW
Bit rate = 8.192 Mb/s
85
150
10
ns
ns
ns
tHr,tHf
HCLK Rise/Fall Time
(3)
tDIF
Delaybetweenfallingedge ofHCLKandfallingedge ofCLK
-10
10
NOTES:
1. WFPS Pin = 0.
2. WFPS Pin = 1
3. WFPS Pin = 0 or 1.
16
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS(1) SERIAL STREAM (ST-BUS® and GCI)
Symbol
tSIS
Parameter
Min.
5
Typ.
Max.
Units
ns
RXSetupTime
RXHoldTime
tSIH
10
ns
tSOD
TX Delay – Active to Active
@ 2.048 Mb/s
30
30
30
ns
ns
ns
@ 4.096 Mb/s
@ 8.192 Mb/s
tDZ
TX Delay – Active to High-Z
@ 2.048 Mb/s
30
30
30
ns
ns
ns
@ 4.096 Mb/s
@ 8.192 Mb/s
tZD
TX Delay – High-Z to Active
@ 2.048 Mb/s
30
30
30
ns
ns
ns
@ 4.096 Mb/s
@ 8.192 Mb/s
tODE
Output Driver Enable (ODE) Delay
@ 2.048 Mb/s
30
30
30
ns
ns
ns
@ 4.096 Mb/s
@ 8.192 Mb/s
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL (1K), with timing corrected to cancel time taken to discharge CL (150 pF).
tFPW
F0i
t
f
tFPS
tCL
tr
tFPH
tCH
tCP
CLK
tSOD
Bit 0, Last Ch(1)
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
TX
tSIH
tSIS
RX
Bit 0, Last Ch(1)
Bit 7, Channel 0
Bit 6, Channel 0
Bit 5, Channel 0
5715 drw08
NOTE:
1. @ 2.048 Mb/s mode, last channel = ch 31,
@ 4.096 Mb/s mode, last channel = ch 63,
@ 8.192 Mb/s mode, last channel = ch 127.
Figure 5. ST-BUS® Timing
17
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
tFPW
F0i
t
f
tCL
tr
tCH
tFPS
tFPH
tCP
CLK
tSOD
Bit 7, Last Ch(1)
Bit 7, Last Ch(1)
Bit 2, Channel 0
Bit 0, Channel 0
Bit 1, Channel 0
TX
tSIS
tSIH
RX
Bit 0, Channel 0
Bit 1, Channel 0
Bit 2, Channel 0
5715 drw09
NOTE:
1. @ 2.048 Mb/s mode, last channel = ch 31,
@ 4.096 Mb/s mode, last channel = ch 63,
@ 8.192 Mb/s mode, last channel = ch 127.
Figure 6. GCI Timing
t
HFPW
tHFPS
tHFPH
F0i
tHCP
t
HCL
DIF
tHCH
HCLK
4.096 MHz
t
Hr
tHf
t
r
tf
t
t
CP
tCH
tCL
CLK
16.384 MHz
t
SOD
Bit 1, Ch 127
Bit 0, Ch 127
Bit 7, Ch 0
Bit 6, Ch 0
Bit 5, Ch 0
TX
Bit 4, Ch 0
tSIH
tSIS
Bit 5, Ch 0
Bit 7, Ch 0
Bit 6, Ch 0
Bit 1, Ch 127
Bit 0, Ch 127
Bit 4, Ch 0
RX
5715 drw10
Figure 7. WFP Bus Timing (@ 8.192 Mb/s, when pin WFPS is HIGH)
CLK
(ST-BUS mode)
CLK
(GCI mode)
tDZ
ODE
TX
t
ODE
TX
TX
HiZ
VALID DATA
t
ODE
tZD
HIZ
HIZ
VALID DATA
VALID DATA
HiZ
5715 drw12
5715 drw 10
Figure 8. Serial Output and External Control
Figure 9. Output Driver Enable (ODE)
18
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICS-MICROPROCESSORINTERꢀACETIMING
Symbol
tCSS
Parameter
Min.
0
Typ.
Max.
Units
ns
CS Setup from DS falling
R/WSetupfromDSfalling
AddressSetupfromDSfalling
CS Hold after DS rising
tRWS
3
ns
tADS
2
ns
tCSH
0
ns
tRWH
tADH
R/W Hold after DS Rising
Address HoldafterDSRising
Data SetupfromDTA LOWonRead
DataHoldonRead
3
ns
2
ns
(1)
tDDR
2
ns
(1,2,3)
tDHR
10
10
-
15
25
0
ns
tDSW
tSWD
tDHW
DataSetuponWrite(FastWrite)
ValidData DelayonWrite (SlowWrite)
DataHoldonWrite
ns
ns
5
ns
(1)
tAKD
AcknowledgmentDelay:
Reading/WritingRegisters
30
ns
ns
ns
ns
Reading/WritingMemory
@ 2.048 Mb/s
345
200
120
@ 4.096 Mb/s
@ 8.192 Mb/s
(1,2,3)
tAKH
AcknowledgmentHoldTime
Data Strobe Setup Time
20
ns
ns
(4)
tDSS
2
NOTES:
1. CL= 150pF
2. RL = 1K
3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
4. To achieve one clock cycle fast memory access, this setup time, tDSS should be met. Otherwise, worst case memory access operation is determined by tAKD.
19
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
COMMERCIALTEMPERATURERANGE
CLK GCI
CLK ST-BUS
tDSS
DS
tCSH
tCSS
CS
tRWH
tRWS
R/W
tADH
tADS
VALID ADDRESS
A0-A11
tDHR
D0-D15
READ
VALID READ DATA
tSWD
tDSW
tDHW
D0-D15
WRITE
VALID WRITE DATA
tDDR
tAKH
tAKD
DTA
5715 drw13
Figure 10. Motorola Non-Mulitplexed Bus Timing
20
ORDERINGINꢀORMATION
IDT
XXXXXX
XX
X
Device Type
Package
Process/
Temperature
Range
BLANK
Commercial (-40°C to +85°C)
Ball Grid Array (BGA, BC144-1)
Thin Quad Flatpacks (TQFP, DA144-1)
BC
DA
72V70840
4,096 x 4,096 3.3V Time Slot Interchange Digital Switch
5715 drw14
DATASHEETDOCUMENTHISTORY
5/05/2000
6/08/2000
8/30/2000
01/24/2001
10/22/2001
1/04/2002
pg. 1
pgs. 1, 2, 3 and 19.
pgs. 2, 4, 6, 9, 11, 13, 14, 16, 17 and 19.
pg. 14
pg. 1.
pgs. 1 and 15.
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21
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