IDT72V835L20PFI [IDT]
3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18; 3.3伏的CMOS双SyncFIFO DUAL 256 ×18 ，双512× 18 ，双1024 ×18 ，双2048 ×18
| 型号： | IDT72V835L20PFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 |
| 文件： | 总26页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
3.3 VOLT CMOS DUAL SyncFIFO™
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1,024 x 18, DUAL 2,048 x 18
and DUAL 4,096 x 18
• Easily expandable in depth and width
FEATURES:
• Asynchronous or coincident Read and Write Clocks
• Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
• The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs
• The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs
• The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs
• The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs
• The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs
• Offers optimal combination of large capacity (8K), high speed,
design flexibility, and small footprint
• Half-Full flag capability
• Output enable puts output data bus in high-impedance state
• High-performance submicron CMOS technology
• Available in a 128-pin thin quad flatpack (TQFP)
• Industrial temperature range (–40°C to +85°C) is available
• Ideal for the following applications:
– Network switching
– Two level prioritization of parallel data
– Bidirectional data transfer
DESCRIPTION:
The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide
synchronous (clocked)First-in, First-out(FIFO)memories designedtorun
off a 3.3V supply for exceptionally low power consumption. One dual
IDT72V805/72V815/72V825/72V835/72V845deviceisfunctionallyequiva-
lenttotwoIDT72V205/72V215/72V225/72V235/72V245FIFOs ina single
package with all associated control, data, and flag lines assigned to
independentpins. These devices are veryhigh-speed, low-powerFirst-In,
First-Out (FIFO) memories with clocked read and write controls. These
– Bus-matching between 18-bit and 36-bit data paths
– Width expansion to 36-bit per package
– Depth expansion to 8,192 words per package
• 10 ns read/write cycle time
• 5V input tolerant
• IDT Standard or First Word Fall Through timing
• Single or double register-buffered Empty and Full Flags
FUNCTIONAL BLOCK DIAGRAM
HFA/(WXOA)
FFA/IRA
PAEA
EFA/
ORA
WCLKA
WENA
WCLKB
WENB
DA0-DA17
LDA
DB0-DB17
LDB
PAFA
INPUT
REGISTER
OFFSET
REGISTER
INPUT
REGISTER
OFFSET
REGISTER
FFB/IRB
FLAG
PAFB
WRITE
FLAG
LOGIC
WRITE
EFB/ORB
PAEB
HFB/(WXOB)
RAM
CONTROL
LOGIC
LOGIC
CONTROL
LOGIC
RAM
ARRAY
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
READ
POINTER
WRITE
POINTER
READ
POINTER
WRITE
POINTER
FLA
WXIA
(HFA)/WXOA
RXIA
READ
CONTROL
LOGIC
READ
CONTROL
LOGIC
EXPANSION
LOGIC
EXPANSION
LOGIC
OUTPUT
REGISTER
OUTPUT
REGISTER
RXOA
RESET
LOGIC
RSA
RESET
LOGIC
RSB
RXOB
RXIB
(HFB)/WXOB
WXIB
FLB
RCLKB
RCLKA
OEB
QA0-QA17
RENB
RENA
OEA
QB0-QB17
4295 drw 01
The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APRIL 2001
1
2001 Integrated Device Technology, Inc.
DSC-4295/1
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
by asserting the Load pin (LD). A Half-Full flag (HF) is available for each
FIFO that is implemented as a single device.
DESCRIPTION (CONTINUED)
FIFOs are applicable for a wide variety of data buffering needs, such as
optical disk controllers, Local Area Networks (LANs), and interprocessor
communication.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and
enablingarisingRCLKedge,willshiftthewordfrominternalmemorytothe
data output lines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOis clockeddirectly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word.
These devices are depth expandable using a Daisy-Chain technique or
First Word Fall Through (FWFT) mode. The XI and XO pins are used to
expand the FIFOs. In depth expansion configuration, FL is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using
IDT’s high-speed submicron CMOS technology.
Each of the two FIFOs contained in these devices has an 18-bit input
and output port. Each input port is controlled by a free-running clock
(WCLK),andaninputenablepin(WEN).Datais readintothesynchronous
FIFO on every clock when WEN is asserted. The output port of each FIFO
bank is controlled by another clock pin (RCLK) and another enable pin
(REN). The Read Clock can be tied to the Write Clock for single clock
operation or the two clocks can run asynchronous of one another for dual-
clock operation. An Output Enable pin (OE) is provided on the read port
of each FIFO for three-state control of the output.
Thesynchronous FIFOs havetwofixedflags,EmptyFlag/OutputReady
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmableflagsiscontrolledbyasimplestatemachine,andisinitiated
PIN CONFIGURATIONS
INDEX
V
PAFA
RXIA
CC
LDA
OEA
RSA
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
FFA
VCC
WXOA/HFA
RXOA
QA0
GND
EFA
QA17
QA16
GND
QA15
QA1
GND
QA2
QA3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VCC
VCC
QA14
QA13
GND
QA12
QA11
QA4
GND
QA5
QA6
QA7
QA8
GND
DB7
DB6
DB5
VCC
QA10
QA9
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
GND
RCLKB
RENB
LDB
DB4
DB3
DB2
DB1
DB0
75
74
73
72
71
70
69
68
67
66
65
PAEB
FLB
WCLKB
WENB
WXIB
V
PAFB
RXIB
CC
OEB
RSB
VCC
FFB
GND
EFB
WXOB/HFB
RXOB
4295 drw 02
TQFP (PK128-1, ORDER CODE: PF)
TOP VIEW
2
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
Name
Data Inputs
I/O
Description
DA0–DA17
I
Data inputs for an 18-bit bus.
DB0-DB17
RSA
Reset
RSB
I
I
I
I
I
I
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and
PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLKA
WCLKB
Write Clock
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
WENA
WENB
Write Enable
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.
When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
RCLKA
Read Clock
RCLKB
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not
empty.
RENA
RENB
Read Enable
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN
is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF is low.
OEA
Output Enable
OEB
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high-impedance state.
LDA
LDB
Load
When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.
FLA
FLB
First Load
I
I
I
In the single device or width expansion configuration, FL together with WXI and RXI etermine if the mode is IDT
Standard mode or First Word Fall Through (FWFT) mode, as well as whether the PAE/PAF flags are synchronous
or asynchronous. (See Table I.) In the Daisy Chain Depth Expansion configuration, FL is grounded on the first
device (first load device) and set to HIGH for all other devices in the Daisy Chain.
WXIA
WXIB
Write Expansion
Read Expansion
In the single device or width expansion configuration, WXI together with FL and RXI Input determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, WXI is connected to WXO (Write Expansion
Out) of the previous device.
RXIA
RXIB
In the single device or width expansion configuration, RXI together with FL and WXI, Input determine if the mode
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, RXI is connected to RXO (Read
Expansion Out) of the previous device.
FFA/IRA
FFB/IRB
Full Flag/
Input Ready
O
O
O
O
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full.
In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to
the FIFO memory.
EFA/ORA
EFB/ORB
Empty Flag/
Output Ready
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is
empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at
the outputs.
PAEA
PAEB
Programmable
Almost-Empty flag
When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default offset
atresetis31fromemptyforIDT72V805LB,63fromemptyforIDT72V815LB,and127fromemptyforIDT7V2825LB/
72V835LB/72V845LB.
PAFA
PAFB
Programmable
Almost-Full Flag
When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is 31 from full for IDT72V805LB, 63 from full for IDT72V815LB, and 127 from full for IDT72V825LB/
72V835LB/72V845LB.
WXOA/HFA
WXOB/HFB
Write Expansion
In the single device or width expansion configuration, the device is more than half full Out/Half-Full Flag
when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to WXI of the next device
when the last location in the FIFO is written.
RXOA
RXOB
Read Expansion
Out
O
O
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last location
in the FIFO is read.
QA0–QA17
QB0-QB17
Data Outputs
Data outputs for an 18-bit bus.
VCC
Power
+3.3V power supply pins.
Ground pins.
GND
Ground
3
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RECOMMENDED OPERATING DC
CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Commercial
Unit
Symbol
Parameter
Min.
Typ.
Max. Unit
VTERM
Terminal Voltage
–0.5 to +5
V
VCC
Supply Voltage
3.0
3.3
3.6
V
with respect to GND
Commercial/Industrial
Supply Voltage
TSTG
IOUT
Storage
Temperature
–55 to +125
–50 to +50
°C
GND
VIH
0
0
0
V
V
Input High Voltage
2.0
—
5.0
DC Output Current
mA
Commercial/Industrial
(1)
VIL
Input Low Voltage
Commercial/Industrial
—
0
—
—
0.8
70
85
V
°C
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TA
TA
Operating Temperature
Commercial
Operating Temperature
Industrial
-40
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
Commercial & Industrial(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
–1
Typ.
—
Max.
Unit
µA
µA
V
(2)
ILI
Input Leakage Current (any input)
Output Leakage Current
1
(3)
ILO
–10
2.4
—
—
10
—
0.4
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
—
—
V
(4,5,6)
ICC1
Active Power Supply Current
Standby Current
—
—
—
—
60
10
mA
mA
(4,7)
ICC2
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. Typical ICC1 = 2[2.04 + 0.88*fS + 0.02*CL*fS] (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC –0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
4
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Commercial
IDT72V805L10
IDT72V815L10
IDT72V825L10
IDT72V835L10
IDT72V845L10
Com’l & Ind’l(2)
IDT72V805L15
IDT72V815L15
IDT72V825L15
IDT72V835L15
IDT72V845L15
Commercial
IDT72V805L20
IDT72V815L20
IDT72V825L20
IDT72V835L20
IDT72V845L20
Symbol
fS
Parameter
Clock Cycle Frequency—
Data Access Time
Min.
100
Max.
Min.
66.7
2
Max.
—
10
—
—
—
—
—
—
—
—
—
—
15
—
8
Min.
50
2
Max.
MHz
12
Unit
—
tA
2
10
4.5
4.5
3
6.5
—
—
—
—
—
—
—
—
—
—
15
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
15
6
20
8
—
—
—
—
—
—
—
—
—
—
20
Clock HIGH Time
Clock LOW Time
6
8
Data Setup Time
4
5
tDH
Data Hold Time
0.5
3
1
1
tENS
tENH
tRS
Enable Setup Time
4
5
Enable Hold Time
0.5
10
8
1
1
Reset Pulse Width(1)
Reset Setup Time
15
10
10
—
0
20
12
12
—
0
tRSS
tRSR
tRSF
tOLZ
tOE
Reset Recovery Time
Reset to Flag and Output Time
8
—
0
(3)
Output Enable to Output in Low-Z
Output Enable to Output Valid
—
10
—
1
3
3
(3)
tOHZ
tWFF
tREF
tPAFA
Output Enable to Output in High-Z
Write Clock to Full Flag
6
3
8
3
10
—
—
—
6.5
6.5
17
—
—
—
10
10
20
—
—
—
12
Read Clock to Empty Flag
12
Clock to Asynchronous Programmable
Almost-Full Flag
22
tPAFS
tPAEA
tPAES
Write Clock to Synchronous
Programmable Almost-Full Flag
—
—
—
8
17
8
—
—
—
10
20
10
—
—
—
12
22
12
ns
ns
ns
Clock to Asynchronous Programmable
Almost-Empty Flag
Read Clock to Synchronous
Programmable Almost-Empty Flag
tHF
Clock to Half-Full Flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Setup Time
—
—
3
17
6.5
—
—
—
—
—
6.5
5
20
10
—
—
—
—
—
8
22
12
—
—
—
ns
ns
ns
ns
ns
tXO
tXI
tXIS
3
8
tSKEW1
Skew time between Read Clock &
5
6
8
Write Clock for FF/IR and EF/OR
Skew time between Read Clock &
(4)
tSKEW2
14
—
18
—
20
—
ns
Write Clock for PAE and PAF
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Industrial temperature range product for the 15ns speed grade is available as a standard device.
3. Values guaranteed by design, not currently tested.
4. tSKEW2 applies to synchronous PAE and synchronous PAF only.
3.3V
330Ω
D.U.T.
AC TEST CONDITIONS
30pF*
510Ω
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
4295 drw 03
1.5V
1.5V
Figure 1. Output Load
* Includes jig and scope capacitances.
See Figure 1
5
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
completely empty for IDT72V815, and 127 away from completely empty for
IDT72V825/72V835/72V845. Continuing read operations will cause the
FIFO to be empty. When the last word has been read from the FIFO, the EF
will go LOW inhibiting further read operations. REN is ignored when the
FIFO is empty.
FUNCTIONAL DESCRIPTION
TIMING MODES:
IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE
TheIDT72V805/72V815/72V825/72V835/72V845supporttwodifferent
timing modes of operation. The selection of which mode will operate is
determinedduringconfigurationatReset(RS).Duringa RS operation,the
First Load (FL), Read Expansion Input ( RXI), and Write Expansion Input
(WXI) pins are used to select the timing mode per the truth table shown in
Table 3. In IDT Standard Mode, the first word written to an empty FIFO will
not appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating Read Enable
(REN) and enabling a rising Read Clock (RCLK) edge, will shift the word
from internal memory to the data output lines. In FWFT mode, the first word
written to an empty FIFO is clocked directly to the data output lines after
three transitions of the RCLK signal. A REN does not have to be asserted
for accessing the first word.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the Empty Offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 130th
(72V805), 258th(72V815),514th(72V825),1,026th(72V835),and2,050th
(72V845) word respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the PAF to go LOW. Again, if no reads are
performed, the PAF will go LOW after (257-m) writes for the IDT72V805,
(513-m) writes for the IDT72V815, (1,025-m) writes for the IDT72V825,
(2,049–m)writesfortheIDT72V835and(4,097–m)writesfortheIDT72V845,
where m is the Full Offset value. The default setting for this value is stated
in the footnote of Table 2.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepend-
ing on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
intotheFIFOonsubsequenttransitionsoftheWriteClock(WCLK).Afterthe
first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where nis the EmptyOffsetvalue. The defaultsettingforthis value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 257 writes for the IDT72V805, 513 for
the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and
4,097 for the IDT72V845. Note that the additional word in FWFT mode is
due to the capacity of the memory plus output register.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 129th (72V805), 257th (72V815), 513th (72V825), 1,025th
(72V835), and 2,049th (72V845) word respectively was written into the
FIFO. Continuing to write data into the FIFO will cause the Programmable
Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the
PAF willgoLOWafter(256-m)writes forthe IDT72V805, (512-m)writes for
the IDT72V815, (1,024-m) writes for the IDT72V825, (2,048–m) writes for
the IDT72V835 and (4,096–m) writes for the IDT72V845. The offset “m” is
the Full Offset value. This parameter is also user programmable. See
section on Programmable Flag Offset Loading. If there is no Full Offset
specified, the PAF willbe LOWwhenthe device is 31awayfromcompletely
full for IDT72V805, 63 away from completely full for IDT72V815, and 127
away from completely full for the IDT72V825/72V835/72V845.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 256 writes for the IDT72V805, 512 for the
IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096
for the IDT72V845, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and the Half-Full flag (HF) to
go HIGH at the conditions described in Table 1. If further read operations
occur, without write operations, the Programmable Almost-Empty flag
(PAE)willgoLOWwhentherearenwordsintheFIFO,wherenistheEmpty
Offsetvalue.IfthereisnoEmptyOffsetspecified,thePAEwillbeLOWwhen
the device is 31 away from completely empty for IDT72V805, 63 away from
Ifthe FIFOis full, the firstreadoperationwillcause the IR flagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the Empty Offset value. If there is no Empty Offset
specified, the PAE willbe LOWwhenthe device is 32awayfromcompletely
empty for IDT72V805, 64 away from completely empty for IDT72V815, and
128awayfromcompletelyemptyforIDT72V825/72V835/72V845.Continu-
ingreadoperationswillcausetheFIFOtobeempty.Whenthelastwordhas
beenreadfromtheFIFO, ORwillgoHIGHinhibitingfurtherreadoperations.
REN is ignored when the FIFO is empty.
PROGRAMMABLE FLAG LOADING
Full and Empty flag Offset values can be user programmable. The
IDT72V805/72V815/72V825/72V835/72V845hasinternalregistersforthese
offsets. Default settings are stated in the footnotes of Table 1 and Table 2.
Offset values are loaded into the FIFO using the data input lines D0-D11.
To load the offset registers, the Load (LD) pin and WEN pin must be held
LOW. Data present on D0-D11 will be transferred in to the Empty Offset
registeronthe firstLOW-to-HIGHtransitionofWCLK. Bycontinuingtohold
the LD and WEN pin low, data present on D0-D11 will be transferred into
the Full Offset register on the next transition of the WCLK. The third
transition again writes to the Empty Offset register. Writing all offset
registers does nothave tooccuratone time. One ortwooffsetregisters can
be written and then by bringing the LD pin HIGH, the FIFO is returned to
6
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
normalread/writeoperation.WhentheLD pinandWENareagainsetLOW, grams, see Figure 13 for asynchronous PAE timing and Figure 14 for
the next offset register in sequence is written.
The contents of the offset registers can be read on the data output lines
asynchronous PAF timing.
If synchronous PAE/PAF configuration is selected , the PAE is asserted
Q0-Q11 when the LD pin is set LOW and REN is set LOW. Data can then andupdatedonthe risingedge ofRCLKonlyandnotWCLK. Similarly,PAF
be read on the next LOW-to-HIGH transition of RCLK. The first transition isassertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.For
of RCLK will present the Empty Offset value to the data output lines. The detail timing diagrams, see Figure 22 for synchronous PAE timing and
next transition of RCLK will present the Full Offset value. Offset register Figure 23 for synchronous PAF timing.
content can be read out in the IDT Standard mode only. It cannot be read
in the FWFT mode.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
The IDT72V805/72V815/72V825/72V835/72V845 can be configured
during the "Configuration at Reset" cycle described in Table 4 with single,
double or triple register-buffered flag output signals. The various combina-
SYNCHRONOUS VS ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V805/72V815/72V825/72V835/72V845 can be configured tions available are described in Table 4 and Table 5. In general, going from
during the "Configuration at Reset" cycle described in Table 3 with either single to double or triple buffered flag outputs removes the possibility of
asynchronous or synchronous timing for PAE and PAF flags.
metastable flag indications on boundary states (i.e, empty or full condi-
If asynchronous PAE/PAF configuration is selected (as per Table 3), the tions). The trade-off is the addition of clock cycle delays for the respective
PAEisassertedLOWontheLOW-to-HIGHtransitionofRCLK. PAEisreset flag to be asserted. Not all combinations of register-buffered flag outputs
to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is are supported. Register-buffered outputs apply to the Empty Flag and Full
asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset Flag only. Partial flags are not effected. Table 4 and Table 5 summarize
to HIGH on the LOW-to-HIGH transition of RCLK. For detail timing dia- the options available.
TABLE 1 STATUS FLAGS FOR IDT STANDARD MODE
Number of Words in FIFO
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
FF PAF HF PAE EF
0
0
0
0
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
(n + 1) to 128
129 to (256-(m+1))(2)
(256-m) to 255
256
(n + 1) to 256
257 to (512-(m+1))(2)
(512-m)to 511
512
(n + 1) to 512
(n + 1) to 1,024
1,025 to (2,048-(m+1))(2)
(2,048-m) to 2,047
2,048
(n + 1) to 2,048
2,049 to (4,096-(m+1))(2)
(4,096-m) to 4,095
4,096
H
H
H
H
(2)
513 to (1,024-(m+1))
(1,024-m) to 1,023
1,024
L
NOTES:
1. n = Empty Offset (Default Values : IDT72V805 n=31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)
2. m = Full Offset (Default Values : IDT72V805 m=31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)
TABLE 2 STATUS FLAGS FOR FWFT MODE
Number of Words in FIFO
IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
IR PAF HF PAE OR
0
0
0
0
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to (n + 1)(1)
(n + 2) to 129
130 to (257-(m+1))(2)
(257-m) to 256
257
1 to (n + 1)
(n + 2) to 257
258 to (513-(m+1))(2)
(513-m) to 512
513
1 to (n + 1)(1)
1 to (n + 1)(1)
1 to (n + 1)
(1)
(1)
(n + 2) to 513
(n + 2) to 1,025
1,026 to (2,049-(m+1))(2)
(2,049-m) to 2,048
2,049
(n + 2) to 2,049
2,050 to (4,097-(m+1))(2)
(4,097-m) to 4,096
4,097
H
H
H
H
(2)
514 to (1,025-(m+1))
(1,025-m) to 1,024
1,025
L
NOTES:
1. n = Empty Offset (Default Values : IDT72V805 n = 31, IDT72V815 n = 63, IDT72V825/72V835/72V845 n = 127)
2. m = Full Offset (Default Values : IDT72V805 m = 31, IDT72V815 m = 63, IDT72V825/72V835/72V845 m = 127)
7
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 3 TRUTH TABLE FOR CONFIGURATION AT RESET
FL
RXI
WXI
EF/OR
FF/IR
PAE, PAF
FIFO TIMING MODE
0
0
0
Single Register-Buffered
Empty Flag
Single Register-Buffered
Full Flag
Asynchronous
Standard
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Triple Register-Buffered
Output Ready Flag
Double Register-Buffered
Empty Flag
Single Register-Buffered
Empty Flag
Single Register-Buffered
Empty Flag
Double Register-Buffered
Input Ready Flag
Double Register-Buffered
Full Flag
Single Register-Buffered
Full Flag
Single Register-Buffered
Full Flag
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Asynchronous
FWFT
Standard
Standard
Standard
FWFT
0(1)
1
1
Triple Register-Buffered
Output Ready Flag
Double Register-Buffered
Empty Flag
Single Register-Buffered
Empty Flag
Double Register-Buffered
Input Ready Flag
Double Register-Buffered
Full Flag
Single Register-Buffered
Full Flag
1
Standard
Standard
1(2)
NOTES:
1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.
2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO
and WXO outputs of the preceding device.
TABLE4 REGISTER-BUFFEREDFLAGOUTPUTOPTIONSIDTSTANDARDMODE
Empty Flag (EF)
Buffered Output
Full Flag (FF)
Buffered Output
Partial Flags
Timing Mode
Programming at Reset
Flag Timing
Diagrams
FL
RXI
WXI
Single
Single
Double
Double
Single
Single
Double
Double
Asynch
Sync
0
1
0
1
0
0
Figure 9, 10
Figure 9, 10
Figure 24, 26
Figure 24, 26
0
0
Asynch
Synch
1
0
0
1
TABLE 5 REGISTER-BUFFERED FLAG OUTPUT OPTIONS FWFT MODE
Output Ready (OR)
Input Ready (IR)
Partial Flags
Programming at Reset
Flag Timing
Diagrams
FL
RXI
WXI
Triple
Triple
Double
Double
Asynch
Sync
0
1
0
1
Figure 27
0
1
Figure 20, 21
8
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EFA/EFB) will go
LOW, inhibiting further read operations. REN is ignored when the FIFO is
empty. Onceawriteisperformed, EFwillgoHIGHallowingareadtooccur.
The EF flag is updated on the rising edge of RCLK.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
Inthe FWFTmode, the firstwordwrittentoanemptyFIFOautomatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK
+ tSKEW after the first write. REN does not need to be asserted LOW. In
CONTROLS:
RESET (RSA/RSB)
Resetis accomplishedwheneverthe Reset(RSA/RSB)inputis takento
a LOW state. During reset, both internal read and write pointers are set to
thefirstlocation.Aresetis requiredafterpower-upbeforeawriteoperation
can take place. The Half-Full flag (HFA/HFB) and Programmable Almost-
Fullflag(PAFA/PAFB)willberesettoHIGHaftertRSF. TheProgrammable
Almost-Empty flag (PAEA/PAEB) will be reset to LOW after tRSF. The Full
Flag (FFA/FFB) will reset to HIGH. The Empty Flag (EFA/EFB) will reset
toLOWinIDTStandardmodebutwillresettoHIGHinFWFTmode. During
reset, the output register is initialized to all zeros and the offset registers
are initialized to their default values.
LD
WEN
WCLK
Selection
Writing to offset registers:
Empty Offset
0
0
Full Offset
0
1
1
0
No Operation
Write Into FIFO
WRITE CLOCK (WCLKA/WCLKB)
A write cycle is initiated on the LOW-to-HIGH transition of the Write
Clock (WCLKA/WCLKB). Data setup and hold times must be met with
respect to the LOW-to-HIGH transition of WCLK.
1
1
No Operation
NOTE:
The Write and Read Clocks can be asynchronous or coincident.
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
WRITE ENABLE (WENA/WENB)
Figure 2. Writing to Offset Registers
When the WENA/WENB input is LOW, data may be loaded into the
FIFORAMarrayonthe risingedge ofeveryWCLKcycle ifthe device is not
full. Data is storedinthe RAMarraysequentiallyandindependentlyofany
ongoing read operation.
When WEN is HIGH, no new data is written in the RAM array on each
WCLK cycle.
To prevent data overflow in the IDT Standard Mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read
cycle, FF will go HIGH allowing a write to occur. The FF flag is updated on
the rising edge of WCLK.
Topreventdataoverflow intheFWFTmode, InputReady(IRA,IRB)will
goHIGH,inhibitingfurtherwrite operations. Uponthe completionofa valid
read cycle, IR will go LOW allowing a write to occur. The IR flag is updated
on the rising edge of WCLK.
17
17
0
0
11
11
EMPTY OFFSET REGISTER
DEFAULT VALUE
001FH (IDT72V805) 003FH (IDT72V815):
007FH (IDT72V825/72V835/72V845)
FULL OFFSET REGISTER
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
DEFAULT VALUE
001FH (IDT72V805) 003FH (IDT72V815):
007FH (IDT72V825/72V835/72V845)
READ CLOCK (RCLKA/RCLKB)
4295 drw 04
Data can be read on the outputs on the LOW-to-HIGH transition of the
Read Clock (RCLKA/RCLKB), when Output Enable (OEA/OEB) is set
LOW.
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (RENA/RENB)
WhenReadEnable(RENA/RENB)isLOW,dataisloadedfromtheRAM
array into the output register on the rising edge of every RCLK cycle if the order to access all other words, a read must be executed using REN. The
device is not empty.
RCLK LOW to HIGH transition after the last word has been read from the
WhentheRENinputis HIGH,the outputregisterholds the previous data FIFO, OutputReady(ORA/ORB)willgoHIGHwitha true read(RCLKwith
and no new data is loaded into the output register. The data outputs Q0- REN = LOW), inhibiting further read operations. REN is ignored when the
Qn maintain the previous data value.
FIFO is empty.
9
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE (OEA/OEB)
D = 256 writes for the IDT72V805, 512 for the IDT72V815, 1,024 for the
IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845.
InFWFTmode, the InputReady(IRA/IRB)functionis selected. IRgoes
LOW when memory space is available for writing in data. When there is
no longer any free space left, IR goes HIGH, inhibiting further write
operations.
When Output Enable (OEA/OEB) is enabled (LOW), the parallel output
buffers receive data fromthe outputregister.When OE is disabled(HIGH),
the Q output data bus is in a high-impedance state.
LOAD (LDA/LDB)
IR will go HIGH after D writes to the FIFO. D = 257 writes for the
IDT72V205LB, 513 for the IDT72V215LB, 1,025 for the IDT72V225LB,
2,049 for the IDT72V235LB and 4,097 for the IDT72V245LB. Note that the
additional word in FWFT mode is due to the capacity of the memory plus
output register.
The IDT72V805/72V815/72V825/72V835/72V845 devices contain two
12-bitoffsetregisters withdata onthe inputs,orreadonthe outputs. When
the Load (LDA/LDB) pin is set LOW and WEN is set LOW, data on the
inputs D0-D11 is written into the Empty offset register on the first LOW-to-
HIGHtransitionofthe Write Clock(WCLK). Whenthe LD pinandWEN are
held LOW then data is written into the Full offset register on the second
LOW-to-HIGH transition of WCLK. The third transition of WCLK again
writes to the Empty offset register.
FF/IR is synchronous and updated on the rising edge of WCLK.
EMPTY FLAG/OUTPUT READY (EFA/ORA, EFB/ORB)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(EFA/EFB) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When EF is HIGH, the FIFO is not
empty.
However, writing all offset registers does not have to occur at one time.
One or two offset registers can be written and then by bringing the LD pin
HIGH, the FIFO is returned to normal read/write operation. When the LD
pin is set LOW, and WEN is LOW, the next offset register in sequence is
written.
Whenthe LD pinis LOWand WEN is HIGH, the WCLKinputis disabled;
then a signal at this input can neither increment the write offset register
pointer, nor execute a write.
In FWFT mode, the Output Ready (ORA/ORB) function is selected. OR
goes LOW at the same time that the first word written to an empty FIFO
appears validonthe outputs. OR stays LOWafterthe RCLKLOWtoHIGH
transitionthatshiftsthelastwordfromtheFIFOmemorytotheoutputs. OR
goes HIGH only with a true read (RCLK with REN = LOW). The previous
data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until OR goes LOW again.
The contents ofthe offsetregisters canbe readonthe outputlines when
the LD pin is set LOW and REN is set LOW; then, data can be read on the
LOW-to-HIGH transition of the Read Clock (RCLK). The act of reading the
control registers employs a dedicated read offset register pointer. (The
read and write pointers operate independently). Offset register content
can be read out in the IDT Standard mode only. It is inhibited in the FWFT
mode.
EF/OR is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAFA/PAFB)
The Programmable Almost-Full flag (PAFA/PAFB) will go LOW when
FIFO reaches the almost-full condition. In IDT Standard mode, if no reads
are performed after Reset (RS), the PAF will go LOW after (256-m) writes
forthe IDT72V805, (512-m)writes forthe IDT72V815, (1,024-m)writes for
the IDT72V825, (2,048–m) writes for the IDT72V835 and (4,096-m) writes
for the IDT72V845. The offset “m” is defined in the FULL offset register.
In FWFT mode, if no reads are performed, PAF will go LOW after (257-
m)writes forthe IDT72V805, (513-m)writes forthe IDT72V815, (1,025-m)
writes for the IDT72V825, (2,049-m) writes for the IDT72V835 and (4,097-
m) writes for the IDT72V845. The default values for m are noted in Table
1 and 2.
A read and a write should not be performed simultaneously to the offset
registers.
FIRST LOAD (FLA/FLB)
For the single device mode, see Table I for additional information. In
the Daisy Chain Depth Expansion configuration, FLA/FLB is grounded to
indicate it is the first device loaded and is set to HIGH for all other devices
in the Daisy Chain. (See Operating Configurations for further details.)
If asynchronous PAF configuration is selected, the PAF is asserted
LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is
reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK).
If synchronous PAF configuration is selected (see Table I), the PAF is
updated on the rising edge of WCLK.
WRITE EXPANSION INPUT (WXIA/WXIB)
This is a dual purpose pin. For single device mode, see Table I for
additional information. WXIA/WXIB is connected to Write Expansion Out
(WXOA/WXOB) of the previous device in the Daisy Chain Depth Expan-
sion mode.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAEA/PAEB)
The PAE flag will go LOW when the FIFO reads the almost-empty
condition. InIDTStandardmode,PAE willgoLOWwhentherearenwords
or less in the FIFO. In FWFT mode, the PAE will go LOW when there are
n+1words orless inthe FIFO. The offset“n”is definedas the Emptyoffset.
The default values for n are noted in Table 1 and 2.
READ EXPANSION INPUT (RXIA/RXIB)
This is a dual purpose pin. For single device mode, see Table I for
additional information. RXIA/RXIB is connected to Read Expansion Out
(RXOA/RXOB)ofthe previous device inthe DaisyChainDepthExpansion
mode.
If asynchronous PAE configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is
reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK).
If synchronous PAE configuration is selected (see Table I), the PAE is
updated on the rising edge of RCLK.
OUTPUTS:
FULL FLAG/INPUT READY (FFA/IRA, FFB/IRB)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FFA/
FFB) function is selected. When the FIFO is full,FF willgoLOW, inhibiting
further write operations. When FF is HIGH, the FIFO is not full. If no reads
are performed after a reset, FF will go LOW after D writes to the FIFO.
10
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WRITE EXPANSION OUT/HALF-FULL FLAG
(WXOA/HFA, WXOB/HFB)
the Daisy Chain by providing a pulse when the previous device writes to
the last location of memory.
This is adual-purposeoutput.IntheSingleDeviceandWidthExpansion
mode, when Write Expansion In (WXIA/WXIB) and/or Read Expansion In READ EXPANSION OUT (RXOA/RXOB)
(RXIA/RXIB) are grounded, this output acts as an indication of a half-full
memory.
In the Daisy Chain Depth Expansion configuration, Read Expansion In
(RXIA/RXIB) is connected to Read Expansion Out (RXOA/RXOB) of the
After half of the memory is filled, and at the LOW-to-HIGH transition of previous device. This outputacts as a signaltothe nextdevice inthe Daisy
the next write cycle, the Half-Full flag goes LOW and will remain set until Chain by providing a pulse when the previous device reads from the last
the difference between the write pointer and read pointer is less than or location of memory.
equaltoone halfofthe totalmemoryofthe device. The Half-Fullflag(HFA/
HFB) is then reset to HIGH by the LOW-to-HIGH transition of the Read DATA OUTPUTS (Q0-Q17, QB0-QB17)
Clock (RCLK). The HF is asynchronous.
Q0-Q17 are data outputs for 18-bit wide data.
In the Daisy Chain Depth Expansion mode, WXI is connected to WXO
of the previous device. This output acts as a signal to the next device in
11
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
RS
RSR
RSR
t
REN, WEN, LD
tRSS
t
FL, RXI, WXI(1)
CONFIGURATION SETTING
RCLK, WCLK (2)
FF/IR
RSF
t
RSF
RSF
RSF
RSF
t
FWFT Mode
EF/OR
IDT Standard Mode
t
t
t
PAF, WXO/
HF, RXO
PAE
OE = 1(3)
Q0 - Q17
4295 drw 05
OE = 0
NOTES:
1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
Figure 5. Reset Timing(2)
t
CLK
tCLKH
tCLKL
tDS
WCLK
tDH
D0
- D17
DATA IN VALID
tENH
t
ENS
NO OPERATION
WEN
FF
tWFF
tWFF
(1)
tSKEW1
RCLK
4295 drw 06
REN
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 6. Write Cycle Timing with Single Register-Buffered FF (IDT Standard Mode)
12
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
RCLK
REN
EF
t
ENS
t
ENH
NO OPERATION
tREF
tREF
t
A
Q0
- Q17
OE
VALID DATA
tOLZ
tOHZ
t
OE
(1)
t
SKEW1
WCLK
WEN
4295 drw 07
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode)
WCLK
tDS
D0 (first valid write)
D0
- D17
D1
D2
D3
D4
t
ENS
WEN
(1)
tFRL
tSKEW1
RCLK
tREF
EF
tENS
REN
tA
tA
Q0
- Q17
D0
D1
tOLZ
t OE
OE
4295 drw 08
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
2. The first word is available the cycle after EF goes HIGH, always.
3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode)
13
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NO WRITE
NO WRITE
(1)
WCLK
(1)
tSKEW1
tDS
tSKEW1
t DS
DATA
WRITE
D0
- D17
DATA WRITE
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
t ENS
tENH
tENH
REN
OE
LOW
tA
DATA IN OUTPUT REGISTER
tA
Q0
- Q17
DATA READ
NEXT DATA READ
4295 drw 09
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)
WCLK
tDS
tDS
DATA WRITE 1
DATA WRITE 2
D0
- D17
tENS
tENS
tENH
tENH
WEN
(1)
(1)
FRL
tFRL
t
tSKEW1
tSKEW1
RCLK
t
REF
t
REF
t
REF
EF
REN
OE
LOW
tA
Q0
- Q17
DATA IN OUTPUT REGISTER
DATA READ
4295 drw 10
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW1, or tCLK + tSKEW1. The
Latency Timing apply only at the Empty Boundary (EF = LOW).
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)
14
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
WCLK
LD
tENS
tENH
tENS
WEN
tDS
tDH
PAE OFFSET
D0—D15
4295 drw 11
PAE OFFSET
PAF OFFSET
D0—D11
Figure 11. Write Programmable Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
LD
tENS
REN
tA
PAE OFFSET
Q0—Q15
UNKNOWN
PAE OFFSET
PAF OFFSET
4295 drw 12
Figure 12. Read Programmable Registers (IDT Standard Mode)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
(2)
(2)
n words in FIFO
,
(2)
n words in FIFO
n + 1 words in FIFO
,
n+1wordsinFIFO
,
PAE
RCLK
REN
(3)
(3)
n + 1 words in FIFO
(3)
n+2wordsinFIFO
tPAEA
tENS
4295 drw 13
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
15
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
(1)
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words
in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
4295 drw 14
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(2),
D/2 words in FIFO(2)
D-1
2
,
D/2 words in FIFO(2)
D-1
2
,
D-1
[
+ 2]
words in FIFO(3)
2
[
+ 1
]
words in FIFO(3)
[
+ 1
words in FIFO(3)
]
tHF
RCLK
tENS
REN
4295 drw 15
NOTES:
1. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.
Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)
16
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
WCLK
Note 1
tXO
tXO
WXO
WEN
tENS
4295 drw 16
NOTE:
1. Write to Last Physical Location.
Figure 16. Write Expansion Out Timing
tCLKH
RCLK
Note 1
tXO
tXO
RXO
REN
tENS
4295 drw 17
NOTE:
1. Read from Last Physical Location.
Figure 17. Read Expansion Out Timing
t
XI
WXI
tXIS
WCLK
4295 drw 18
Figure 18. Write Expansion In Timing
t
XI
RXI
t
XIS
RCLK
4295 drw 19
Figure 19. Read Expansion In Timing
17
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
18
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
19
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
PAE
n Words in FIFO(2)
,
n words in FIFO(2)
,
n + 1 words in FIFO(2)
n + 2 words in FIFO(3)
,
n + 1 words in FIFO(3)
n + 1words in FIFO(3)
(4)
t
PAES
tSKEW2
t
PAES
RCLK
tENH
tENS
4295 drw 22
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
t
PAFS
D-(m+1) Words in FIFO
D -(m+1) Words
in FIFO
PAF
D - m Words in FIFO
(3)
SKEW2
t
t
PAFS
RCLK
tENH
tENS
4295 drw 23
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:
D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
20
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NO WRITE
NO WRITE
2
1
WCLK
1
2
(1)
SKEW1
(1)
SKEW1
tDS
tDS
t
t
DATA WRITE
Wd
D0
- D17
FF
t
WFF
tWFF
t
WFF
WEN
RCLK
tENH
tENH
tENS
tENS
REN
OE
LOW
tA
tA
NEXT DATA READ
DATA IN OUTPUT REGISTER
DATA READ
Q0
- Q17
4295 drw 24
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
tCLK
t
CLKH
tCLKL
1
2
WCLK
tDH
tDS
D0
-
D17
DATAIN VALID
tENH
tENS
NO OPERATION
WEN
FF
t
WFF
tWFF
(1)
tSKEW1
RCLK
REN
4295 drw 25
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle.
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 25. Write Cycle Timing with Double Register-Buffered FF (IDT Standard Mode)
21
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
1
2
RCLK
tENH
tENS
NO OPERATION
REN
EF
t
REF
t
REF
tA
Q0
-
Q17
LAST WORD
tOLZ
tOHZ
tOE
OE
(1)
SKEW1
t
WCLK
tENH
tENS
WEN
tDH
tDS
FIRST WORD
D0
-
D17
4295 drw 26
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle.
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 26. Read Cycle Timing with Double Register-Buffered EF (IDT Standard Timing)
WCLK
t
ENH
t
ENS
WEN
t
DS
t
DH
t
DS
W[n+3]
W4
W[n +2]
W1
W2
W3
D0
-
D17
(1)
t
SKEW1
2
1
RCLK
3
REN
t
A
Q0
-
Q17
DATA IN OUTPUT REGISTER
W1
t
REF
t
REF
4295 drw 27
OR
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and the
rising edge of RCLK is less than tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH, OE = LOW
3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
Figure 27. OR Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
22
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
application requirements are for 256/512/1,024/2,048/4,096 words or less.
These FIFOs are ina single Device Configurationwhenthe FirstLoad(FL),
Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are
configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
Each of the two FIFOs contained in a single IDT72V805/72V815/
72V825/72V835/72V845 may be used as a stand-alone device when the
RESET (RS)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
72V805
72V815
72V825
72V835
72V845
DATA IN (D0 - D17)
DATA OUT (Q0 - Q17)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAE)
HALF-FULL FLAG (HF)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE (PAF)
FL
RXI
WXI
4295 drw 28
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
(one of the two FIFOs contained in the IDT72V805/72V815/72V825/72V835/72V845)
WIDTH EXPANSION CONFIGURATION
Flags/Input Ready. Figure 29 demonstrates a 36-word width by using two
Word width may be increased simply by connecting together the control IDT72V805/72V815/72V825/72V835/72V845s. Any word width can be
signals ofFIFOAandB. Status flags canbe detectedfromanyone device. attainedbyaddingadditionalIDT72V805/72V815/72V825/72V835/72V845s.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input These FIFOs are ina single Device Configurationwhenthe FirstLoad(FL),
Ready. Because of variations in skew between RCLK and WCLK, it is Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are
possible for flag assertion and deassertion to vary by one cycle between configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
FIFOs. To avoid problems the user must create composite flags by gating (1,1,0) during reset (Figure 29). Please see the Application Note AN-83.
the EmptyFlags/OutputReadyofeveryFIFO, andseparatelygatingallFull
RESET (RS)
RESET (RS)
DATA IN (D) 36
18
18
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
WRITE ENABLE (WEN)
LOAD (LD)
PROGRAMMABLE (PAE)
HALF FULL FLAG (HF)
FIFO A
FIFO B
EMPTY FLAG/OUTPUT
READY (EF/OR)
FF/IR
EF/OR
FF/IR
EF/OR
18
DATA OUT (Q)
36
FULL FLAG/INPUT
READY (FF/IR)
FL WXI RXI
FL WXI RXI
18
4295 drw 29
NOTE:
1. Do not connect any output control signals directly together.
Figure 29. Block Diagram of the Two FIFOs Contained in One IDT72V805/72V815/72V825/72V835/72V845
Configured for a 36-Bit Width Expansion
23
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
(WITH PROGRAMMABLE FLAGS)
These devices caneasilybe adaptedtoapplications requiringmore than
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
ExpansionusingoneIDT72V805/72V815/72V825/72V835/72V845s. Maxi-
mum depth is limited only by signal loading. Follow these steps:
Write Expansion In (WXI) pin of the next device. See Figure 30.
4. TheReadExpansionOut(RXO)pinofeachdevicemustbetiedtothe
Read Expansion In (RXI) pin of the next device. See Figure 30
5. All Load (LD) pins are tied together.
6. The Half-Full flag (HF) is not available in this Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite PAE
and PAF flags are not precise.
8. InDaisyChainmode,theflagoutputs aresingleregister-bufferedand
the partial flags are in asynchronous timing mode.
1. The first device must be designated by grounding the First Load (FL)
control input.
2. All other devices must have FL in the HIGH state.
3. TheWriteExpansionOut(WXO)pinofeachdevicemustbetiedtothe
IDT72V845
WXOA RXOA
WCLKA
WENA
RSA
RCLKA
RENA
OEA
LDA
FIFO A
4,096 x 18
DAn
QAn
Vcc
FLA
FFA/IRA EFA/ORA
PAEA
PAFA
WXIA RXIA
DATA IN
DATA OUT
RXOB
RCLKB
RENB
WXOB
WRITE CLOCK
WRITE ENABLE
RESET
WCLKB
READ CLOCK
WENB
READ ENABLE
OUTPUT ENABLE
RSB
OEB
DBn
QBn
LDB
LOAD
FIFO B
4,096 x 18
FFA/IRA EFA/ORA
EF
FF
PAE
PAF
PAFB
WXIB
PAEB
RXIB
FIRST LOAD (FL)
4295 drw 30
Figure 30. Block Diagram of 8,192 x 18 Synchronous FIFO Memory with Programmable Flags
Used in Depth Expansion Configuration
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
emptyconfigurationwillpass fromone FIFOtothe next(“ripple down”)until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes LOW, enabling a write to the next FIFO in line.
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs
of one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 31 shows
adepthexpansionusingoneIDT72V805/72V815/72V825/72V835/72V845
devices.
24
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Foranemptyexpansionconfiguration, the amountoftime ittakes for OR created in one FIFO of the chain, that FIFO’s IR line goes LOW, enabling
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last the preceding FIFO to write a word to fill it.
FIFO’s outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
Fora fullexpansionconfiguration, the amountoftime ittakes for IR ofthe
first FIFO in the chain to go LOW after a word has been read from the last
FIFO is the sum of the delays for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK
period. Note that extra cycles should be added for the possibility that the where N is the number of FIFOs in the expansion and TWCLK is the WCLK
tSKEW1 specificationis notmetbetweenWCLKandtransferclock, orRCLK period. Note that extra cycles should be added for the possibility that the
and transfer clock, for the OR flag.
tSKEW1 specificationis notmetbetweenRCLKandtransferclock, orWCLK
The “ripple down” delay is only noticeable for the first word written to an and transfer clock, for the IR flag.
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
The first free location created by reading from a full depth expansion possible, to the end of the chain and free locations to the beginning of the
configuration will “bubble up” from the last FIFO to the previous one until it chain.
finally moves into the first FIFO of the chain. Each time a free location is
HF
HF
PAF
PAE
TRANSFER CLOCK
READ CLOCK
READ ENABLE
WRITE CLOCK
WRITE ENABLE
WCLK
WEN
IR
RCLK
WCLK
RCLK
OR
WEN
REN
72V805
72V815
72V825
72V835
72V845
72V805
72V815
72V825
72V835
72V845
INPUT READY
OUTPUT READY
OUTPUT ENABLE
REN
OE
OR
OE
Qn
IR
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
FL
RXI
FL
WXI
RXI
WXI
4295 drw 31
(0,1)
(0,1)
V
CC
VCC
GND
GND
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 Synchronous FIFO Memory
with Programmable Flags Used in Depth Expansion Configuration
25
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
XX
Speed
X
X
Power
Package
Process /
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Thin Quad Flatpack (TQFP, PK128-1)
Commercial Only
PF
10
15
20
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Com’l & Ind’l
Commercial Only
L
Low Power
72V805
72V815
72V825
72V835
72V845
256 x 18 3.3V Dual Synchronous FIFO
512 x 18 3.3V Dual Synchronous FIFO
1,024 x 18 3.3V Dual Synchronous FIFO
2,048 x 18 3.3V Dual Synchronous FIFO
4,096 x 18 3.3V Dual Synchronous FIFO
4295 drw 32
NOTE:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
DATASHEET DOUCUMENT HISTORY
04/26/2001
pgs. 1, 4, 5 and 26.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
408-330-1753
email: FIFOhelp@idt.com
www.idt.com*
PFPkg: www.idt.com/docs/PSC4045.pdf
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
26
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