IDT7383L30FF [IDT]

Bit-Slice Processor, 16-Bit, CMOS, FINE PITCH, FP-68;


型号：	IDT7383L30FF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bit-Slice Processor, 16-Bit, CMOS, FINE PITCH, FP-68 时钟输入元件外围集成电路
文件：	总7页 (文件大小：72K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT7014S

HIGH-SPEED

4K x 9 DUAL-PORT

STATIC RAM

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• True Dual-Ported memory cells which allow simultaneous

access of the same memory location

• High-speed access

The IDT7014 is an extremely high-speed 4K x 9 Dual-Port

Static RAM designed to be used in systems where on-chip

hardware port arbitration is not needed. This part lends itself

to high-speed applications which do not need on-chip arbitra-

tion to manage simultaneous access.

— Military: 20/25/35ns (max.)

— Commercial: 12/15/20/25ns (max.)

• Low-power operation

The IDT7014 provides two independent ports with separate

control, address, and I/O pins that permit independent,

asynchronous access for reads or writes to any location in

memory. See functional description.

The IDT7014 utilitizes a 9-bit wide data path to allow for

parity at the user's option. This feature is especially useful in

data communication applications where it is necessary to use

a parity bit for transmission/reception error checking.

Fabricated using IDT’s high-performance technology, the

IDT7014 Dual-Ports typically operate on only 900mW of

power at maximum access times as fast as 12ns.

— IDT7014S

Active: 900mW (typ.)

• Fully asynchronous operation from either port

• TTL-compatible; single 5V (±10%) power supply

• Available in 52-pin PLCC and a 64-pin TQFP

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

The IDT7014 is packaged in a 52-pin PLCC and a 64-pin

thin plastic quad flatpack (TQFP).

FUNCTIONAL BLOCK DIAGRAM

R/W

R/WR

OEL

OER

COLUMN

CONTROL

COLUMN

CONTROL

I/O0L- I/O8L

I/O0R- I/O8R

LEFT SIDE

ADDRESS

DECODE

LOGIC

RIGHT SIDE

ADDRESS

DECODE

LOGIC

MEMORY

ARRAY

0L- A11L

A0R- A11R

2528 drw 01

The IDT logo is a registereed trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OCTOBER 1996

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

DSC-2528/6

6.11

IDT7014S

HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS^(1,2)

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

Symbol

Rating

Commercial

Military Unit

(2)

VTERM

Terminal Voltage

with Respect to

GND

–0.5 to +7.0 –0.5 to +7.0

INDEX

6 5 4 3 2

5251 50 4948 47

(3)

VTERM

Terminal Voltage

–0.5 to Vcc

0 to +70

–0.5 to Vcc

Operating

Temperature

–55 to +125 °C

10R

11R

TBIAS

TSTG

Temperature

Under Bias

–55 to +125 –65 to +135 °C

–55 to +125 –65 to +150 °C

10L

11L

IDT 7014

J52-1

PLCC

GND

R/W

Storage

Temperature

(3)

Top View

GND

I/O8R

I/O7R

I/O6R

I/O5R

R/W

IOUT

DC Output Current

GND

I/O8L

I/O7L

NOTES:

2528 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

onlyandfunctionaloperationofthedeviceattheseoranyotherconditions

abovethoseindicatedintheoperationalsectionsofthisspecificationisnot

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

I/O6L

21 2223 24 2526 27 2829 30 3132 33

2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time

or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc

+ 0.5V.

2528 drw 02

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Ambient

INDEX

Grade

Temperature

–55°C to +125°C

0°C to +70°C

GND

VCC

Military

5.0V ± 10%

Commercial

5.0V ± 10%

A10L

10R

11R

2528 tbl 02

A11L

IDT7014

PN64-1

TQFP

OEL

N/C

GND

N/C

GND

I/O8R

I/O7R

I/O6R

RECOMMENDED DC OPERATING

CONDTIONS

VCC

(3)

N/C

Top View

Symbol

Parameter

Supply Voltage

Input High Voltage

Min.

4.5

Typ.

5.0

Max. Unit

N/C

GND

I/O8L

I/O7L

I/O6L

VCC

5.5

GND

VIH

2.2

—

6.0⁽²⁾

0.8

VIL

Input Low Voltage –0.5⁽¹⁾

—

NOTES:

2528 tbl 03

2528 drw 03

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 0.5V.

NOTES:

1. All VCC pins must be connected to power supply.

2. All ground pins must be connected to ground supply.

3. This text does not indicate the orientation of the actual part-marking

6.11

IDT7014S

HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)

IDT7014S

Symbol

|ILI|

Parameter

Input Leakage Current

Test Condition

VCC = 5.5V, VIN = 0V to VCC

VOUT = 0V to VCC

IOL = 4mA

Min.

—

Max.

Unit

µA

0.4

—

|ILO|

Output Leakage Current

Output Low Voltage

Output High Voltage

—

VOL

—

VOH

IOH = –4mA

2.4

2528 tbl 04

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5V ± 10%)

IDT7014S12

Com'l. Only

IDT7014S15 IDT7014S20 IDT7014S25 IDT7014S35

Com'l. Only Mil. Only

Typ. Max. Typ. Max. Typ. Max. Unit

Test

Symbol Parameter

Condition Version Typ. Max. Typ.

Max.

ICC

Dynamic

Operating

Outputs Open Mil.

f = fMAX

—

160

260

155

260

150

255

150

250

(1)

Current (Both

Ports Active)

Com’l. 160 250

160

250

155

245

150

240

—

NOTE:

2528 tbl 05

1. At f = fmax, address inputs are cycling at the maximum read cycle of 1/tRC using the "AC Test Conditions" input levels of GND to 3V.

AC TEST CONDITIONS

Input Pulse Levels

893Ω

GND to 3.0V

DATAOUT

BUSY

INT

DATAOUT

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

3ns

1.5V

347Ω

5pF

347Ω

30pF

1.5V

2528 drw 05

2528 drw 04

Figures 1, 2, and 3

2528 tbl 06

Figure 2. Output Test Load

(for tHZ, tWZ, and tOW)

Including scope and jig.

Figure 1. AC Output Test Load.

CAPACITANCE⁽¹⁾

(TA = +25°C, f = 1.0MHz) TQFP Package Only

(2)

Symbol

Parameter

Condition

VIN = 3dV

VOUT = 3dV

Max. Unit

CIN

Input Capacitance

Output Capacitance

COUT

2528 tbl 07

NOTES:

- 10pF is the I/O capacitance

of this device, and 3 pF is the

AC Test Load Capacitance

1. This parameter is determined by device characteristics but is not tested.

2. 3dv references the interperlated capacitance when the input and output

signals swith from 0V to 3V or from 3V to 0V.

∆tAA

(Typical, ns)

20 40 60 80 100 120 140 160 180 200

Capacitance (pF)

-1

2528 drw 06

Figure 3. Typical Output Derating (Lumped Capacitive Load).

6.11

IDT7014S

HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE

7014S12

7014S15

7014S20

7014S25

7014S35

Mil. Only

Com'l. Only Com'l. Only

Symbol

Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Unit

READ CYCLE

tRC

tAA

Read Cycle Time

Address Access Time

—

tAOE

tOH

tLZ

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^{(1, 2)}

—

tHZ

Output High-Z Time^{(1, 2)}

—

NOTES:

2528 tbl 08

1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is determined by device characterization, but is not production tested.

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE^(1,2)

tRC

ADDRESS

DATAOUT

tOH

PREVIOUS DATA VALID

DATA VALID

2528 drw 07

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE^{(1, 3)}

tAOE

tLZ

VALID DATA

DATAOUT

2528 drw 08

NOTES:

1. R/W = VIH for Read Cycles.

2. OE = VIL.

3. Addresses valid prior to OE transition LOW.

6.11

IDT7014S

HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE

7014S12

7014S15

7014S20

7014S25

7014S35

Mil. Only

Com'l. Only Com'l. Only

Symbol

Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Unit

WRITE CYCLE

tWC

tAW

tAS

Write Cycle Time

—

Address Valid to End-of-Write

Address Set-up Time

tWP

tWR

tDW

tHZ

Write Pulse Width

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^{(1, 2)}

Data Hold Time⁽³⁾

—

tDH

tWZ

—

Write Enabled to Output in High-Z^{(1, 2)}

—

tOW

tWDD

Output Active from End-of-Write^{(1, 2, 3)}

Write Pulse to Data Delay⁽⁴⁾

Write Data Valid to Read Data Delay⁽⁴⁾

—

tDDD

NOTES:

2528 tbl 09

1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

over voltage and temperature, the actual tDH will always be smaller than the actual tOW.

4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write With Port-to-Port Read”.

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ ^(1,2)

tWC

ADDR"A"

R/W"A"

MATCH

tWP

tDH

DATAIN "A"

ADDR"B"

VALID

MATCH

tWDD

DATAOUT "B"

VALID

tDDD

NOTES:

1. R/W"B" = VIH, Read cycle pass through.

2528 drw 09

2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is opposite from port "A".

6.11

IDT7014S

HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE^{(1, 2, 3, 4, 5)}

ADDRESS

(5)

tWR

R/W

DATAOUT

DATAIN

(4)

(3)

tDH

2528 drw 10

NOTES:

1. R/W must be HIGH during all address transitions.

2. tWR is measured from R/W going HIGH to the end of write cycle.

3. During this period, the I/O pins are in the output state, and input signals must not be applied.

4. Transition is measured ±200mV from the Low or High-impedance voltage with the Output Test Load (Figure 2).

5. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to

be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can

be as short as the specified tWP.

FUNCTIONAL DESCRIPTION

TABLE I – READ/WRITE CONTROL

Left or Right Port⁽¹⁾

The IDT7014 provides two ports with separate control,

address, and I/O pins that permit independent access for

reads or writes to any location in memory. It lacks the chip

enable feature of most Dual-Ports, thus it operates in active

mode as soon as power is applied. Each port has its own

Output Enable control (OE). In the read mode, the port’s OE

turnsontheoutputdriverswhensetLOW. Theuserapplication

should avoid simultaneous write operations to the same

memory location. There is no on-chip arbitration circuitry to

resolve write priority and partial data from both ports may be

written. READ/WRITE conditions are illustrated in Table 1.

R/W

D0-8

Function

DATAIN

Data written into memory

DATAOUT

Data in memory output on port

High-impedance outputs

NOTE:

2528 tbl 10

1. AOL - A11L is not equal to AOR - A11R.

'H' = HIGH,'L' = LOW, 'X' = Don’t Care, and 'Z' = High-impedance.

6.11

IDT7014S

HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

999

XXXX

Device Type Power

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

64-pin TQFP (PN64-1)

52-pin PLCC (J52-1)

Commercial Only

Speed in nanoseconds

Military Only

Standard Power

7014

36K (4K x 9-Bit) Dual-Port RAM

2528 drw 11

6.11

IDT7383L30FF [IDT]

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