IDT74ALVCH16374PF8 [IDT]

Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.40 MM PITCH, TVSOP-48;


型号：	IDT74ALVCH16374PF8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.40 MM PITCH, TVSOP-48 光电二极管电视
文件：	总6页 (文件大小：72K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74ALVCH16374

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPELATCHWITH3-STATEOUTPUTS

3.3V CMOS 16-BIT EDGE-

TRIGGERED D-TYPE

IDT74ALVCH16374

LATCH WITH 3-STATE

OUTPUTS AND BUS-HOLD

FEATURES:

DESCRIPTION:

• 0.5 MICRON CMOS Technology

This16-bitedge-triggeredD-typeflip-flopisbuiltusingadvanceddualmetal

CMOStechnology.TheALVCH16374isparticularlysuitableforimplementing

bufferregisters,I/Oports,bidirectionalbusdrivers,andworkingregisters.Itcan

beusedastwo8-bitflip-flopsorone16-bitflip-flop.Onthepositivetransitionof

theclock(CLK)input,theQoutputsoftheflip-floptakeonthelogiclevelsatthe

data(D)inputs.OEcanbeusedtoplacetheeightoutputsineitheranormallogic

state(highorlowlogiclevels)orahigh-impedancestate.Inthehigh-impedance

state, the outputs neitherloadnordrive the bus lines significantly. The high-

impedancestateandtheincreaseddriveprovidethecapabilitytodrivebuslines

withoutneedforinterface orpullupcomponents.OE does notaffectinternal

operationsoftheflip-flop.Olddatacanberetainedornewdatacanbeentered

whiletheoutputsareinthehigh-impedancestate.

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

The ALVCH16374 has been designed with a ±24mA output driver. This

driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed

performance.

The ALVCH16374 has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputsand

eliminatestheneedforpull-up/downresistor.

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

FUNCTIONALBLOCKDIAGRAM

2OE

1OE

2CLK

1CLK

1Q1

2Q1

1D1

2D1

TO 7 OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

APRIL 1999

DSC-4564/2

IDT74ALVCH16374

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPELATCHWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

Description

Max

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +4.6

(3)

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

1CLK

1OE

1Q1

1Q2

TSTG

IOUT

IIK

Storage Temperature

DC Output Current

–65 to +150

–50 to +50

±50

° C

1D1

1D2

GND

1D3

1D4

Continuous Clamp Current,

VI < 0 or VI > VCC

GND

1Q3

1Q4

V^CC

1Q5

1Q6

GND

1Q7

IOK

Continuous Clamp Current, VO < 0

–50

ICC

ISS

Continuous Current through each

VCC or GND

±100

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

V^CC

1D5

1D6

2. V^CCterminals.

3. All terminals except V^CC.

GND

1D7

1D8

2D1

2D2

CAPACITANCE (TA = +25°C, F = 1.0MHz)

1Q8

2Q1

2Q2

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

COUT

CI/O

GND

2Q3

2Q4

VCC

2Q5

GND

2D3

NOTE:

1. As applicable to the device type.

2D4

PINDESCRIPTION

VCC

2D5

2D6

GND

2D7

Pin Names

Description

xDx

xCLK

xQx

Data Inputs⁽¹⁾

Clock Inputs

3-State Outputs

2Q6

GND

2Q7

xOE

3-State Output Enable Input (Active LOW)

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

2D8

2Q8

2CLK

2OE

(1)

FUNCTION TABLE (EACH FLIP-FLOP)

Inputs

xCLK

↑

Output

xQx

SSOP/ TSSOP/ TVSOP

TOP VIEW

xOE

xDx

↑

(2)

H or L

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

↑ = LOW-to-HIGH Transition

2. Output level before the indicated steady-state input conditions were established.

IDT74ALVCH16374

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPELATCHWITH3-STATEOUTPUTS

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

Input HIGH Current

VCC = 3.6V

VI = VCC

—

µA

µ A

Input LOW Current

VI = GND

VO = VCC

VO = GND

IOZH

IOZL

VIK

High Impedance Output Current

(3-State Output pins)

—

Clamp Diode Voltage

VCC = 2.3V, IIN = –18mA

VCC = 3.3V

–0.7

–1.2

Input Hysteresis

—

100

0.1

—

µ A

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

—

750

µ A

NOTE:

1. Typical values are at VCC = 3.3V, +25°C ambient.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µ A

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-HoldInputOverdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

–45

—

µ A

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74ALVCH16374

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPELATCHWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, TA = 25°C

VCC = 2.5V ± 0.2V

VCC = 3.3V ± 0.3V

Symbol

CPD

Parameter

Test Conditions

Typical

Unit

PowerDissipationCapacitanceOutputsenabled

PowerDissipationCapacitanceOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

fMAX

tPLH

Parameter

Min.

150

Max.

—

Min.

150

—

Max.

Min.

150

Max.

—

Unit

—

MHz

PropagationDelay

5.3

4.9

4.2

tPHL

xCLK to xQx

tPZH

tPZL

OutputEnableTime

6.2

5.3

—

5.9

4.7

4.8

4.3

xOE to xQx

tPHZ

tPLZ

OutputDisableTime

xOE to xQx

1.2

tSU

Set-upTime,databeforeCLK↑

HoldTime,dataafterCLK↑

Pulse Duration, CLK HIGH or LOW

2.1

0.6

3.3

—

2.2

0.5

3.3

—

1.9

0.5

3.3

—

(2)

tSK(o)

OutputSkew

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

Skew between any two outputs of the same package and switching in the same direction.

IDT74ALVCH16374

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPELATCHWITH3-STATEOUTPUTS

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

tPHL

tPLH

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V Unit

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

VIH

Vcc / 2

150

OPPOSITE PHASE

INPUT TRANSITION

VLZ

VHZ

150

ALVC Link

Propagation Delay

VLOAD

Open

GND

DISABLE

VCC

ENABLE

VIH

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

(1, 2)

Pulse

VLOAD/2

D.U.T.

VLOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

Generator

V^LZ

VOL

CLOSED

500Ω

tPHZ

tPZH

OUTPUT

NORMALLY

HIGH

VOH

VHZ

SWITCH

OPEN

ALVC Link

Test Circuit for All Outputs

ALVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

VIH

1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.

DATA

INPUT

t^SU

VIH

TIMING

INPUT

SWITCHPOSITION

Test

Switch

V^LOAD

GND

Open

tREM

VIH

ASYNCHRONOUS

CONTROL

Open Drain

Disable Low

Enable Low

VIH

SYNCHRONOUS

CONTROL

Disable High

Enable High

tSU

ALVC Link

All Other Tests

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

PULSE

OUTPUT 1

OUTPUT 2

VOL

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

ALVC Link

tPLH2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

tPHL2

Pulse Width

ALVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH16374

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPELATCHWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

Device Type Package

IDT

ALVC

XXX

Temp. Range

Bus-Hold

Family

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

16-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs

374

Double-Density, 24mA

Bus-Hold

– 40°C to +85°C

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