IDT74ALVCH16525PF8 [IDT]

Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56;


型号：	IDT74ALVCH16525PF8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56 光电二极管电视
文件：	总7页 (文件大小：75K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74ALVCH16525

INDUSTRIALTEMPERATURERANGE

3.3VCMOS18-BITREGISTEREDBUSTRANSCEIVERWITH3-STATEOUTPUTS

3.3V CMOS 18-BIT

IDT74ALVCH16525

REGISTERED BUS TRANS-

CEIVER WITH 3-STATE

OUTPUTS AND BUS-HOLD

FEATURES:

DESCRIPTION:

• 0.5 MICRON CMOS Technology

This 18-bit registered bus transceiver is built using advanced dual metal

CMOStechnology.Dataflowineachdirectioniscontrolledbyoutput-enable

(OEABandOEBA)andclock-enable(CLKENABandCLKENBA)inputs.For

theA-to-Bdataflow,thedataflowsthroughasingleregister.TheB-to-Adata

canflowthroughafour-stagepipelineregisterpath,orthroughasingleregister

path,dependingonthestateoftheselect(SEL)input.Dataisstoredintheinternal

registersonthelow-to-hightransitionoftheclock(CLK)input,providedthatthe

appropriateCLKENinputsarelow.TheA-to-Bdatatransferissynchronized

totheCLKABinput,andB-to-AdatatransferissynchronizedwiththeCLK1BA

andCLK2BAinputs.

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4µ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in SSOP, TSSOP, and TVSOP packages

The ALVCH16525 has been designed with a ±24mA output driver. This

driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed

performance.

The ALVCH16525 has “bus-hold” which retains the inputs’ last state

whenevertheinputbusgoestoahighimpedance.Thispreventsfloatinginputs

andeliminatestheneedforpull-up/downresistors.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

FUNCTIONALBLOCKDIAGRAM

CLKAB

CLK1BA

CLK2BA

CLKENBA

CLKENAB

OEAB

OEBA

SEL

A¹

B¹

1 of 18 Channels

To 17 Other Channels

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

APRIL 1999

DSC-4694/2

IDT74ALVCH16525

3.3VCMOS18-BITREGISTEREDBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

Description

Max

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +4.6

(3)

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

CLKENAB

OEAB

SEL

CLKAB

TSTG

IOUT

IIK

Storage Temperature

DC Output Current

–65 to +150

–50 to +50

±50

°C

Continuous Clamp Current,

VI < 0 or VI > VCC

GND

IOK

Continuous Clamp Current, VO < 0

–50

ICC

ISS

Continuous Current through each

VCC or GND

±100

NOTES:

VCC

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

GND

2. V^CCterminals.

3. All terminals except V^CC.

GND

A10

A11

B10

B11

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

A12

GND

A13

B12

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

GND

COUT

CI/O

B13

B14

B15

NOTE:

A14

1. As applicable to the device type.

A15

VCC

A16

VCC

B16

A17

B17

PINDESCRIPTION

GND

A18

Pin Names

CLKAB

Description

B18

Clock Input for the A to B direction

CLK1BA

CLK2BA

OEBA

CLK1BA

CLK2BA

Clock Input for the B to A pipeline register

Clock Input for the B to A output register

CLKENBA

CLKENBA Clock Enable for CLK1BA and CLK2BA clocks (Active LOW)

CLKENAB Clock Enable for CLKAB clock (Active LOW)

SSOP/ TSSOP/ TVSOP

TOP VIEW

OEAB

OEBA

SEL

Output Enable for the B port (Active LOW)

Output Enable for the A port (Active LOW)

Select pin for pipelined/non-pipelined mode in the B-to-A direction

(Active LOW)

A-to-B Data Inputs or B-to-A 3-State Outputs⁽¹⁾

B-to-A Data Inputs or A-to-B 3-State Outputs⁽¹⁾

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

IDT74ALVCH16525

INDUSTRIALTEMPERATURERANGE

3.3VCMOS18-BITREGISTEREDBUSTRANSCEIVERWITH3-STATEOUTPUTS

FUNCTIONTABLE⁽¹⁾

A-TO-B STORAGE (OEAB = L, OEBA = H)

B-TO-A STORAGE (OEBA = L, OEAB = H)

Inputs

Output

Inputs

Output

A⁽²⁾

CLKENAB

CLKAB

B⁽²⁾

CLKENBA CLK2BA CLK1BA

SEL

↑

L⁽³⁾

H⁽³⁾

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

↑ = LOW-to-HIGH Transition

2. Output level before the indicated steady-state input conditions were established.

3. Three CLK1BA edges and one CLK2BA are needed to propagate data from B to A when SEL is LOW.

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

Input HIGH Current

VCC = 3.6V

VI = VCC

—

±5

µA

Input LOW Current

VI = GND

VO = VCC

VO = GND

IOZH

IOZL

VIK

High Impedance Output Current

(3-State Output pins)

—

±10

–1.2

—

Clamp Diode Voltage

VCC = 2.3V, IIN = –18mA

VCC = 3.3V

–0.7

Input Hysteresis

—

100

0.1

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

—

750

µA

NOTE:

1. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74ALVCH16525

3.3VCMOS18-BITREGISTEREDBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µA

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-Hold Input Overdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

–45

—

µA

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC – 0.2

1.7

2.2

2.4

—

VCC = 2.3V

—

VCC = 2.7V

—

VCC = 3V

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

IOL = 12mA

IOL = 24mA

VCC = 2.7V

VCC = 3V

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, TA = 25°C

VCC = 2.5V ± 0.2V

VCC = 3.3V ± 0.3V

Symbol

CPD

Parameter

Test Conditions

Typical

—

Typical

160

Unit

PowerDissipationCapacitanceOutputsenabled

PowerDissipationCapacitanceOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

—

160

IDT74ALVCH16525

INDUSTRIALTEMPERATURERANGE

3.3VCMOS18-BITREGISTEREDBUSTRANSCEIVERWITH3-STATEOUTPUTS

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

fMAX

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Parameter

Min.

120

Max.

—

Min.

125

—

Max.

—

Min.

150

Max.

—

Unit

MHz

PropagationDelay

4.5

4.4

4.2

CLKAB to Bx or CLK2BA to Ax

OutputEnableTime

6.1

6.3

—

6.1

5.4

5.1

4.9

OEAB to Bx or OEBA to Ax

OutputDisableTime

OEAB to Bx or OEBA to Ax

Set-up Time, Ax data before CLKAB↑

Set-up Time, Bx data before CLK2BA↑

Set-up Time, Bx data before CLK1BA↑

Set-up Time, SEL before CLK2BA↑

Set-up Time, CLKENAB before CLKAB↑

Set-up Time, CLKENBA before CLK1BA↑

Set-up Time, CLKENBA before CLK2BA↑

Hold Time, Ax data after CLKAB↑

Hold Time, Bx data after CLK2BA↑

Hold Time, Bx data after CLK1BA↑

Hold Time, SEL after CLK2BA↑

Hold Time, CLKENAB after CLKAB↑

Hold Time, CLKENBA after CLK1BA↑

Hold Time, CLKENBA after CLK2BA↑

Pulse Duration, CLK HIGH or LOW

OutputSkew⁽²⁾

1.3

2.1

1.3

3.3

2.1

2.7

0.7

0.4

0.8

—

1.3

1.8

1.2

3.3

1.9

2.5

0.4

—

1.3

1.7

1.1

3.3

1.6

2.1

2.2

0.9

0.6

—

500

tSU

0.4

0.1

0.3

0.1

0.3

3.2

—

3.2

—

t^SK(o)

NOTES:

—

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

Skew between any two outputs of the same package and switching in the same direction.

IDT74ALVCH16525

3.3VCMOS18-BITREGISTEREDBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

tPHL

tPLH

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

VIH

Vcc / 2

150

OPPOSITE PHASE

INPUT TRANSITION

VLZ

VHZ

150

ALVC Link

Propagation Delay

VLOAD

Open

GND

DISABLE

VCC

ENABLE

VIH

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

(1, 2)

Pulse

VLOAD/2

D.U.T.

VLOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

Generator

V^LZ

VOL

500Ω

tPHZ

tPZH

OUTPUT

NORMALLY

HIGH

VOH

VHZ

SWITCH

OPEN

ALVC Link

Test Circuit for All Outputs

ALVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

VIH

1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

DATA

INPUT

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.

t^SU

VIH

TIMING

INPUT

SWITCHPOSITION

Test

Switch

V^LOAD

GND

tREM

ASYNCHRONOUS

CONTROL

Open Drain

Disable Low

Enable Low

SYNCHRONOUS

CONTROL

Disable High

Enable High

tSU

ALVC Link

All Other Tests

Open

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

VOL

LOW-HIGH-LOW

PULSE

OUTPUT 1

OUTPUT 2

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

ALVC Link

tPLH2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

tPHL2

Pulse Width

ALVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH16525

INDUSTRIALTEMPERATURERANGE

3.3VCMOS18-BITREGISTEREDBUSTRANSCEIVERWITH3-STATEOUTPUTS

ORDERINGINFORMATION

ALVC

IDT

XXX

Device Type Package

Bus-Hold Family

Temp. Range

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

18-Bit Registered Bus Transceiver with 3-State Outputs

525

Double-Density with Resistors, ±24mA

Bus-Hold

-40°C to +85°C

CORPORATE HEADQUARTERS

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Santa Clara, CA 95054

for SALES:

for Tech Support:

logichelp@idt.com

(408) 654-6459

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

IDT74ALVCH16525PF8 [IDT]

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