IDT74ALVCH16601PV8 [IDT]

Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56;


型号：	IDT74ALVCH16601PV8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, ALVC/VCX/A Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56 光电二极管输出元件逻辑集成电路
文件：	总7页 (文件大小：111K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74ALVCH16601

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER

EXTENDED COMMERCIAL TEMPERATURE RANGE

3.3V CMOS 18-BIT UNIVER-

SAL BUS TRANSCEIVER

IDT74ALVCH16601

WITH 3-STATE OUTPUTS

AND BUS-HOLD

FEATURES:

D-type flip-flops to allow data flow in transparent, latched, and clocked

modes.

–

0.5 MICRON CMOS Technology

Typicalt^SK(0)(Output Skew) < 250ps

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

0.635mm pitch SSOP, 0.50mm pitch TSSOP,

and 0.40mm pitch TVSOP packages

Data flow in each direction is controlled by output-enable (OEAB and

OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)

inputs. The clock can be controlled by the clock-enable (CLKENAB and

CLKENBA) inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is high. When LEAB is low, the A data is

latched if CLKAB is held at a high or low logic level. If LEAB is low, the

data is stored in the latch/flip-flop on the low-to-high transition of CLKAB.

Output enable OEAB is active low. When OEAB is low, the outputs are

active. When OEAB is high, the outputs are in the high-impedance state.

–

Extended commercial range of – 40°C to + 85°C

V^CC= 3.3V ± 0.3V, Normal Range

V^CC= 2.7V to 3.6V, Extended Range

V^CC= 2.5V ± 0.2V

CMOS power levels (0.4µW typ. static)

Rail-to-Rail output swing for increased noise margin

Drive Features for ALVCH16601:

Data flow for B to A is similar to that of A to B but uses OEBA, LEBA,

CLKBA and CLKENBA.

–

High Output Drivers: ±24mA

Suitable for heavy loads

The ALVCH16601 has been designed with a ±24mA output driver.

This driver is capable of driving a moderate to heavy load while

maintaining speed performance.

APPLICATIONS:

• 3.3V High Speed Systems

• 3.3V and lower voltage computing systems

The ALVCH16601 has “bus-hold” which retains the inputs’ last state

This 18-bit universal bus transceiver is built using advanced dual metal whenever the input goes to a high impedance. This prevents floating

DESCRIPTION:

CMOS technology. The ALVCH16601 combines D-type latches and

inputs and eliminates the need for pull-up/down resistors.

Functional Block Diagram

OEAB

CLKENAB

CLKAB

LEAB

LEBA

CLKBA

CLKENBA

OEBA

CLK

TO 17 OTHER CHANNELS

EXTENDED COMMERCIAL TEMPERATURE RANGE

APRIL 1999

1999 Integrated Device Technology, Inc.

DSC-4732/-

IDT74ALVCH16601

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER

EXTENDED COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATING ⁽¹⁾

PIN CONFIGURATION

Symbol

Description

Terminal Voltage

Max.

Unit

(2)

VTERM

– 0.5 to + 4.6

OEAB

LEAB

A¹

CLKENAB

with Respect to GND

Terminal Voltage

CLKAB

B¹

(3)

VTERM

– 0.5 to

VCC + 0.5

with Respect to GND

Storage Temperature

TSTG

IOUT

IIK

– 65 to + 150

°C

GND

A²

GND

DC Output Current

– 50 to + 50

± 50

Continuous Clamp Current,

VI < 0 or VI > VCC

Continuous Clamp Current, VO < 0

A³

IOK

– 50

V^CC

B⁴

ICC

ISS

Continuous Current through

each VCC or GND

±100

A⁴

A⁵

NEW16link

B⁵

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

2. V^CCterminals.

A⁶

B⁶

GND

A⁷

GND

B⁷

A⁸

B⁸

B⁹

SO56-1

SO56-2

SO56-3

3. All terminals except V^CC.

A⁹

A¹⁰

A¹¹

A¹²

B¹¹

B¹²

CAPACITANCE (T^A= +25^oC, f = 1.0MHz)

GND

A¹³

GND

Symbol

Parameter⁽¹⁾

Conditions

Typ.

Max.

Unit

CIN

Input Capacitance

VIN = 0V

B¹³

B¹⁴

B¹⁵

A¹⁴

COUT

CI/O

Output

Capacitance

I/O Port

VOUT = 0V

VIN = 0V

A¹⁵

V^CC

A¹⁶

V^CC

B¹⁶

B¹⁷

Capacitance

NEW16link

NOTE:

1. As applicable to the device type.

GND

A¹⁸

GND

B¹⁸

PIN DESCRIPTION

CLKBA

OEBA

LEBA

Pin Names

Description

CLKENBA

OEAB

OEBA

LEAB

LEBA

CLKAB

CLKBA

A-to-B Output Enable Input (Active LOW)

B-to-A Output Enable Input (Active LOW)

A-to-B Latch Enable Input

SSOP/TSSOP/TVSOP

TOP VIEW

B-to-A Latch Enable Input

A-to-B Clock Input

B-to-A Clock Input

A-to-B Data Inputs or B-to-A 3-State Outputs⁽¹⁾

B-to-A Data Inputs or A-to-B 3-State Outputs⁽¹⁾

A-to-B Clock Enable Input (Active LOW)

B-to-A Clock Enable Input (Active LOW)

CLKENAB

CLKENBA

NOTE:

1. These pins have “Bus-Hold.” All other pins are standard inputs,

outputs, or I/Os.

IDT74ALVCH16601

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER

EXTENDED COMMERCIAL TEMPERATURE RANGE

(1, 2)

FUNCTION TABLE

Inputs

Output

CLKENAB

OEAB

LEAB

CLKAB

↑

Lor H

NOTES:

1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,

LEBA, CLKBA and CLKENBA.

2. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

↑ = LOW-to-HIGHTransition

B0 = Indicates the previous state

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = – 40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

Typ.⁽¹⁾

Max.

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 3.6V

1.7

—

0.7

VIL

Input LOW Voltage Level

—

0.8

IIH

Input HIGH Current

VI = VCC

—

± 5

± 10

– 1.2

—

µA

IIL

Input LOW Current

VCC = 3.6V

VI = GND

VO = VCC

VO = GND

—

IOZH

IOZL

VIK

High Impedance Output Current

(3-State Output pins)

Clamp Diode Voltage

Input Hysteresis

VCC = 3.6V

—

µA

—

VCC = 2.3V, IIN = – 18mA

VCC = 3.3V

– 0.7

100

0.1

µA

ICCL

ICCH

ICCZ

∆ICC

VCC = 3.6V

VIN = GND or VCC

Quiescent Power Supply Current

Quiescent Power Supply

Current Variation

One input at VCC − 0.6V,

other inputs at VCC or GND

—

750

µA

NEW16link

NOTE:

1. Typical values are at V^CC= 3.3V, +25°C ambient.

IDT74ALVCH16601

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER

EXTENDED COMMERCIAL TEMPERATURE RANGE

BUS-HOLD CHARACTERISTICS

Symbol

Parameter⁽¹⁾

Test Conditions

VI = 2.0V

Min.

Typ.⁽²⁾

Max.

Unit

IBHH

Bus-Hold Input Sustain Current

VCC = 3.0V

VCC = 2.3V

VCC = 3.6V

– 75

—

µA

IBHL

VI = 0.8V

– 45

—

IBHH

IBHL

Bus-Hold Input Sustain Current

Bus-Hold Input Overdrive Current

VI = 1.7V

µA

VI = 0.7V

—

IBHHO

IBHLO

VI = 0 to 3.6V

—

± 500

µA

NEW16link

NOTES:

1. Pins with Bus-hold are identified in the pin description.

2. Typical values are at V^CC= 3.3V, +25°C ambient.

OUTPUT DRIVE CHARACTERISTICS

Symbol

Parameter

Test Conditions⁽¹⁾

Min.

Max.

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC – 0.2

—

VCC = 2.3V

1.7

2.2

2.4

—

VCC = 2.7V

—

VCC = 3.0V

—

VCC = 3.0V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

Output LOW Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3.0V

—

NEW16link

NOTE:

1. V^IHand V^ILmust be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the

appropriate V^CCrange. T^A= – 40°C to + 85°C.

IDT74ALVCH16601

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER

EXTENDED COMMERCIAL TEMPERATURE RANGE

OPERATING CHARACTERISTICS, T = 25 C

VCC = 2.5V ± 0.2V

VCC = 3.3V ± 0.3V

Unit

Symbol

Parameter

Power Dissipation Capacitance

Outputs enabled

Test Conditions

Typical

CPD

CL = 0pF, f = 10Mhz

CPD

Power Dissipation Capacitance

Outputs disabled

(1)

SWITCHING CHARACTERISTICS

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

Parameter

Min.

150

Max.

—

Min.

150

—

Max.

Min.

150

—

Max.

—

Unit

fMAX

—

MHz

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Propagation Delay

Ax to Bx or Bx to Ax

Propagation Delay

LEAB to Bx or LEBA to Ax

Propagation Delay

4.6

4.1

4.6

5.2

5.3

4.9

—

5.3

5.8

6.1

4.8

—

4.7

1.2

1.1

1.4

CLKAB to Bx or CLKBA to Ax

Output Enable Time

OEAB to Bx or OEBA to Ax

Output Disable Time

OEAB to Bx or OEBA to Ax

Setup Time, data before CLK↑

5.2

4.4

2.3

—

2.4

1.6

1.2

—

2.1

1.6

1.1

1.7

0.8

1.4

1.7

0.6

3.3

—

500

tSU

Setup Time, data before LE↓, CLK HIGH

Setup Time, data before LE↓, CLK LOW

Setup Time, CLKEN before CLK↑

Hold Time, data after CLK↑

1.3

0.7

1.3

1.7

0.3

3.3

—

0.7

1.6

Hold Time, data after LE↓, CLK HIGH

Hold Time, data after LE↓, CLK LOW

Hold Time, CLKEN after CLK↑

0.5

3.3

—

Pulse Width, LE HIGH

Pulse Width, CLK HIGH or LOW

(2)

tSK(o) Output Skew

NOTES:

1. See test circuits and waveforms. T^A= – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74ALVCH16601

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER

EXTENDED COMMERCIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS:

PROPAGATION DELAY

TEST CONDITIONS

Symbol

(1)

(2)

VCC = 3.3V±0.3V VCC = 2.7V VCC = 2.5V±0.2V

Unit

VLOAD

2 xVcc

Vcc

SAME PHASE

INPUT TRANSITION

VIH

2.7

1.5

300

2.7

1.5

300

t^PHL

t^PLH

VOH

Vcc / 2

150

OUTPUT

VLZ

VHZ

VOL

t^PHL

t^PLH

150

VIH

OPPOSITE PHASE

INPUT TRANSITION

NEW16link

ALVC Link

TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES

V^LOAD

DISABLE

V^CC

ENABLE

V^IH

V^T

Open

GND

CONTROL

INPUT

500Ω

t^PZL

t^PLZ

V^IN

V^OUT

Pulse^{(1, 2)}

Generator

V^LOAD/2

V^T

D.U.T.

V^LOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

V^LZ

V^OL

500Ω

t^PHZ

PZH

R^T

C^L

OUTPUT

NORMALLY

HIGH

V^OH

V^HZ

SWITCH

OPEN

V^T

ALVC Link

DEFINITIONS:

C^L= Load capacitance: includes jig and probe capacitance.

R^T= Termination resistance: should be equal to Z^OUTof the Pulse

ALVC Link

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

Generator.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t^F≤ 2.5ns; t^R≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

SET-UP, HOLD, AND RELEASE TIMES

V^IH

DATA

INPUT

SWITCH POSITION

V^T

t^SU

t^H

Test

Switch

V^IH

V^T

TIMING

INPUT

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other tests

VLOAD

t^REM

V^IH

V^T

ASYNCHRONOUS

CONTROL

GND

Open

V^IH

V^T

SYNCHRONOUS

CONTROL

t^SU

t^H

NEW16link

ALVC Link

OUTPUT SKEW - ^TSK(x)

V^IH

V^T

INPUT

PULSE WIDTH

t^PLH1

t^PHL1

V^OH

V^T

LOW-HIGH-LOW

PULSE

V^T

OUTPUT 1

t^SK(x)

V^OL

t^SK(x)

t^W

V^OH

V^T

HIGH-LOW-HIGH

PULSE

V^T

OUTPUT 2

V^OL

ALVC Link

t^PLH2

t^SK(x) = t^PLH2- t^PLH1or t^PHL2- t^PHL1

t^PHL2

ALVC Link

NOTES:

1. For t^SK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For t^SK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH16601

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER

EXTENDED COMMERCIAL TEMPERATURE RANGE

ORDERINGINFORMATION

Device Type Package

IDT

ALVC

XXX

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package (SO56-1)

Thin Shrink Small Outline Package (SO56-2)

Thin Very Small Outline Package (SO56-3)

601

18-Bit Universal Bus Transceiver with 3-State Outputs

Double-Density with Resistors, ±24mA

Bus-Hold

-40°C to +85°C

CORPORATE HEADQUARTERS

2975 Stender Way

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74ALVCH16601PV8 [IDT]

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