IDT74ALVCH16836PV8 [IDT]
Bus Driver, ALVC/VCX/A Series, 1-Func, 20-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56;
| 型号： | IDT74ALVCH16836PV8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver, ALVC/VCX/A Series, 1-Func, 20-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56 光电二极管 |
| 文件： | 总7页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 20-BIT
IDT74ALVCH16836
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
This20-bituniversalbusdriverisbuiltusingadvanceddualmetalCMOS
technology. Data flow from A to Y is controlled by the output-enable (OE)
input. Thedeviceoperatesinthetransparentmodewhenthelatch-enable
(LE) input is low. When LE is high, the A data is latched if the clock (CLK)
input is held at a high or low logic level. If LE is high, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLK. When OEis high,
the outputs are in the high-impedance state.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP, TSSOP, and TVSOP packages
The ALVCH16836 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
The ALVCH16836 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high-impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONALBLOCKDIAGRAM
1
OE
56
CLK
29
LE
55
A1
1D
2
Y1
C1
CLK
TO 19 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 1999
1
©1999 Integrated Device Technology, Inc.
DSC-4498/2
IDT74ALVCH16836
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
VTERM
TSTG
IOUT
Terminal Voltage with Respect to GND
–0.5 to +4.6
1
OE
Y1
56
CLK
A1
(3)
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
2
55
54
53
52
51
50
49
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
3
Y2
A2
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
4
GND
GND
A3
5
Y3
Y4
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
6
A4
ICC
ISS
Continuous Current through each
VCC or GND
±100
VCC
7
VCC
A5
8
NOTES:
Y5
Y6
Y7
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
9
48
A6
10
A7
47
46
45
44
43
42
11
12
13
14
15
16
17
18
GND
Y8
GND
A8
2. VCC terminals.
3. All terminals except VCC.
Y9
A9
Y10
Y11
Y12
A10
A11
A12
A13
GND
A14
A15
A16
VCC
A17
CAPACITANCE (TA = +25°C, F = 1.0MHz)
41
40
39
38
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
Y13
GND
Y14
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
COUT
19
20
21
22
23
24
25
26
27
COUT
Y15
37
36
35
NOTE:
Y16
1. As applicable to the device type.
VCC
Y17
34
33
32
31
30
29
FUNCTIONTABLE(1)
Y18
A18
Inputs
Output
GND
GND
OE
H
L
LE
X
CLK
X
Ax
X
L
Yx
Z
Y19
Y20
NC
A19
A20
LE
L
X
L
28
L
L
X
H
L
H
L
H
H
H
H
↑
L
SSOP/ TSSOP/ TVSOP
TOP VIEW
L
↑
H
X
X
H
L
H
Y(2)
Y(3)
L
L
PINDESCRIPTION
NOTES:
Pin Names
Description
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
OE
CLK
LE
3-State Output Enable Inputs (Active LOW)
Register Input Clock
↑ = LOW-to-HIGH Transition
Latch Enable (Active LOW)
Data Inputs(1)
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established,
provided that CLK is HIGH before LE goes LOW.
3. Output level before the indicated steady-state input conditions were established.
A x
Y x
3-State Outputs
N C
No Internal Connection
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74ALVCH16836
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
±5
±5
µA
µA
µA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
±10
±10
–1.2
—
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
µA
µA
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH16836
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
2
1.7
2.2
2.4
2
—
—
—
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
Typical
VCC = 3.3V ± 0.3V
Typical
Symbol
CPD
Parameter
Test Conditions
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
4
IDT74ALVCH16836
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
Min.
150
1
Max.
—
Min.
150
—
Max.
—
Min.
150
1
Max.
—
Unit
ns
PropagationDelay
4.2
4.2
3.6
ns
Ax to Yx
PropagationDelay
1.3
1.4
1.4
1
5
—
—
—
—
4.9
5.2
5.6
4.3
1.3
1.4
1.1
1.3
4.2
4.5
4.6
3.9
ns
ns
ns
ns
LE to Yx
PropagationDelay
5.5
5.5
4.5
CLK to Yx
OutputEnableTime
OE to Yx
OutputDisableTime
OE to Yx
Set-upTime,databeforeCLK↑
Set-up Time, data before LE↑, CLK HIGH
Set-up Time, data before LE↑, CLKLOW
HoldTime,dataafterCLK↑
Hold Time, data after LE↑, CLK HIGH or LOW
Pulse Duration, LE LOW
Pulse Duration, CLK HIGH or LOW
OutputSkew(2)
1.4
1.2
1.4
0.9
1.1
3.3
3.3
—
—
—
—
—
—
—
—
—
1.7
1.6
1.5
0.9
1.1
3.3
3.3
—
—
—
—
—
—
—
—
—
1.5
1.3
1.2
0.9
1.1
3.3
3.3
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ps
tSU
tSU
tH
tH
tW
tW
tSK(O)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2
Skew between any two outputs of the same package and switching in the same direction.
5
IDT74ALVCH16836
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
tPHL
tPHL
tPLH
tPLH
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VT
Vcc / 2
150
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
0V
CONTROL
INPUT
500Ω
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
VT
Generator
VLZ
VOL
CLOSED
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
VIH
VT
DATA
INPUT
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
0V
tSU
tH
VIH
TIMING
INPUT
SWITCHPOSITION
VT
0V
Test
Switch
VLOAD
GND
tREM
VIH
ASYNCHRONOUS
CONTROL
Open Drain
Disable Low
Enable Low
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
All Other Tests
Open
ALVC Link
VIH
Set-up, Hold, and Release Times
VT
INPUT
0V
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
VOL
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74ALVCH16836
3.3VCMOS20-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
ALVC
XXX
XX
XX
X
XXX
Device Type Package
Bus-Hold Family
Temp. Range
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
20-Bit Universal Bus Driver with 3-State Outputs
836
16
Double-Density with Resistors, 24mA
Bus-Hold
H
74
–40°C to +85°C
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7
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