IDT74FCT162H501ATPA8 [IDT]
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56;
| 型号： | IDT74FCT162H501ATPA8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
IDT54/74FCT162H501AT/CT
18-BIT REGISTERED
TRANSCEIVER
DESCRIPTION:
FEATURES:
TheFCT162H501T18-bitregisteredtransceiversarebuiltusingadvanced
dualmetalCMOStechnology.Thesehigh-speed,low-power18-bitregistered
bustransceiverscombineD-typelatchesandD-typeflip-flopstoallowdataflow
in transparent, latched and clocked modes. Data flow in each direction is
controlledbyoutput-enable(OEABandOEBA),latchenable(LEABandLEBA)
andclock(CLKABandCLKBA)inputs.ForA-to-Bdataflow,thedeviceoperates
intransparentmodewhenLEABishigh.WhenLEABislow,theAdataislatched
if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is
storedinthelatch/flip-floponthelow-to-hightransitionofCLKAB.OEABis the
outputenablefortheBport.DataflowfromtheBporttotheAportissimilarbut
requiresusing OEBA,LEBAandCLKBA.Flow-throughorganizationofsignal
pinssimplifieslayout.Allinputsaredesignedwithhysteresisforimprovednoise
margin.
• 0.5 MICRON CMOS Technology
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤ 1µA (max.)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull up resistors
• Available in SSOP and TSSOP packages
The FCT162H501T has "Bus Hold" which retains the input's last state
whenevertheinputgoestohighimpedance. Thisprevents"floating"inputsand
eliminatestheneedforpull-up/downresistors.
FUNCTIONALBLOCKDIAGRAM
1
OEAB
30
CLKBA
28
LEBA
27
OEBA
55
CLKAB
2
LEAB
C
C
54
B1
3
A1
D
D
C
D
C
D
TO 17 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
NOVEMBER 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5434/1
IDT74FCT162H501AT/CT
FASTCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Max
Unit
V
OEAB
LEAB
A1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B1
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to 7
2
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
3
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
°C
mA
GND
A2
4
GND
B2
5
NOTES:
A3
6
B3
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VCC
A4
7
VCC
B4
8
A5
9
B5
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
B6
GND
A7
GND
B7
CAPACITANCE (TA = +25°C, f = 1.0MHz)
A8
B8
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
A9
B9
SO56-1
SO56-2
E56-1
CIN
Input Capacitance
Output Capacitance
VIN = 0V
3.5
6
8
pF
pF
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
GND
COUT
VOUT = 0V
3.5
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTIONTABLE(1,4)
Inputs
Outputs
OEAB
LEAB
CLKAB
Ax
X
L
Bx
Z
L
H
H
H
H
H
H
X
H
H
L
X
X
X
↑
↑
L
L
OEBA
LEBA
H
L
H
L
L
H
X
X
H
SSOP/ TSSOP
TOP VIEW
L
B(2)
B(3)
L
H
NOTES:
PINDESCRIPTION
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and
CLKBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
Pin Names
Description
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
A-to-BOutputEnableInput
B-to-AOutputEnableInput(ActiveLOW)
A-to-BLatchEnableInput
B-to-ALatchEnableInput
A-to-B Clock Input
B-to-A Clock Input
A-to-BDataInputsorB-to-A3-StateOutputs(1)
B-to-ADataInputsorA-to-B3-StateOutputs(1)
Bx
NOTE:
1. These pins have “Bus Hold”. All other pins are standard inputs, outputs or I/Os.
2
IDT74FCT162H501AT/CT
FASTCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE(BUSHOLD)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Input HIGH Level
TestConditions(1)
Guaranteed Logic HIGH Level
GuaranteedLogicLOWLevel
Min.
2
Typ.(2)
—
Max.
—
Unit
V
VIL
InputLOWLevel
Input
—
—
—
—
—
—
—
—
—
–50
50
—
—
—
–80
—
—
—
0.8
V
IIH
StandardInput(5) VCC = Max.
VI = VCC
—
±1
µA
HIGH
Current(4)
StandardI/O(5)
Bus-holdInput
Bus-hold I/O
—
±1
—
±100
±100
±1
—
IIL
Input
StandardInput(5)
StandardI/O(5)
Bus-holdInput
Bus-hold I/O
VI = GND
—
LOW
Current(4)
—
±1
—
±100
±100
—
—
IBHH
IBHL
IOZH
IOZL
VIK
Bus-holdSustain
Current(4)
Bus-holdInput
VCC = Min.
VCC = Max.
VI = 2V
—
µA
µA
VI = 0.8V
VO = 2.7V
VO = 0.5V
—
—
HighImpedanceOutputCurrent
(3-StateOutputpins)(5,6)
ClampDiodeVoltage
—
±1
—
±1
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
–0.7
–140
100
5
–1.2
–250
—
V
IOS
ShortCircuitCurrent
mA
mV
µA
VH
InputHysteresis
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
500
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
OutputLOWCurrent
Output HIGH Current
Output HIGH Voltage
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = Min.
Min.
Typ.(2)
115
Max.
200
–200
—
Unit
mA
mA
V
IODL
60
–60
2.4
IODH
–115
3.3
VOH
IOH = –24mA
IOH = 24mA
VIN = VIH or VIL
VOL
OutputLOWVoltage
VCC = Min.
—
0.3
0.55
V
VIN = VIH or VIL
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Pins with Bus-hold are identified in the pin description.
5. The test limit for this parameter is ±5µA at TA = –55°C.
6. Does not include Bus-hold I/O pins.
3
IDT74FCT162H501AT/CT
FASTCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
OutputsOpen
VIN = VCC
VIN = GND
—
75
120
µA/
MHz
OEAB = OEBA = VCC or GND
OneInputToggling
50% Duty Cycle
IC
TotalPowerSupplyCurrent(6)
VCC = Max.
VIN = VCC
—
0.8
1.7
mA
OutputsOpen
VIN = GND
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
OneBitToggling
fi = 5MHz
VIN = 3.4V
VIN = GND
—
—
1.3
3.8
3.2
50% Duty Cycle
VCC = Max.
VIN = VCC
6.5(5)
OutputsOpen
VIN = GND
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
Eighteen BitsToggling
fi = 2.5MHz
VIN = 3.4V
VIN = GND
—
8.5
20.8(5)
50% Duty Cycle
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT162H501AT/CT
FASTCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
FCT162H501AT
FCT162H501CT
Min.(2)
Max.
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
CLKAB or CLKBA frequency(3)
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
150
5.1
Unit
MHz
ns
—
—
150
4.3
PropagationDelay
1.5
1.5
Ax to Bx or Bx to Ax
PropagationDelay
1.5
1.5
1.5
1.5
3
5.6
5.6
6
1.5
1.5
1.5
1.5
2.4
0
4.4
4.4
4.8
5.2
—
ns
ns
ns
ns
ns
ns
LEBA to Ax, LEAB to Bx
PropagationDelay
CLKBA to Ax, CLKAB to Bx
OutputEnableTime
OEBA to Ax, OEAB to Bx
OutputDisableTime
5.6
—
—
OEBA to Ax, OEAB to Bx
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Set-up Time HIGH or LOW
Ax to LEAB, Bx to LEBA
Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
tH
tSU
tH
0
—
Clock LOW
Clock HIGH
3
—
—
—
2
—
—
—
ns
ns
ns
1.5
1.5
1.5
0.5
tW
tW
LEAB or LEBA Pulse Width HIGH(3)
CLKAB or CLKBA Pulse Width HIGH or LOW(3)
OutputSkew(4)
3
3
—
—
3
3
—
—
ns
ns
ns
tSK(o)
—
0.5
—
0.5
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT162H501AT/CT
FASTCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
V CC
7.0V
SWITCHPOSITION
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
VOUT
VIN
Pulse
Generator
D.U.T.
50pF
CL
All Other Tests
500Ω
RT
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
1.5V
0V
DATA
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
3V
1.5V
0V
PRESET
CLEAR
CLOCK ENABLE
ETC.
Pulse Width
tSU
tH
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT162H501AT/CT
FASTCMOS18-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
IDT
FCT XXX
X
XXXX
X
Temperature
Range
Family Bus Hold Device Type Package
PV
PA
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
18-Bit Registered Transceiver
501AT
501CT
H
Bus-Hold
162
Double-Density 5 Volt Balanced Drive
74
– 40°C to +85°C
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
7
相关型号：
IDT74FCT162H501ATPAG
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TSSOP-56
IDT
IDT74FCT162H501ATPFG
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TVSOP-56
IDT
IDT74FCT162H501ATPV8
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56
IDT
IDT74FCT162H501ATPVG
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, SSOP-56
IDT
©2020 ICPDF网 联系我们和版权申明