IDT74FCT163601APF [IDT]
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS; 3.3V CMOS 18位具有三态输出通用总线收发器
| 型号： | IDT74FCT163601APF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74FCT163601/A
ADVANCE INFORMATION
3.3V CMOS
18-BIT UNIVERSAL BUS
TRANSCEIVER
Integrated Device Technology, Inc.
WITH 3-STATE OUTPUTS
FEATURES:
• 0.5 MICRON CMOS Technology
universal bus transceivers combine D-type latches and D-
type flip-flops to allow data flow in transparent, latched and
clocked modes.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
Data flow in each direction is controlled by output-enable
(OEABandOEBA), latch-enable(LEABandLEBA), andclock
(CLKAB and CLKBA) inputs. The clock can be controlled by
theclock-enable(CLKENAB andCLKENBA)inputs. ForA-to-
Bdataflow,thedeviceoperatesinthetransparentmodewhen
LEAB is high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB is low, the
A-bus data is stored in the latch/flip-flop on the low-to-high
transition of CLKAB. Output enable OEAB is active low.
When OEAB is low, the outputs are active. When OEAB is
high, the outputs are in the high-impedance state.
DataflowforBtoAissimilartothatofAtoBbutusesOEBA,
LEBA, CLKBA and CLKENBA.
TheFCT163601hasseriescurrentlimitingresistors. These
offer low ground bounce, minimal undershoot, and controlled
output fall times-reducing the need for external series termi-
nating resistors.
DESCRIPTION:
The FCT163601/A 18-bit registered transceiver is built
using advanced dual metal CMOS technology. These 18-bit
FUNCTIONAL BLOCK DIAGRAM
1
OEAB
56
CLKENAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
29
CLKENBA
27
OEBA
CE
1D
C1
3
54
A1
B1
CLK
CE
1D
C1
CLK
3251 drw 01
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 1996
1996 Integrated Device Technology, Inc.
5.9
DSC-3251/1
1
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
OEAB
LEAB
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLKENAB
CLKAB
CIN
Input
Capacitance
I/O
VIN = 0V
3.5
6.0
pF
2
A1
3
B1
CI/O
VOUT = 0V
3.5
8.0
pF
Capacitance
GND
4
GND
3251 lnk 04
NOTE:
A
2
3
5
B
B
V
B
B
B
2
1. This parameter is measured at characterization but not tested.
A
6
3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
V
CC
7
CC
4
A4
A5
A6
8
Description
Terminal Voltage with
Respect to GND
Max.
Unit
(2)
VTERM
–0.5 to +4.6
V
9
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
6
(3)
VTERM
Terminal Voltage with
Respect to GND
–0.5 to +7.0
V
V
GND
GND
(4)
A7
A8
A9
B
B
B
B
B
B
7
VTERM
Terminal Voltage with
Respect to GND
–0.5 to
VCC + 0.5
–65 to +150
8
TSTG
IOUT
Storage Temperature
°C
9
SO56-1
SO56-2
SO56-3
DC Output Current
–60 to +60
mA
A10
A11
A12
10
11
12
3251 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGSmaycausepermanentdamagetothedevice. Thisisastressrating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
GND
GND
A13
A14
A15
B13
B14
B15
VCC
B16
B17
3. Input terminals.
4. Output and I/O terminals.
V
CC
FUNCTION TABLE(1,4)
A16
Inputs
Outputs
B
A17
LEAB
CLKAB
A
X
L
CLKENAB
OEAB
GND
GND
X
X
X
H
L
H
L
L
L
L
L
L
L
X
H
H
L
X
X
X
X
↑
Z
L
A18
B18
H
X
L
H
B0(2)
CLKBA
OEBA
LEBA
CLKENBA
L
L
SSOP
L
L
↑
H
X
X
H
TSSOP/TVSOP
TOP VIEW
3251 drw 02
L
L
L
B0(2)
B0(3)
PIN DESCRIPTION
L
L
H
Pin Names
Description
NOTES:
3251 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEBA, CLKBA and CLKENBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
OEAB
OEBA
LEAB
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
CLKBA
Ax
A-to-B Clock Input
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
A to B Clock Enable Input (Active LOW)
B to A Clock Enable Input (Active LOW)
Bx
CLKENAB
CLKENBA
3251 tbl 01
5.9
2
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max. Unit
VIH
Input HIGH Level (Input pins)
Guaranteed Logic HIGH Level
2.0
—
5.5
VCC+0.5
0.8
V
Input HIGH Level (I/O pins)
Input LOW Level
2.0
—
—
VIL
II H
Guaranteed Logic LOW Level
–0.5
V
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
VCC = Max.
VCC = Max.
VI = 5.5V
VI = VCC
—
—
—
—
±1
±1
µA
II L
VI = GND
VI = GND
VO = VCC
VO = GND
—
—
±1
—
—
±1
IOZH
IOZL
VIK
—
—
±1
µA
—
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–60
90
—
–1.2
–110
200
—
V
IODH
IODL
VOH
Output HIGH Current
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
–36
50
mA
mA
V
Output LOW Current
Output HIGH Voltage
VCC = Min.
IOH = –0.1mA
IOH = –3mA
IOH = –8mA
VCC–0.2
2.4
VIN = VIH or VIL
3.0
3.0
—
VCC = 3.0V
2.4(5)
—
VIN = VIH or VIL
VCC = Min.
VOL
Output LOW Voltage
IOL = 0.1mA
IOL = 16mA
IOL = 24mA
IOL = 24mA
—
—
—
—
—
0.2
0.3
0.3
0.2
0.4
V
VIN = VIH or VIL
0.55
0.50
VCC = 3.0V
VIN = VIH or VIL
IOS
VH
Short Circuit Current(4)
Input Hysteresis
VCC = Max., VO = GND(3)
–60
—
–135
150
0.1
–240
—
mA
mV
µA
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.,
VIN = GND or VCC
—
10
3251 lnk 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC –0.6V at rated current.
5.9
3
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
—
2.0
30
µA
VIN = VCC –0.6V(3
ICCD
IC
Dynamic Power Supply Current(4)
Total Power Supply Current(6)
VCC = Max., Outputs Open
OEAB = VCC OEBA = GND
One Input Toggling
VIN = VCC
VIN = GND
—
60
100
µA/
MHz
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz (CLKBA)
50% Duty Cycle
OEAB = VCC
OEBA = GND
LEBA = GND
CLKENBA = GND
One Bit Toggling
fi = 5MHz
VIN = VCC
VIN = GND
—
—
0.6
0.6
1.0
1.0
mA
VIN = VCC –0.6
VIN = GND
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz (CLKBA)
50% Duty Cycle
OEAB = VCC
OEBA = GND
LEBA = GND
CLKENBA = GND
Eighteen Bits Toggling
fi = 2.5MHz
VIN = VCC
VIN = GND
—
—
3.0
3.0
5.0(5)
VIN = VCC –0.6
VIN = GND
5.3(5)
50% Duty Cycle
3251 tbl 06
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.9
4
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
FCT163601A
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT163601
Symbol
Parameter
Condition(1)
Min.(2)
—
Max.
100
6.5
Min.(2)
—
Max.
150
5.5
Unit
MHz
ns
fMAX CLKAB or CLKBA frequency(4) CL = 50pF
tPLH Propagation Delay
RL = 500Ω
1.5
1.5
tPHL Ax to Bx or Bx to Ax
tPLH Propagation Delay
tPHL LEBA to Ax, LEAB to Bx
tPLH Propagation Delay
tPHL CLKBA to Ax, CLKAB to Bx
tPZH Output Enable Time
tPZL OEBA to Ax, OEAB to Bx
tPHZ Output Disable Time
tPLZ OEBA to Ax, OEAB to Bx
1.5
1.5
1.5
1.5
4.0
0
7.2
7.3
7.5
6.5
—
1.5
1.5
1.5
1.5
3.0
0
6.2
6.3
6.5
5.2
—
ns
ns
ns
ns
ns
ns
ns
ns
tSU
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tH
—
—
tSU
Set-up Time
HIGH or LOW
Ax to LEAB,
Bx to LEBA
Clock
LOW
Clock
HIGH
2.5
2.0
—
2.5
2.0
—
—
—
tSU
tH
Set-up Time, CLKEN to CLK
3.0
1.5
—
—
2.5
1.0
—
—
ns
ns
Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
Hold Time, CKLEN after CLK
tH
0
—
—
0
—
—
ns
ns
tW
LEAB or LEBA Pulse Width
3.0
2.5
(4)
HIGH
tW
CLKAB or CLKBA Pulse Width
HIGH or LOW(4)
3.0
—
—
3.0
—
—
ns
tSK(o) Output Skew(3)
0.5
0.5
ns
NOTES:
3251 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
5.9
5
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
6V
←
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
V
CC
Open
GND
6V
500Ω
500Ω
GND
V
OUT
V IN
Pulse
Generator
D.U.T.
Open
3251 tbl 08
DEFINITIONS:
50pF
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
R T
C
L
3251 lnk 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
1.5V
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
SYNCHRONOUS CONTROL
PRESET
3251 lnk 06
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
3251 lnk 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3V
1.5V
3V
VOL
VOH
OUTPUT
NORMALLY
LOW
SWITCH
6V
tPLH
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
3251 lnk 07
0V
3251 lnk 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If VCC is below 3V, input voltage swings should be adjusted not to
exceed VCC.
5.9
6
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XX
FCT
XXXX
X
Temp. Range
Package
Device Type
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
PV
PA
PF
163601
163601A
Non-Inverting 18-Bit Registered Transceiver
–40°C to +85°C
74
5.9
7
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