IDT74FCT16652ATPAB [IDT]
FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS; FAST CMOS 16位总线收发器/寄存器
| 型号： | IDT74FCT16652ATPAB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS |
| 文件： | 总9页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT16652T/AT/CT/ET
IDT54/74FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS
TRANSCEIVER/
REGISTERS
Integrated Device Technology, Inc.
vicesareorganizedastwoindependent8-bitbustransceivers
with 3-state D-type registers. For example, the xOEAB and
xOEBA signals control the transceiver functions.
The xSAB and xSBA control pins are provided to select
either real time or stored data transfer. The circuitry used for
select control will eliminate the typical decoding glitch that
occurs in a multiplexer during the transition between stored
and real time data. A LOW input level selects real-time data
and a HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D-flip-flops by LOW-to-HIGH transitions at the appro-
priate clock pins (xCLKAB or xCLKBA), regardless of the
select or enable control pins. Flow-through organization of
signal pins simplifies layout. All inputs are designed with
hysteresis for improved noise margin.
The FCT16652T/AT/CT/ET are ideally suited for driving
high capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– VCC = 5V ±10%
• Features for FCT16652T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162652T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
The FCT162652T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimalundershoot,andcontrolledoutputfalltimes–reducing
the need for external series terminating resistors. The
FCT162652T/AT/CT/ET are plug-in replacements for the
FCT16652T/AT/CT/ETandABT16652foron-boardbusinter-
face applications.
DESCRIPTION:
The FCT16652T/AT/CT/ET and FCT162652T/AT/CT/ET
16-bit registered transceivers are built using advanced dual
metal CMOS technology. These high-speed, low-power de-
FUNCTIONAL BLOCK DIAGRAM
2OEAB
1
OEAB
OEBA
CLKBA
SBA
CLKAB
2OEBA
2CLKBA
1
1
1
1
2SBA
2CLKAB
2SAB
1
SAB
B REG
B REG
D
D
C
C
2B1
1B1
A REG
A REG
2A1
1A1
D
D
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2549 drw 02
2549 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGE
AUGUST 1996
1996 Integrated Device Technology, Inc.
DSC-2549/8
1
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1OEAB
1CLKAB
1SAB
GND
1A1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEAB
CLKAB
SAB
GND
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1CLKBA
1SBA
GND
1B1
1
1
OEBA
1
2
CLKBA
2
1
3
1
SBA
3
4
GND
4
1
A
A
1
2
5
1
1
B
B
1
2
5
1
6
1A2
6
1B2
VCC
7
V
CC
VCC
7
VCC
1
A
A
A
3
4
5
8
1
B
3
4
5
1A3
8
1B3
1
9
1
1
B
1A4
9
1B4
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
B
1A5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1B5
GND
GND
GND
1A6
GND
1B6
1A
1A
1A
2A
2A
2A
6
7
8
1
2
3
1
1
1
2
2
2
B
B
B
B
B
B
6
7
8
1
2
3
1A7
1B7
SO56-1
SO56-2
SO56-3
1A8
1B8
E56-1
2A1
2B1
2A2
2B2
2A3
2B3
GND
GND
GND
2A4
GND
2B4
2
A
A
A
4
5
6
2
2
2
B
B
B
4
5
2
2A5
2B5
2
6
2A6
2B6
VCC
V
CC
VCC
VCC
2
A
A
7
8
2
B
7
8
2A7
2B7
2
2B
2A8
2B8
GND
GND
GND
2SAB
2CLKAB
2OEAB
GND
2SBA
2CLKBA
2OEBA
2
SAB
2
2
SBA
2
CLKAB
CLKBA
2OEAB
2
OEBA
2549 drw 03
2549 drw 04
SSOP/
TSSOP/TVSOP
TOP VIEW
CERPACK
TOP VIEW
2
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Pin Names
Description
Data Register A Inputs
Data Register B Outputs
Data Register B Inputs
Data Register A Outputs
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
xAx
CIN
Input
Capacitance
I/O
VIN = 0V
4.5
5.5
6.0
pF
xBx
CI/O
VOUT = 0V
8.0
pF
Capacitance
2549 lnk 02
NOTE:
1. This parameter is measured at characterization but not tested.
xCLKAB, xCLKBA Clock Pulse Inputs
xSAB, xSBA
Output Data Source Select Inputs
xOEAB, xOEBA Output Enable Inputs
2549 tbl 01
(2)
FUNCTION TABLE
Inputs
Data I/O(1)
Operation or Function
xOEAB
x
xCLKAB xCLKBA
xSAB
xSBA
xAx
xBx
OEBA
L
L
H
H
H or L
↑
H or L
↑
X
X
X
X
Input
Input
Isolation
Store A and B Data
Unspecified(1) Store A, Hold B
X
H
H
H
↑
↑
H or L
↑
X
X(2)
X
X
Input
Input
Output
Store A in Both Registers
L
L
X
L
H or L
↑
↑
↑
X
X
X
X(2)
Unspecified(1)
Output
Input
Input
Hold A, Store B
Store B in both Registers
L
L
L
L
X
X
X
H or L
X
X
X
L
H
H
L
Output
Input
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored B Data to A Bus
H
X
X
H
H
H
H
H
H
L
X
Input
Output
Output
H or L
H or L
X
H or L
Output
2549 tbl 03
NOTES:
1. The data output functions may be enabled or disabled by various signals at the xOEAB or xOEBA inputs.
Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH
transition on the clocks inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
3. H = HIGH Voltage Level
(1)
L = LOW Voltage Level
X = Don't care
↑ = LOW-to-HIGH Transition
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Max.
Unit
(2) Terminal Voltage with Respect to
VTERM
–0.5 to +7.0
V
GND
(3) Terminal Voltage with Respect to
GND
VTERM
–0.5 to
VCC +0.5
V
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150 °C
–60 to +120 mA
2549 lnk 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
3
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
A
BUS
B
BUS
A
BUS
B
2549 drw 05
2549 drw 06
xCLKAB
X
x
OEAB
x
OEBA
x
CLKAB
xOEAB xOEBA
x
CLKBA
x
SAB
x
SBA
xCLKBA
X
xSAB
X
xSBA
L
H
H
X
X
L
X
L
L
REAL-TIME TRANSFER
BUS B TO A
REAL-TIME TRANSFER
BUS A TO B
BUS
A
BUS
A
BUS
B
BUS
B
2549 drw 07
2549 drw 08
x
OEAB
x
OEBA
x
CLKAB
H or L
x
CLKBA
x
SAB
x
SBA
xOEAB xOEBA xCLKAB
xCLKBA
xSAB
xSBA
H or L
H
L
H
H
X
L
L
H
X
H
X
↑
X
X
↑
X
X
X
X
↑
↑
X
STORAGE FROM
A AND/OR B
TRANSFER STORED
DATA TO A AND/OR B
4
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ±10%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
–80
—
—
—
—
—
0.8
±1
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current (Input pins)(5)
Input HIGH Current (I/O pins)(5)
Input LOW Current (Input pins)(5)
Input LOW Current (I/O pins)(5)
High Impedance Output Current
(3-State Output pins)(5)
VCC = Max.
VI = VCC
—
µA
—
±1
II L
VI = GND
—
±1
—
±1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
±1
µA
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
—
–0.7
–140
100
5
–1.2
–225
—
V
IOS
VH
Short Circuit Current
mA
mV
µA
Input Hysteresis
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
500
2549 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16652T
Symbol
Parameter
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min. Typ.(2) Max.
Unit
IO
Output Drive Current
–50
2.5
2.4
—
3.5
3.5
–180
—
mA
VOH
Output HIGH Voltage
VCC = Min.
IOH = –3mA
V
V
VIN = VIH or VIL
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOH = –24mA MIL.
IOH = –32mA COM'L.(4)
IOL = 48mA MIL.
—
2.0
—
3.0
0.2
—
—
0.55
±1
V
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
IOL = 64mA COM'L.
IOFF
Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V
—
µA
2549 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162652T
Symbol
Parameter
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
Min. Typ.(2) Max.
Unit
IODL
Output LOW Current
60
–60
2.4
115
200
mA
VOUT = 1.5V(3)
IODH
VOH
Output HIGH Current
Output HIGH Voltage
VCC = 5V, VIN = VIH or VIL,
–115 –200
mA
V
VCC = Min.
IOH = –16mA MIL.
IOH = –24mA COM'L.
IOL = 16mA MIL.
3.3
0.3
—
VIN = VIH or VIL
VCC = Min.
VOL
Output LOW Voltage
—
0.55
V
VIN = VIH or VIL
IOL = 24mA COM'L.
2549 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
V
V
CC = Max.
IN = 3.4V(3)
—
0.5
1.5
mA
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
VIN = VCC
—
75
120
µA/
Outputs Open
VIN = GND
MHz
xOEAB = xOEBA=GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
V
CC = Max.
Outputs Open
CP = 10MHz (xCLKBA)
V
IN = VCC
—
—
0.8
1.3
1.7
3.2
mA
VIN = GND
f
50% Duty Cycle
xOEAB = xOEBA=GND
One Bit Toggling
fi = 5MHz
V
V
IN = 3.4V
IN = GND
50% Duty Cycle
V
CC = Max.
Outputs Open
CP = 10MHz (xCLKBA)
V
IN = VCC
—
—
3.8
8.3
6.5(5)
VIN = GND
f
50% Duty Cycle
xOEAB = xOEBA=GND
Sixteen Bits Toggling
fi = 2.5MHz
V
V
IN = 3.4V
IN = GND
20.0(5)
50% Duty Cycle
2549 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
6
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16652T/162652T
FCT16652AT/162652AT
Com'l. Mil.
Com'l.
Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH Propagation Delay
tPHL Bus to Bus
CL = 50pF
RL = 500Ω
2.0
2.0
2.0
2.0
2.0
4.0
2.0
6.0
—
9.0
2.0
11.0
2.0
2.0
2.0
2.0
2.0
2.0
1.5
5.0
—
6.3
2.0
7.7
ns
tPZH Output Enable Time
tPZL xOEAB or xOEBA to Bus
tPHZ Output Disable Time
tPLZ xOEAB or xOEBA to Bus
tPLH Propagation Delay
tPHL Clock to Bus
14.0
9.0
9.0
11.0
—
2.0
2.0
2.0
2.0
4.5
2.0
6.0
—
15.0
11.0
10.0
12.0
—
9.8
6.3
6.3
7.7
—
2.0
2.0
2.0
2.0
2.0
1.5
5.0
—
10.5
7.7
7.0
8.4
—
ns
ns
ns
ns
ns
ns
ns
tPLH Propagation Delay xSBA or
tPHL xSAB to Bus
tSU
Set-up Time HIGH or LOW
Bus to Clock
tH
Hold Time HIGH or LOW
Bus to Clock
—
—
—
—
tW
Clock Pulse Width
HIGH or LOW
—
—
—
—
tSK(o) Output Skew(3)
0.5
0.5
0.5
0.5
ns
2549 tbl 09
FCT16652CT/162652CT
Com'l. Mil.
FCT16652ET/162652ET
Com'l. Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH Propagation Delay
tPHL Bus to Bus
CL = 50pF
RL = 500Ω
1.5
5.4
1.5
6.0
1.5
3.8
—
—
ns
tPZH Output Enable Time
tPZL xOEAB or xOEBA to Bus
tPHZ Output Disable Time
tPLZ xOEAB or xOEBA to Bus
tPLH Propagation Delay
tPHL Clock to Bus
1.5
1.5
1.5
1.5
2.0
1.5
5.0
—
7.8
6.3
5.7
6.2
—
1.5
1.5
1.5
1.5
2.0
1.5
5.0
—
8.9
7.7
6.3
7.0
—
1.5
1.5
1.5
1.5
2.0
0.0
3.0(4)
—
4.8
4.0
3.8
4.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tPLH Propagation Delay xSBA or
tPHL xSAB to Bus
tSU
Set-up Time HIGH or LOW
Bus to Clock
tH
Hold Time HIGH or LOW
Bus to Clock
—
—
—
tW
Clock Pulse Width
HIGH or LOW
—
—
—
tSK(o) Output Skew(3)
0.5
0.5
0.5
ns
2549 tbl 10
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
7
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
VCC
7.0V
Enable Low
Open
All Other Tests
500
Ω
Ω
2549 lnk 07
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
VOUT
VIN
Pulse
Generator
D.U.T.
Generator.
50pF
500
T
R
C
L
2549 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
t
REM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
1.5V
ETC.
SYNCHRONOUS CONTROL
PRESET
3V
2549 drw 07
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
2549 drw 06
ENABLE AND DISABLE TIMES
PROPAGATION DELAY
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
PHL
PHL
t
PZL
tPLZ
V
OH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
V
OL
tPLH
t
0.3V
0.3V
VOL
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2549 drw 08
0V
2549 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
8
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
X
X
IDT
XX
FCT XXXX
Device Type Package Process
Temperature
Range
Commercial
MIL-STD-883, Class B
Blank
B
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
PV
PA
PF
E
16652T
Non-Inverting 16-Bit Bus Transceiver/Register
16652AT
16652CT
16652ET
162652T
162652AT
162652CT
162652ET
–55°C to +125°C
–40°C to +85°C
54
74
2549 drw 14
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090
Telephone: (408) 727-6116
FAX 408-492-8674
9
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