IDT74FCT16827CTPA8 [IDT]
Bus Driver, FCT Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, TSSOP-56;
| 型号： | IDT74FCT16827CTPA8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver, FCT Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, TSSOP-56 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总7页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
IDT74FCT16827AT/CT
20-BIT BUFFER
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The FCT16827T 20-bit buffer is built using advanced dual metal CMOS
technology. These20-bitbusdriversprovidehigh-performancebusinterface
buffering for wide data/address paths or buses carrying parity. Two pair of
NAND-ed output enable controls offer maximum control flexibility and are
organizedtooperatethedeviceastwo10-bitbuffersorone20-bitbuffer.Flow-
throughorganizationofsignalpinssimplifieslayout. Allinputsaredesignedwith
hysteresisforimprovednoisemargin.
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤1µA (max.)
• VCC = 5V ±10%
• High drive outputs (–32mA IOH, 64mA IOL)
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
TheFCT16827Tisideallysuitedfordrivinghighcapacitanceloadsandlow
impedancebackplanes.Theoutputbuffersaredesignedwithpoweroffdisable
capabilitytoallow"liveinsertion"ofboardswhenusedasbackplanedrivers.
• Available in SSOP and TSSOP packages
FUNCTIONALBLOCKDIAGRAM
1
28
1OE1
56
2OE1
29
1OE2
2OE2
2
42
55
15
1A1
1Y1
2A1
2Y1
TO NINE OTHER CHANNELS
TO NINE OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5439/1
IDT74FCT16827AT/CT
FASTCMOS20-BITBUFFER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +7
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE2
1A1
1OE1
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
2
1Y1
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
°C
mA
3
1Y2
1A2
GND
4
GND
NOTES:
5
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1Y3
1A3
6
1Y4
1A4
VCC
7
VCC
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
8
1Y5
1Y6
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1Y7
GND
CAPACITANCE (TA = +25°C, f = 1.0MHz)
1Y8
1Y9
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
3.5
6
8
pF
pF
1Y10
COUT
VOUT = 0V
3.5
2Y1
2Y2
NOTE:
1. This parameter is measured at characterization but not tested.
2Y3
2A3
GND
GND
2A4
2A5
2A6
VCC
2Y4
2Y5
PINDESCRIPTION
Pin Names
xOEx
xAx
Description
OutputEnableInputs(ActiveLOW)
DataInputs
2Y6
VCC
2Y7
2Y8
2A7
2A8
xYx
3-StateOutputs
GND
2Y9
GND
2A9
2Y10
2OE1
2A10
2OE2
FUNCTIONTABLE(1)
Inputs
Outputs
SSOP/ TSSOP
TOP VIEW
xOE1
xOE2
xAx
L
xYx
L
L
L
L
L
H
H
H
X
X
H
X
Z
X
Z
NOTE:
1. H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High-Impedance
2
IDT74FCT16827AT/CT
FASTCMOS20-BITBUFFER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
Unit
V
Input HIGH Level
VIL
InputLOWLevel
GuaranteedLogicLOWLevel
VCC = Max.
—
—
—
—
—
—
—
—
–80
—
—
—
0.8
±1
V
IIH
InputHIGHCurrent(Inputpins)(5)
Input HIGH Current (I/O pins)(5)
InputLOWCurrent(Inputpins)(5)
InputLOWCurrent(I/Opins)(5)
HighImpedanceOutputCurrent
(3-StateOutputpins)(5)
VI = VCC
—
µA
—
±1
IIL
VI = GND
—
±1
—
±1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
±1
µA
—
±1
ClampDiodeVoltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
–0.7
–140
100
5
–1.2
–250
—
V
IOS
ShortCircuitCurrent
mA
mV
µA
VH
InputHysteresis
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max
500
VIN = GND or VCC
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
–50
2.5
2.4
2
Typ.(2) Max.
Unit
IO
OutputDriveCurrent
VCC = Max., VO = 2.5V(3)
—
3.5
3.5
3
–180
—
mA
VOH
Output HIGH Voltage
VCC = Min.
IOH = –3mA
IOH = –15mA
IOH = –32mA(4)
IOL = 64mA
VIN = VIH or VIL
—
V
V
—
VOL
OutputLOWVoltage
VCC = Min.
—
0.2
0.55
VIN = VIH or VIL
IOFF
Input/OutputPowerOffLeakage(5)
VCC = 0V, VIN or VO ≤ 4.5V
—
—
±1
µA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is ±5µA at TA = –55°C.
3
IDT74FCT16827AT/CT
FASTCMOS20-BITBUFFER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
TTL Inputs HIGH
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
VIN = VCC
—
60
100
µA/
OutputsOpen
VIN = GND
MHz
xOE1 = xOE2 = GND
OneInputToggling
50% Duty Cycle
IC
TotalPowerSupplyCurrent(6)
VCC = Max.
OutputsOpen
fi = 10MHz
VIN = VCC
VIN = GND
—
—
—
—
0.6
0.9
3
1.5
2.3
mA
50% Duty Cycle
xOE1 = xOE2 = GND
OneBitToggling
VIN = 3.4V
VIN = GND
VCC = Max.
OutputsOpen
fi = 2.5MHz
50% Duty Cycle
xOE1 = xOE2 = GND
TwentyBitsToggling
VIN = VCC
VIN = GND
5.5(5)
20.5(5)
VIN = 3.4V
VIN = GND
8
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT16827AT/CT
FASTCMOS20-BITBUFFER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
74FCT16827AT
74FCT16827CT
Symbol
tPLH
Parameter
PropagationDelay
xAx to xYx
Condition(1)
CL = 50pF
Min.(2)
Max.
Min.(2)
Max.
Unit
1.5
8
1.5
3.7
ns
tPHL
RL = 500Ω
CL = 300pF(3)
RL = 500Ω
CL = 50pF
1.5
1.5
15
12
1.5
1.5
7
tPZH
tPZL
OutputEnableTime
4.8
ns
ns
ns
xOEx to xYx
RL = 500Ω
CL = 300pF(3)
RL = 500Ω
CL = 5pF(3)
RL = 500Ω
CL = 50pF
RL = 500Ω
1.5
1.5
1.5
—
23
9
1.5
1.5
1.5
—
9
4
tPZH
tPZL
OutputDisableTime
xOEx to xYx
10
0.5
4
tSK(o)
OutputSkew(4)
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT16827AT/CT
FASTCMOS20-BITBUFFER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
V CC
7.0V
SWITCHPOSITION
Test
Switch
Closed
Open
500Ω
V OUT
Open Drain
Disable Low
Enable Low
VIN
Pulse
Generator
D.U.T.
50pF
CL
All Other Tests
500Ω
RT
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
1.5V
0V
DATA
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
CLOCK ENABLE
ETC.
Pulse Width
tSU
tH
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT16827AT/CT
FASTCMOS20-BITBUFFER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
FCT
XXXX
XXX
XX
Temp. Range
Family
Package
Device Type
PV
PA
Shrink Small Outline Package
Thin Shrink Small Outline Package
20-Bit Buffer
827AT
827CT
16
74
Double-Density, 5 Volt, High Drive
– 40°C to +85°C
DATASHEETDOCUMENTHISTORY
5/21/2002 Removed TVSOP package
6/21/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
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for Tech Support:
logichelp@idt.com
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www.idt.com
7
相关型号：
IDT74FCT16827ETPAT/R
Bus Driver, FCT Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 6.10 MM, 0.50 MM PITCH, TSSOP-56
IDT
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