IDT74FCT2543CTEB [IDT]
FAST CMOS OCTAL LATCHED TRANSCEIVER; 快速CMOS八路锁存收发器
| 型号： | IDT74FCT2543CTEB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS OCTAL LATCHED TRANSCEIVER |
| 文件： | 总7页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT543T/AT/CT/DT
IDT54/74FCT2543T/AT/CT
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
Integrated Device Technology, Inc.
FEATURES:
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
DESCRIPTION:
The FCT543T/FCT2543T is a non-inverting octal trans-
ceiver built using an advanced dual metal CMOS technology.
This device contains two sets of eight D-type latches with
separate input and output controls for each set. For data flow
fromAtoB, forexample, theA-to-BEnable(CEAB)inputmust
be LOW in order to enter data from A0–A7 or to take data from
B0–B7, as indicated in the Function Table. With CEAB LOW,
a LOW signal on the A-to-B Latch Enable (LEAB) input makes
the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB and OEAB both LOW, the 3-state B output buffers
are active and reflect the data present at the output of the A
latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT543T:
– Std., A, C and D speed grades
– High drive outputs (-15mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
• Features for FCT2543T:
– Std., A, and C speed grades
– Resistor outputs (-15mA IOH, 12mA IOL Com.)
(-12mA IOH, 12mA IOL Mil.)
The FCT2543T has balanced output drive with current
limiting resistors. This offers low ground bounce, minimal
undershoot and controlled output fall times-reducing the need
for external series terminating resistors. FCT2xxxT parts are
plug-in replacements for FCTxxxT parts.
– Reduced system switching noise
FUNCTIONAL BLOCK DIAGRAM
DETAIL A
B0
D
Q
LE
Q
D
A0
LE
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
DETAIL A x 7
B6
B7
OEBA
OEAB
CEBA
LEBA
CEAB
LEAB
2613 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JANUARY 1995
1995 Integrated Device Technology, Inc.
6.17
DSC-4203/5
1
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
1
24
Vcc
CEBA
B0
B1
B2
B3
B4
B5
B6
LEBA
OEBA
A0
4
3
2
28 27 26
23
22
2
5
25
24
23
22
21
20
19
B
B
B
1
2
3
A
A
1
2
3
1
6
P24-1 21
4
A1
A2
A3
A4
7
A
3
D24-1
SO24-2
SO24-7
SO24-8
&
5
20
19
18
17
16
15
14
13
NC
NC
8
6
L28-1
9
B
B
B
4
5
6
A
A
A
4
5
6
7
10
11
8
A5
E24-1
9
6
A
12 13 14 15 16 17 18
10
11
12
A7
B7
LEAB
OEAB
CEAB
GND
2613 drw 02
2613 drw 03
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
FUNCTION TABLE(1, 2)
For A-to-B (Symmetric with B-to-A)
Latch
PIN DESCRIPTION
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
Description
Output
Buffers
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
Inputs
Status
A-to-B
B0–B7
CEAB
LEAB
—
H
OEAB
H
—
—
H
L
Storing
High Z
High Z
B-to-A Enable Input (Active LOW)
—
Storing
—
—
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
—
—
L
LEBA
L
L
Transparent
Storing
Current A Inputs
Previous* A Inputs
2613 tbl 02
A0–A7
B0–B7
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
H
L
NOTES:
1. * Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
2613 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
L = LOW Voltage Level
— = Don’t Care or Irrelevant
Symbol
Rating
Commercial
Military
Unit
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA.
(2)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
VCC +0.5
–0.5 to
VCC +0.5
V
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
TA
Operating
0 to +70
–55 to +125 °C
CIN
Input
Capacitance
Output
VIN = 0V
6
8
10
pF
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
COUT
VOUT = 0V
12
pF
Capacitance
2613 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120 –60 to +120 mA
2613 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.17
2
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
—
—
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
0.8
V
I
I
I
I
I
I H
I L
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current
(3-State Output pins)(4)
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
V
CC = Max.
CC = Max.
CC = Max., V
V
V
V
V
I
I
= 2.7V
= 0.5V
—
±1
±1
±1
±1
±1
µA
µA
µA
—
OZH
OZL
I
V
O
O
= 2.7V
= 0.5V
—
—
V
V
I
= VCC (Max.)
—
V
IK
H
CC = Min., IIN = –18mA
—
–0.7
200
0.01
–1.2
—
V
V
mV
I
CC
Quiescent Power Supply Current
V
CC = Max., VIN = GND or VCC
1
mA
2613 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR 543T/AT/CT/DT
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VOH
Output HIGH Voltage
VCC = Min.
VIN = VIH or VIL
IOH = –6mA MIL.
2.4
2.0
—
3.3
3.0
0.3
—
V
IOH = –8mA COM'L.
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOL = 48mA MIL.
—
V
V
VOL
Output LOW Voltage
Short Circuit Current
VCC = Min.
VIN = VIH or VIL
VCC = Max., VO = GND(3)
0.55
IOL = 64mA COM'L.
IOS
–60
—
–120 –225
±1
mA
IOFF
Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V
—
µA
2613 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR 2543T/AT/CT/DT
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
I
I
ODL
Output LOW Current
V
CC = 5V, VIN = VIH or VIL,
CC = 5V, VIN = VIH or VIL,
V
V
OUT= 1.5V(3)
16
–16
2.4
48
–48
3.3
—
—
—
mA
ODH
Output HIGH Current
Output HIGH Voltage
V
OUT= 1.5V(3)
mA
V
V
OH
OL
V
V
V
V
CC = Min.
IN = VIH or VIL
CC = Min.
I
I
I
OH = –12mA MIL.
OH = –15mA COM'L.
OL = 12mA
V
Output LOW Voltage
—
0.3
0.50
V
IN = VIH or VIL
2613 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
6.17
3
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
2.0
mA
ICCD
Dynamic Power Supply Current(4) VCC = Max., Outputs Open
VIN = VCC
VIN = GND
FCTxxxT
—
—
0.15 0.25
0.06 0.12
mA/
MHz
CEAB and OEAB = GND
CEBA = VCC
FCT2xxxT
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open
fCP = 10MHz (LEAB)
50% Duty Cycle
CEAB and OEAB = GND
CEBA = VCC
VIN = VCC
VIN = GND
FCTxxxT
—
—
—
—
1.5
0.6
2.0
1.1
3.5
2.2
5.5
4.2
mA
FCT2xxxT
VIN = 3.4V FCTxxxT
VIN = GND
One Bit Toggling
at fi = 5MHz
FCT2xxxT
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz (LEAB)
50% Duty Cycle
CEAB and OEAB = GND
CEBA = VCC
VIN = VCC
VIN = GND
FCTxxxT
—
—
—
—
3.8 7.3(5)
1.5 4.0(5)
6.0 16.3(5)
3.8 13.0(5)
FCT2xxxT
VIN = 3.4V FCTxxxT
VIN = GND
Eight Bits Toggling
at fi = 2.5MHz
FCT2xxxT
50% Duty Cycle
2613 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.17
4
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT543T/
FCT543AT/
FCT2543AT
FCT2543T
Com'l.
Mil.
Com'l.
Mil.
. Max. Unit
Symbol
Parameter
Condition(1)
= 50pF
= 500
Min (2)
.
Max. Min (2)
.
Max. Min (2)
.
Max. Min (2)
tPLH
PHL
Propagation Delay
Transparant Mode
C
L
1.5
8.5
1.5
10.0
1.5
6.5
1.5
7.5
ns
t
R
L
Ω
An to Bn or Bn to An
t
t
t
t
PLH
PHL
PZH
PZL
Propagation Delay
LEBA to An, LEAB to Bn
Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Set-up Time, HIGH or LOW
An or Bn to LEBA or LEAB
Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB
LEBA or LEAB Pulse Width
LOW
1.5
1.5
12.5
12.0
1.5
1.5
14.0
14.0
1.5
1.5
8.0
9.0
1.5
1.5
9.0
ns
ns
10.0
t
t
PHZ
PLZ
1.5
9.0
1.5
13.0
1.5
7.5
1.5
8.5
ns
t
t
t
SU
3.0
2.0
5.0
—
—
—
3.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
ns
ns
H
W
ns
2513 tbl 09
FCT543CT/
FCT2543CT
FCT543DT
Com'l.
Max. Min (2) Max. Min (2)
Com'l.
Mil.
Mil.
. Max. Unit
Symbol
Parameter
Condition(1)
= 50pF
= 500
Min (2) Max. Min (2)
.
.
.
tPLH
PHL
Propagation Delay
Transparant Mode
C
L
1.5
5.3
1.5
6.1
1.5
4.4
—
—
ns
t
R
L
Ω
An to Bn or Bn to An
t
t
t
t
PLH
PHL
PZH
PZL
Propagation Delay
LEBA to An, LEAB to Bn
Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Set-up Time, HIGH or LOW
An or Bn to LEBA or LEAB
Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB
LEBA or LEAB Pulse Width
LOW
1.5
1.5
7.0
8.0
1.5
1.5
8.0
9.0
1.5
1.5
5.0
5.4
—
—
—
—
ns
ns
t
t
PHZ
PLZ
1.5
6.5
1.5
7.5
1.5
4.3
—
—
ns
t
t
t
SU
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
1.5
1.5
—
—
—
—
—
—
—
—
—
ns
ns
H
W
3.0(3)
ns
NOTES:
1. See test circuits and waveforms.
2513 tbl 10
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
6.17
5
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500Ω
500Ω
Enable Low
VOUT
VIN
Open
All Other Tests
Pulse
Generator
D.U.T.
2513 lnk 11
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
50pF
C L
T
R
Generator.
2513 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
1.5V
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
ETC.
SYNCHRONOUS CONTROL
PRESET
2513 drw 07
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
2513 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2513 drw 08
0V
2513 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.17
6
IDT54/74FCT543T/AT/CT/DT - 2543T/AT/CT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
X
FCT
X
XXXX
X
X
Temperature
Range
Family Device Package
Type
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
SO
L
Small Outline IC
Leadless Chip Carrier
CERPACK
Shrink Small Outline Package
Quarter-size Small Outline Package
E
PY
Q
543T
Octal Latched Transceiver
543AT
543CT
543DT
Blank
2
High Drive
Balanced Drive
54
74
-55°C to +125°C
0° to +70°C
2613 drw 10
6.17
7
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