IDT74FCT273SO [IDT]
FAST CMOS OCTAL FLIP-FLOP WITH MASTER RESET; 快速CMOS八路触发器具有硕士RESET
| 型号： | IDT74FCT273SO |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS OCTAL FLIP-FLOP WITH MASTER RESET |
| 文件： | 总7页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
FAST CMOS
OCTAL FLIP-FLOP
WITH MASTER RESET
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT273 equivalent to FAST speed;
• IDT54/74FCT273A 45% faster than FAST
• IDT54/74FCT273C 55% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST
(5µA max.)
• Octal D flip-flop with Master Reset
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
The IDT54/74FCT273/A/C are octal D flip-flops built using
an advanced dual metal CMOS technology. The IDT54/
74FCT273/A/C have eight edge-triggered D-type flip-flops
with individual D inputs and O outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM
0
1
2
3
4
5
6
7
D
D
D
D
D
D
D
D
CP
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
RD
CP
RD
CP
RD
CP
RD
CP
RD
CP
RD
CP
RD
CP
RD
MR
O0
O1
O2
O3
O4
O5
O6
O7
2558 drw 01
PIN CONFIGURATIONS
INDEX
1
20
19
18
17
16
15
MR
O0
D0
D1
O1
O2
D2
D3
O3
Vcc
O7
D7
D6
O6
O5
D5
D4
O4
CP
2
3
3
2
20 19
18
D7
4
5
6
7
8
P20-1
D20-1
SO20-2
&
D1
O1
O2
D2
D3
1
4
D6
O6
O5
D5
17
16
15
14
5
L20-2
6
7
E20-1 14
13
12
11
8
10 11 12 13
9
9
10
GND
2558 drw 02
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1992
1992 Integrated Device Technology, Inc.
7.10
DSC-4609/2
1
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
FUNCTION TABLE
Pin Names
Description
Inputs
Outputs
DN
Data Input
Operating Mode
Reset (Clear)
Load “1”
CP
X
DN
X
h
ON
L
MR
L
MR
CP
ON
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
H
↑
H
Load “0”
H
↑
l
L
2558 tbl 05
NOTES:
H = HIGH voltage level steady-state
2558 tbl 06
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t care
↑ = LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
(2)
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to +7.0 –0.5 to +7.0
V
CIN
Input Capacitance
VIN = 0V
6
8
10
12
pF
pF
COUT
Output Capacitance VOUT = 0V
NOTE:
2558 tbl 02
(3)
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to VCC –0.5 to VCC
V
1. This parameter is guaranteed by characterization data and not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
TBIAS
TSTG
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Storage
Temperature
PT
Power Dissipation
DC Output Current
0.5
0.5
W
IOUT
120
120
mA
NOTES:
2558 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
7.10
2
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Test Conditions(1)
Min.
2.0
—
Typ.(2)
Max.
—
Unit
V
Guaranteed Logic HIGH Level
—
VIL
Guaranteed Logic LOW Level
VCC = Max.
—
0.8
V
IIH
VI = VCC
VI = 2.7V
VI = 0.5V
VI = GND
—
—
5
µA
—
—
5(4)
–5(4)
–5
IIL
Input LOW Current
—
—
—
—
VIK
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Vcc = Min., IN = –18mA
Vcc = Max.(3), VO = GND
—
–0.7
–1.2
V
mA
V
IOS
–60
VHC
VHC
2.4
2.4
—
–120
VCC
VCC
4.3
—
—
VOH
Vcc = 3V, VIN = VLC or VHC, IOH = –32µA
Vcc = Min.
IOH = –300µA
—
VIN = VIH or VIL
IOH = –12mA MIL.
—
IOH = –15mA COM’L.
4.3
—
VOL
Output LOW Voltage
Vcc = 3V, VIN = VLC or VHC, IOL = 300µA
GND
GND
0.3
VLC
V
(4)
Vcc = Min.
IOL = 300µA
—
VLC
VIN = VIH or VIL
IOL = 32mA MIL.
IOL = 48mA COM’L.
—
0.5
0.5
—
0.3
NOTES:
2558 tbl 03
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.10
3
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Parameter
Test Conditions(1)
Vcc = Max.
Min.
Typ.(2)
Max.
Unit
ICC
Quiescent Power Supply Current
—
0.2
1.5
mA
VIN ≥ VHC; VIN ≤ VLC
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
Vcc = Max.
—
—
0.5
2.0
mA
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current(4)
Vcc = Max.
Outputs Open
MR = VCC
VIN ≥ VHC
VIN ≤ VLC
0.15
0.25
mA/MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
Vcc = Max.
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
1.7
2.2
4.0
6.0
mA
Outputs Open
fCP = 10MHz
50% Duty Cycle
MR = VCC
One Bit Toggling
at fi = 5MHz
VIN = 3.4V
VIN = GND
50% Duty Cycle
Vcc = Max.
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
4.0
6.2
7.8(5)
Outputs Open
fCP = 10MHz
50% Duty Cycle
MR = VCC
Eight Bits Toggling
fi = 2.5MHz
VIN = 3.4V
VIN = GND
16.8(5)
50% Duty Cycle
NOTES:
2558 tbl 04
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.10
4
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273
IDT54/74FCT273A
IDT54/74FCT273C
Com’l.
Mil.
Com’l.
Mil.
Com’l.
Mil.
(2)
(2)
(2)
(2)
(2)
(2)
Symbol
Parameter
Condition(1) Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max. Unit
tPLH
tPHL
Propagation Delay
Clock to Output
CL = 50 pF
RL = 500Ω
2.0 13.0
2.0 15.0
2.0
2.0
2.0
1.5
6.0
6.0
2.0
7.2
7.2
—
2.0
8.3
8.3
—
2.0
5.8
6.1
—
2.0 6.5
ns
ns
ns
ns
ns
ns
ns
tPHL
tSU
tH
Propagation Delay
MR to Output
2.0 13.0
2.0 15.0
2.0
2.0
1.5
6.0
6.0
2.5
2.0
2.0
1.5
6.0
6.0
2.0
2.0 6.8
Set-up Time HIGH
or LOW Data to CP
3.0
2.0
7.0
7.0
4.0
—
—
—
—
—
3.5
2.0
7.0
7.0
5.0
—
—
—
—
—
2.0
1.5
6.0
6.0
2.5
—
—
—
—
—
Hold Time HIGH
or LOW Data to CP
—
—
—
tW
Clock Pulse Width
HIGH or LOW
—
—
—
tW
MR Pulse Width
LOW
—
—
—
tREM
Recovery Time
MR to CP
—
—
—
NOTES:
2558 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
7.10
5
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
SWITCH POSITION
Test
Switch
Closed
Open
7.0V
Open Drain
Disable Low
Enable Low
500Ω
VOUT
VIN
Pulse
Generator
D.U.T.
All Other Tests
50pF
CL
500Ω
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
2558 tbl 08
R T
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
1.5V
0V
DATA
INPUT
tSU
t H
LOW-HIGH-LOW
1.5V
3V
1.5V
0V
TIMING
INPUT
PULSE
t W
ASYNCHRONOUS CONTROL
t REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
t H
tSU
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
CONTROL
INPUT
1.5V
0V
SAME PHASE
INPUT TRANSITION
1.5V
0V
tPZL
tPLZ
tPHL
tPLH
3.5V
1.5V
3.5V
OUTPUT
NORMALLY
LOW
VOH
SWITCH
CLOSED
OUTPUT
1.5V
0.3V
0.3V
VOL
VOH
tPZH
tPHZ
VOL
tPLH
tPHL
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3V
1.5V
0V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
0V
NOTES
2558 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.10
6
IDT54/74FCT273/A/C FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XX
IDT
FCT
X
X
X
Temperature
Range
Device
Type
Package Process
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
SO
L
E
Small Outline IC
Leadless Chip Carrier
CERPACK
273
273A
273C
Octal D Flip-Flop w/Clear
Fast Octal D Flip-Flop w/Clear
Super Fast Octal D Flip-Flop w/Clear
54
74
–55
°C to +125°C
0
°
C to +70°C
2558 drw 03
7.10
7
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