IDT74FCT377ATL [IDT]
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE; 快速CMOS八路D触发器与时钟使能
| 型号： | IDT74FCT377ATL |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE |
| 文件： | 总7页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT377T/AT/CT/DT
FAST CMOS
OCTAL D FLIP-FLOP
WITH CLOCK ENABLE
Integrated Device Technology, Inc.
FEATURES:
• Std., A, C and D speed grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
DESCRIPTION:
TheIDT54/74FCT377T/AT/CT/DTareoctalDflip-flopsbuilt
usinganadvanceddualmetalCMOStechnology. TheIDT54/
74FCT377T/AT/CT/DThaveeightedge-triggered,D-typeflip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW. The register is fully
edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop’s O output. The CE input must be
stable only one set-up time prior to the LOW-to-HIGH transi-
tion for predictable operation.
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 48mA IOL)
• Power off disable outputs permit “live insertion”
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
FUNCTIONAL BLOCK DIAGRAM
D0
D 1
D2
D 3
D4
D5
D6
D 7
CE
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D Q
CP
CP
CP
CP
CP
CP
CP
CP
CP
0
1
2
3
4
5
6
7
O
O
O
O
O
O
O
O
2630 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1995
1995 Integrated Device Technology, Inc.
6.14
DSC-4200/3
1
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
1
2
20
19
18
CE
O0
D0
D1
O1
O2
D2
D3
O3
Vcc
O7
D7
D6
O6
O5
D5
D4
O4
CP
3
2
20 19
18
3
D
D
O
O
D
7
6
6
5
5
4
5
6
7
8
D
O
1
1
P20-1
1
D20-1 17
4
17
16
15
14
SO20-2
L20-2
5
16
O
D
D
2
SO20-8
15
6
2
&
7
14
E20-1
3
13
12
11
8
10 11 12 13
9
9
10
GND
2630 drw 03
2630 drw 02
DIP/SOIC/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
PIN DESCRIPTION
FUNCTION TABLE(1)
Pin Names
D0 – D7
CE
Description
Inputs
Outputs
Data Inputs
Operating Mode
Load “1”
CP
D
h
l
O
H
L
CE
Clock Enable (Active LOW)
Data Outputs
↑
↑
l
l
O0 – O7
CP
Load “0”
Clock Pulse Input
Hold
↑
H
h
H
X
X
No Change
No Change
2630 tbl 01
NOTE:
1. H = HIGH Voltage Level
2630 tbl 02
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH
Clock Transition
L = LOW Voltage Level
ABSOLUTE MAXIMUM RATINGS(1)
l
=
LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
Symbol
Rating
Commercial
Military
Unit
(2)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
X = Don't Care
↑ = LOW-to-HIGH Clock Transition
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
VCC +0.5
–0.5 to
VCC +0.5
V
CAPACITANCE (TA = +25°C, f = 1.0MHz)
TA
Operating
0 to +70
–55 to +125 °C
Symbol
Parameter(1)
Conditions Typ. Max. Unit
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
CIN
Input
Capacitance
Output
VIN = 0V
6
8
10
pF
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
COUT
VOUT = 0V
12
pF
Capacitance
2630 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
PT
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120 –60 to +120 mA
2630 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.14
2
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
VIL
Parameter
Test Conditions(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Min.
2.0
—
Typ.(2)
Max. Unit
Input HIGH Level
—
—
0.8
±1
V
V
Input LOW Level
—
IIH
Input HIGH Current(4)
Input LOW Current(4)
Input HIGH Current(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Max.
VI = 2.7V
—
—
µA
µA
µA
V
IIL
VCC = Max.
VI = 0.5V
—
—
±1
II
VCC = Max., VI = VCC (Max.)
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
VCC = Min.
—
—
±1
VIK
IOS
VOH
—
–0.7
–120
3.3
–1.2
–225
—
–60
2.4
mA
V
IOH = –6mA MIL.
VIN = VIH or VIL
IOH = –8mA COM’L.
IOH = –12mA MIL.
IOH = –15mA COM’L.
IOL = 32mA MIL.
2.0
—
3.0
0.3
—
—
0.5
±1
V
V
VOL
IOFF
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
IOL = 48mA COM’L.
Input/Output Power Off
Leakage(5)
VCC = 0V, VIN or VO ≤ 4.5V
—
µA
VH
Input Hysteresis
Quiescent Power
Supply Current
—
—
—
200
—
1
mV
mA
ICC
VCC = Max.
0.01
VIN = GND or VCC
NOTES:
2630 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = -55°C.
5. This parameter is guaranted but not tested.
6.14
3
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
2.0
mA
ICCD
IC
Dynamic Power Supply
Current(4)
VCC = Max., Outputs Open
CE = GND
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
Total Power Supply
Current(6)
VCC = Max., Outputs Open
fCP = 10MHz
VIN = VCC
VIN = GND
—
—
1.5
2.0
3.5
5.5
mA
CE = GND
One Bit Toggling
fi = 5MHz
VIN = 3.4V
VIN = GND
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz, 50% Duty Cycle
VIN = VCC
VIN = GND
—
—
3.8
6.0
7.3(5)
CE = GND
Eight Bits Toggling
fi = 2.5MHz
VIN = 3.4V
VIN = GND
16.3(5)
50% Duty Cycle
2639 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.14
4
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT377T
FCT54/74FCT377AT
Com'l. Mil.
Com'l.
Mil.
Symbol
tPLH
Parameter
Propagation Delay
CP to On
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
2.0
2.5
2.0
4.0
1.5
7.0
13.0
2.0
15.0
2.0
2.0
1.5
3.5
1.5
6.0
7.2
2.0
8.3
ns
tPHL
tSU
Set-Up Time HIGH or LOW
Dn to CP
—
—
—
—
—
3.0
2.5
4.0
1.5
7.0
—
—
—
—
—
—
—
—
—
—
2.0
1.5
3.5
1.5
7.0
—
—
—
—
—
ns
ns
ns
ns
tH
Hold Time HIGH or LOW
Dn to CP
tSU
tH
Set-Up Time HIGH or LOW
CE to CP
Hold Time HIGH or LOW
CE to CP
tW
Clock Pulse Width,
HIGH or LOW
ns
2630 tbl 06
IDT54/74FCT377CT
Com'l. Mil.
FCT54/74FCT377DT
Com'l. Mil.
Symbol
tPLH
Parameter
Propagation Delay
CP to On
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
2.0
5.2
2.0
5.5
2.0
4.4
—
—
ns
tPHL
tSU
Set-Up Time HIGH or LOW
Dn to CP
2.0
1.5
3.5
1.5
6.0
—
—
—
—
—
2.0
1.5
3.5
1.5
7.0
—
—
—
—
—
2.0
1.0
3.0
0.0
3.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
tH
Hold Time HIGH or LOW
Dn to CP
tSU
tH
Set-Up Time HIGH or LOW
CE to CP
Hold Time HIGH or LOW
CE to CP
tW
Clock Pulse Width,
HIGH or LOW
NOTES:
2630 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
6.14
5
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500Ω
Enable Low
VOUT
VIN
Open
All Other Tests
Pulse
Generator
D.U.T.
2630 lnk 08
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
50pF
C L
500Ω
T
R
2630 drw 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
1.5V
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
ETC.
SYNCHRONOUS CONTROL
PRESET
2630 drw 06
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
2630 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2630 drw 07
0V
2630 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.14
6
IDT54/74FCT377T/AT/CT/DT
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
X
XXXX
X
X
Temperature
Range
Family
Device Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
SO
L
E
Q
Small Outline IC
Leadless Chip Carrier
CERPACK
Quarter-size Small Outline Package
377T
Octal D Flip-Flop w/Clock Enable
377AT
377CT
377DT
Blank High Drive
54
74
–55
°C to +125°C
0
°
C to +70°C
2630 drw 09
6.14
7
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