IDT74FCT543CTSOG8 [IDT]

Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, SOIC-24;
IDT74FCT543CTSOG8
型号: IDT74FCT543CTSOG8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, SOIC-24

光电二极管 输出元件 逻辑集成电路
文件: 总7页 (文件大小:78K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
FAST CMOS  
OCTAL LATCHED  
TRANSCEIVER  
IDT74FCT543AT/CT/DT  
FEATURES:  
DESCRIPTION:  
A, C, and D grades  
Low input and output leakage 1µA (max.)  
• CMOS power levels  
True TTL input and output compatibility:  
VOH = 3.3V (typ.)  
VOL = 0.3V (typ.)  
High Drive outputs (-15mA IOH, 64mA IOL)  
Meets or exceeds JEDEC standard 18 specifications  
• Power off disable outputs permit "live insertion"  
Available in SOIC and QSOP packages  
TheFCT543Tisanon-invertingoctaltransceiverbuiltusinganadvanced  
dualmetalCMOStechnology. ThisdevicecontainstwosetsofeightD-type  
latches withseparate inputandoutputcontrols foreachset. Fordata flow  
fromAtoB,forexample,theA-to-BEnable(CEAB)inputmustbelowinorder  
to enter data from A0A7 or to take data from B0–B7, as indicated in the  
FunctionTable. WithCEAB low, a lowsignalonthe A-to-BLatchEnable  
(LEAB)inputmakes the A-to-Blatches transparent;a subsequentlow-to-  
hightransitionoftheLEABsignalputstheAlatchesinthestoragemodeand  
theiroutputsnolongerchangewiththeAinputs. WithCEABandOEABboth  
low,the3-stateBoutputbuffersareactiveandreflectthedatapresentatthe  
outputofthe Alatches. Controlofdata fromBtoAis similar,butuses the  
CEBA, LEBA andOEBA inputs.  
FUNCTIONALBLOCKDIAGRAM  
DETAIL A  
D
Q
0
B
LE  
Q
D
A
0
LE  
1
2
3
4
5
6
7
1
2
3
4
5
A
A
A
A
A
A
A
B
B
B
B
B
DETAIL A x 7  
6
B
B
7
OEBA  
OEAB  
CEBA  
LEBA  
CEAB  
LEAB  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 2009  
1
© 2009 Integrated Device Technology, Inc.  
DSC-5489/7  
IDT74FCT543AT/CT/DT  
FASTCMOSOCTALLATCHEDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Description  
Max  
Unit  
V
(2)  
VTERM  
Terminal Voltage with Respect to GND  
–0.5 to +7  
(3)  
24  
VTERM  
Terminal Voltage with Respect to GND –0.5 to VCC+0.5  
V
1
LEBA  
OEBA  
V
CC  
TSTG  
IOUT  
Storage Temperature  
DC Output Current  
–65 to +150  
–60 to +120  
° C  
mA  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
3
4
CEBA  
A0  
A1  
A2  
A3  
A4  
A5  
NOTES:  
B
B
B
B
0
1
2
3
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability. No terminal voltage may exceed  
Vcc by +0.5V unless otherwise noted.  
5
6
7
8
9
2. Inputs and Vcc terminals only.  
3. Output and I/O terminals only.  
B
B
B
B
4
5
6
7
CAPACITANCE (TA = +25°C, F = 1.0MHz)  
A
6
7
Symbol  
CIN  
Parameter(1)  
Input Capacitance  
Output Capacitance  
Conditions  
VIN = 0V  
Typ.  
6
Max. Unit  
10  
12  
pF  
pF  
A
10  
11  
COUT  
VOUT = 0V  
8
LEAB  
OEAB  
CEAB  
GND  
NOTE:  
1. This parameter is measured at characterization but not tested.  
12  
SOIC/ QSOP  
TOP VIEW  
PINDESCRIPTION  
Pin Names  
OEAB  
OEBA  
CEAB  
CEBA  
LEAB  
Description  
A-to-BOutputEnableInput(ActiveLOW)  
B-to-AOutputEnableInput(ActiveLOW)  
A-to-BEnable Input(Active LOW)  
B-to-AEnable Input(Active LOW)  
A-to-BLatchEnableInput(ActiveLOW)  
B-to-ALatchEnableInput(ActiveLOW)  
A-to-BDataInputsorB-to-A3-StateOutputs  
B-to-ADataInputsorA-to-B3-StateOutputs  
LEBA  
A0A7  
B0–B7  
2
IDT74FCT543AT/CT/DT  
FASTCMOSOCTALLATCHEDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
FUNCTION TABLE(1, 2)  
ForA-to-B(SymmetricwithB-to-A)  
Latch  
Output  
Buffers  
Inputs  
LEAB  
X
Status  
A-to-B  
Storing  
Storing  
X
CEAB  
H
OEAB  
B0–B7  
HighZ  
X
X
H
L
X
H
X
X
X
HighZ  
L
L
Transparent  
Storing  
CurrentAInputs  
Previous* A Inputs  
L
H
L
NOTES:  
1. * Before LEAB LOW-to-HIGH Transition  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Don’t Care  
2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA  
and OEBA.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
FollowingConditionsApplyUnlessOtherwiseSpecified:  
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%  
Symbol  
VIH  
Parameter  
Input HIGH Level  
Test Conditions(1)  
Guaranteed Logic HIGH Level  
Min.  
2
Typ.(2)  
Max.  
0.8  
1
Unit  
V
VIL  
Input LOW Level  
Guaranteed Logic LOW Level  
VCC = Max.  
V
IIH  
Input HIGH Current(4)  
Input LOW Current(4)  
High Impedance Output Current  
VI = 2.7V  
VI = 0.5V  
VO = 2.7V  
VO = 0.5V  
µA  
µA  
µA  
IIL  
VCC = Max.  
1
IOZH  
IOZL  
VCC = Max  
1
(4)  
(3-State output pins)  
1
II  
Input HIGH Current(4)  
VCC = Max., VI = VCC (Max.)  
VCC = Min, IIN = -18mA  
1
µA  
V
VIK  
VH  
ICC  
ClampDiodeVoltage  
–0.7  
200  
0.01  
–1.2  
1
Input Hysteresis  
mV  
mA  
Quiescent Power Supply Current  
VCC = Max., VIN = GND or VCC  
OUTPUTDRIVECHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
Min.  
2.4  
2
Typ.(2)  
3.3  
Max.  
Unit  
VOH  
OutputHIGHVoltage  
VCC = Min  
IOH = –8mA  
IOH = –15mA  
IOL = 64mA  
V
VIN = VIH or VIL  
3
VOL  
Output LOWVoltage  
VCC = Min  
0.3  
0.55  
V
VIN = VIH or VIL  
(3)  
IOS  
Short Circuit Current  
Input/Output Power Off Leakage(5)  
VCC = Max., VO = GND  
–60  
–120  
–225  
1
mA  
µA  
IOFF  
VCC = 0V, VIN or VO 4.5V  
NOTES:  
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at VCC = 5.0V, +25°C ambient.  
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.  
4. The test limit for this parameter is ±5µA at TA = –55°C.  
5. This parameter is guaranteed but not tested.  
3
IDT74FCT543AT/CT/DT  
FASTCMOSOCTALLATCHEDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
POWERSUPPLYCHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
Min.  
Typ.(2)  
Max.  
Unit  
ΔICC  
Quiescent Power Supply Current  
TTL Inputs HIGH  
VCC = Max.  
VIN = 3.4V  
0.5  
2
mA  
(3)  
ICCD  
IC  
Dynamic Power Supply  
Current(4)  
VCC = Max., Outputs Open  
CEAB and OEAB = GND  
CEBA = VCC  
VIN = VCC  
VIN = GND  
0.15  
0.25  
mA/  
MHz  
One Input Toggling  
50% Duty Cycle  
Total Power Supply Current(6)  
VCC = Max., Outputs Open  
fCP = 10MHz (LEAB )  
50% Duty Cycle  
CEAB and OEAB = GND  
CEBA = VCC  
One Bit Toggling  
VIN = VCC  
VIN = GND  
1.5  
2
3.5  
5.5  
mA  
mA  
VIN = 3.4V  
VIN = GND  
at fi = 5MHz  
50% duty cycle  
(5)  
7.3  
VCC = Max., Outputs Open  
fCP = 10MHz (LEAB )  
50% Duty Cycle  
CEAB and OEAB = GND  
CEBA = VCC  
VIN = VCC  
VIN = GND  
3.8  
6
(5)  
16.3  
VIN = 3.4V  
VIN = GND  
Eight Bits Toggling  
at fi = 2.5MHz  
50% duty cycle  
NOTES:  
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at VCC = 5.0V, +25°C ambient.  
3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND.  
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.  
5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested.  
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC  
IC = ICC + ΔICC DHNT + ICCD (fCP/2+ fiNi)  
ICC = Quiescent Current  
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)  
DH = Duty Cycle for TTL Inputs High  
NT = Number of TTL Inputs at DH  
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)  
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)  
fi = Output Frequency  
Ni = Number of Outputs at fi  
All currents are in milliamps and all frequencies are in megahertz.  
4
IDT74FCT543AT/CT/DT  
FASTCMOSOCTALLATCHEDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE  
74FCT543AT  
74FCT543CT  
74FCT543DT  
(2)  
(2)  
(2)  
Symbol Parameter  
Condition(1)  
CL = 50pF  
RL = 500Ω  
Min.  
Max.  
6.5  
Min.  
Max.  
Min.  
Max.  
Unit  
tPLH  
tPHL  
PropagationDelay  
1.5  
1.5  
5.3  
1.5  
4.4  
ns  
TransparantMode  
Ax to Bx or Bx to Ax  
tPLH  
tPHL  
tPZH  
tPZL  
PropagationDelay  
1.5  
1.5  
8
9
1.5  
1.5  
7
8
1.5  
1.5  
5
ns  
ns  
LEBA to Ax, LEAB to Bx  
OutputEnableTime  
5.4  
OEBA or OEAB to Ax or Bx  
CEBA or CEAB to Ax or Bx  
OutputDisableTime  
tPHZ  
tPLZ  
1.5  
7.5  
1.5  
6.5  
1.5  
4.3  
ns  
OEBA or OEAB to Ax or Bx  
CEBA or CEAB to Ax or Bx  
Set-up Time, HIGH or LOW  
Ax or Bx to LEBA or LEAB  
Hold Time, HIGH or LOW  
Ax or Bx to LEBA or LEAB  
LEBA or LEAB Pulse Width LOW  
tSU  
tH  
2
2
5
2
2
5
1.5  
1.5  
ns  
ns  
ns  
(3)  
tW  
3
NOTES:  
1. See test circuit and waveforms.  
2. Minimum limits are guaranteed but not tested on Propagation Delays.  
3. This limit is guaranteed but not tested.  
5
IDT74FCT543AT/CT/DT  
FASTCMOSOCTALLATCHEDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
TESTCIRCUITSANDWAVEFORMS  
V
CC  
SWITCHPOSITION  
7.0V  
Test  
Switch  
Closed  
Open  
500W  
Open Drain  
Disable Low  
Enable Low  
V
OUT  
V
IN  
Pulse  
Generator  
D.U.T  
.
All Other Tests  
50pF  
500W  
T
R
DEFINITIONS:  
CL = Load capacitance: includes jig and probe capacitance.  
L
C
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.  
Octal Link  
Test Circuits for All Outputs  
3V  
DATA  
1.5V  
0V  
INPUT  
LOW-HIGH-LOW  
tH  
tSU  
1.5V  
PULSE  
3V  
1.5V  
0V  
TIMING  
INPUT  
ASYNCHRONOUS CONTROL  
tW  
tREM  
PRESET  
CLEAR  
ETC.  
3V  
1.5V  
0V  
HIGH-LOW-HIGH  
PULSE  
1.5V  
SYNCHRONOUS CONTROL  
PRESET  
3V  
1.5V  
0V  
CLEAR  
tSU  
tH  
CLOCK ENABLE  
ETC.  
Pulse Width  
Octal Link  
Octal Link  
Set-Up, Hold, and Release Times  
ENABLE  
DISABLE  
3V  
1.5V  
0V  
3V  
SAME PHASE  
CONTROL  
INPUT  
1.5V  
0V  
INPUT TRANSITION  
t
PLH  
t
PHL  
PHL  
t
PZL  
tPLZ  
VOH  
OUTPUT  
3.5V  
1.5V  
3.5V  
1.5V  
OUTPUT  
NORMALLY  
LOW  
SWITCH  
CLOSED  
VOL  
tPLH  
t
0.3V  
0.3V  
VOL  
3V  
1.5V  
0V  
tPZH  
tPHZ  
OPPOSITE PHASE  
INPUT TRANSITION  
VOH  
OUTPUT  
NORMALLY  
HIGH  
SWITCH  
OPEN  
1.5V  
0V  
0V  
Octal Link  
Octal Link  
Propagation Delay  
Enable and Disable Times  
NOTES:  
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.  
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.  
6
IDT74FCT543AT/CT/DT  
FASTCMOSOCTALLATCHEDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
ORDERINGINFORMATION  
XXXX  
XX  
X
XX  
FCT  
Package  
Process  
Device Type  
Temp. Range  
Blank  
Industrial  
Small Outline IC - Green  
Quarter-size Small Outline Package - Green  
SOG  
QG  
Fast CMOS Octal Latched Transceiver  
543AT  
543CT  
543DT  
74  
40 C to +85 C  
DatasheetDocumentHistory  
10/10/09 Pg. 6  
Updatedthe orderinginformationbyremovingthe "IDT"notationandnonRoHSpart.  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
for Tech Support:  
logichelp@idt.com  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
7

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