IDT74FCT810CTPYG8 [IDT]
Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, PDSO20, GREEN, SSOP-20;
| 型号： | IDT74FCT810CTPYG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, FCT Series, 5 True Output(s), 5 Inverted Output(s), CMOS, PDSO20, GREEN, SSOP-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总6页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
IDT74FCT810BT/CT
BUFFER/CLOCK DRIVER
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 600ps (max.)
• Very low duty cycle distortion < 700ps (max.)
• Low CMOS levels
The 74FCT810T is a dual bank inverting/ non-inverting clock driver
builtusingadvanceddualmetalCMOStechnology.Itconsistsoftwobanks
ofdrivers,oneinvertingandonenon-inverting.Eachbankdrivesfiveoutput
buffersfromastandardTTL-compatibleinput.TheFCT810Thas lowoutput
skew, pulse skew and package skew. Inputs are designed with hysteresis
circuitry for improved noise immunity. The outputs are designed with TTL
outputlevelsandcontrollededgeratestoreducesignalnoise. Theparthas
multiplegrounds, minimizingtheeffectsofgroundinductance.
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: -32mA IOH, +48mA IOL
• Two independent output banks with 3-state control:
– One 1:5 inverting bank
– One 1:5 non-inverting bank
• Available in QSOP, SSOP, and SOIC packages
FUNCTIONALBLOCKDIAGRAM
PINCONFIGURATION
1
2
20
19
18
VCC
OA1
OA2
OA3
GND
OA4
OA5
GND
VCC
OB1
OB2
OB3
GND
OB4
OB5
GND
OEA
5
3
4
5
INA
OA1 -OA5
17
16
15
14
13
12
11
6
7
8
OEB
INB
5
OB1 -OB5
9
OEA
INA
OEB
INB
10
QSOP/ SOIC/ SSOP
TOP VIEW
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 2010
1
c
2001 Integrated Device Technology, Inc.
DSC-4646/3
IDT74FCT810BT/CT
FASTCMOSBUFFER/CLOCKDRIVER
COMMERCIALTEMPERATURERANGE
CAPACITANCE (TA = +25OC, f = 1.0MHz)
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
CIN
Parameter(1)
Conditions
VIN = 0V
Typ.
4.5
Max. Unit
Symbol
VTERM
TSTG
Description
Max
Unit
V
InputCapacitance
OutputCapacitance
6
8
pF
pF
TerminalVoltagewithRespecttoGND
StorageTemperature
–0.5 to +7
–65to+150
COUT
VOUT = 0V
5.5
°C
NOTE:
IOUT
DCOutputCurrent
–60to+120
mA
1. This parameter is measured at characterization but not tested.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PINDESCRIPTION
Pin Names
OEA, OEB
INA, INB
Description
3-StateOutput-EnableInputs(ActiveLOW)
ClockInputs
OAx, OBx
ClockOutputs
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Commercial: TA = 0°C to +70°C, VCC = 5V ± 5%
Symbol
VIH
Parameter
TestConditions(1)
Guaranteed Logic HIGH Level
GuaranteedLogicLOWLevel
VCC = Max.
Min.
2
Typ.(2)
—
Max.
—
Unit
V
Input HIGH Level (Input pins)
InputLOWLevel
VIL
—
—
—
—
—
—
—
–60
2.4
2
—
0.8
1
V
IIH
Input HIGH Current (Input pins)
InputLOWCurrent(Inputpins)
HighImpedanceOutputCurrent
(3-StateOutputpins)
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
µA
µA
µA
IIL
VCC = Max.
—
1
IOZH
IOZL
II
VCC = Max.
—
1
—
1
Input HIGH Current
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
VCC = Min.
—
1
µA
V
VIK
ClampDiodeVoltage
ShortCircuitCurrent
–0.7
–120
3.3
3
–1.2
–225
—
IOS
mA
V
VOH
Output HIGH Voltage
IOH = –15mA
IOH = –32mA(4)
IOL = 48mA
VIN = VIH or VIL
—
VOL
OutputLOWVoltage
VCC = Min.
—
0.3
0.55
V
VIN = VIH or VIL
IOFF
VH
Input/OutputPowerOffLeakage
InputHysteresisforallinputs
Quiescent Power Supply Current
VCC = 0V, VIN or VO ≤4.5V
—
—
—
—
—
150
5
1
—
µA
mV
µA
ICCL
ICCH
ICCZ
VCC = Max., VIN = GND or VCC
500
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition should not exceed one second.
2
IDT74FCT810BT/CT
COMMERCIALTEMPERATURERANGE
FASTCMOSBUFFER/CLOCKDRIVER
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
VCC = Max.
VIN = 3.4V(3)
—
0.5
2
mA
TTL Inputs HIGH
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
VIN = VCC
—
—
60
100
13
µA/MHz
OutputsOpen
VIN = GND
OEA = OEB = GND
50% Duty Cycle
VCC = Max.
IC
TotalPowerSupplyCurrent(6)
VIN = VCC
7.5
mA
OutputsOpen
VIN = GND
fO = 25MHz
50% Duty Cycle
OEA = GND, OEB = VCC
VCC = Max.
VIN = 3.4V
VIN = GND
VIN = VCC
VIN = GND
—
—
7.8
30
14
50.5(5)
OutputsOpen
fO = 50MHz
50% Duty Cycle
OEA = OEB = GND
VIN = 3.4V
VIN = GND
—
30.5
52.5(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO = Output Frequency
NO = Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
3
IDT74FCT810BT/CT
FASTCMOSBUFFER/CLOCKDRIVER
COMMERCIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE(3,4)
FCT810BT
FCT810CT
(2)
(2)
Symbol
tPLH
Parameter
Conditions(1)
CL = 50pF
Min.
Max.
Min.
Max.
Unit
PropagationDelay
1.5
4.5
1.5
4.3
ns
tPHL
INA to OAx, INA to OBx
RL = 500Ω
tR
OutputRiseTime
—
—
—
1.5
1.5
0.5
—
—
—
1.5
1.5
0.3
ns
ns
ns
tF
OutputFallTime
tSK1(O)
Outputskew(samebank):skewbetweenoutputsof
samebankandsamepackage(sametransition)
Outputskew(allbanks):skewbetweenoutputsof
allbanksofsamepackage(inputstiedtogether)
Pulseskew:skewbetweenoppositetransitions
ofsameoutput(|tPHL-–tPLH|)
tSK2(O)
tSK(P)
—
—
0.7
0.7
—
—
0.6
0.7
ns
ns
tSK(T)
Packageskew:skewbetweenoutputsofdifferent
packagesatsamepowersupplyvoltage,
temperature,packagetypeandspeedgrade
OutputEnableTime
—
1.2
—
1
ns
tPZL
tPZH
tPLZ
tPHZ
1.5
1.5
6
6
1.5
1.5
5
5
ns
ns
OEA to OAx, OEB to OBx
OutputDisableTime
OEA to OAx, OEB to OBx
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
4
IDT74FCT810BT/CT
COMMERCIALTEMPERATURERANGE
FASTCMOSBUFFER/CLOCKDRIVER
TESTCIRCUITSANDWAVEFORMS
SWITCHPOSITION
V CC
7.0V
Test
Switch
500
Disable LOW
Enable LOW
Closed
V OUT
VIN
Pulse
Generator
D.U.T.
Disable HIGH
Enable HIGH
GND
50pF
500
T
R
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
L
C
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuit for All Outputs
3V
1.5V
3V
INPUT
0V
tPLH1
tPHL1
1.5V
0V
VOH
INPUT
1.5V
VOL
tPLH
tPHL
OUTPUT 1
OUTPUT 2
tSK(o)
tSK(o)
VOH
VOH
2.0V
1.5V
VOL
1.5V
VOL
0.8V
OUTPUT
tPLH2
tPHL2
tF
tR
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Output Skew (Same Bank) - tSK1(O)
Package Delay
3V
1.5V
0V
3V
INPUT
tPLH1
tSK(o)
tPLH2
tPHL1
1.5V
0V
VOH
INPUT
1.5V
VOL
tPHL
tPLH
OUTPUT 1
OUTPUT 2
VOH
1.5V
VOL
tSK(o)
VOH
1.5V
VOL
OUTPUT
tSK(p) = |tPHL - tPLH|
tPHL2
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Pulse Skew - tSK(P)
Output Skew (All Banks) - tSK2(O)
ENABLE
DISABLE
3V
3V
1.5V
0V
CONTROL
INPUT
1.5V
0V
INPUT
tPD1b
tPD1a
VOH
1.5V
VOL
PZL
PLZ
t
t
3.5V
1.5V
3.5V
V OL
OUTPUT
NORMALLY
LOW
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
SWITCH
CLOSED
tSK2(o)
tSK2(o)
VOH
1.5V
VOL
0.3V
t
PZH
PHZ
t
tPD2a
tPD2b
OUTPUT
NORMALLY
HIGH
0.3V VOH
0V
SWITCH
OPEN
1.5V
0V
tSK(t) = |tPD2a - tPD1a| or |tPD2b - tPD1b|
Package Skew - tSK(T)
Enable and Disable Times
NOTES:
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤1.0MHz; tF ≤2.5ns; tR ≤2.5ns
5
IDT74FCT810BT/CT
FASTCMOSBUFFER/CLOCKDRIVER
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
FCT
XX
XXX
XX
Package
Temp. Range
Device Type
SOG
PYG
SOIC - Green
SSOP - Green
QSOP - Green
QG
Inverting, Non-Inverting Buffer/Clock Driver
810BT
810CT
0°C to + 70°C
74
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6
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