IDT74FCT810CTSOG [IDT]
暂无描述;
| 型号： | IDT74FCT810CTSOG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 暂无描述 时钟驱动器 |
| 文件： | 总6页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT810BT/CT
FAST CMOS
BUFFER/CLOCK DRIVER
Integrated Device Technology, Inc.
LCC packages
• Military product compliant to MIL-STD-883, Class B
FEATURES:
• 0.5 MICRON CMOS technology
• Guaranteed low skew < 600ps (max.)
• Very low duty cycle distortion < 700ps (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: –32mA IOH, 48mA IOL
• Two independent output banks with 3-state control
– One 1:5 Inverting bank
DESCRIPTION:
The IDT54/74FCT810BT/CT is a dual bank inverting/ non-
inverting clock driver built using advanced dual metal CMOS
technology. It consists of two banks of drivers, one inverting
and one non-inverting. Each bank drives five output buffers
from a standard TTL-compatible input. The IDT54/
74FCT810BT/CT have low output skew, pulse skew and
package skew. Inputs are designed with hysteresis circuitry
for improved noise immunity. The outputs are designed with
TTL output levels and controlled edge rates to reduce signal
noise. Theparthasmultiplegrounds, minimizingtheeffectsof
ground inductance.
– One 1:5 Non-Inverting bank
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, CERPACK and
FUNCTIONAL BLOCK DIAGRAMS
PIN CONFIGURATIONS
1
2
3
4
5
20
19
18
V
CC
V
CC
OA
OA
OA
1
2
3
OB
OB
OB
1
2
3
OE
A
5
5
IN
A
OA1-OA5
17
16
15
14
13
12
11
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
GND
GND
OA
4
5
6
7
8
OB
OB
4
5
OEB
OA
E20-1
INB
OB1-OB5
GND
OE
IN
GND
OE
IN
3103 drw 01
9
A
B
10
A
B
3103 drw 02
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
INDEX
3
2
20 19
1
OB
2
OA
3
4
5
6
7
8
18
17
16
15
14
OB
3
GND
OA
4
5
GND
L20-2
OA
OB
OB
4
5
GND
9 10 11 12 13
LCC
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
3103 drw 03
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1995
1995 Integrated Device Technology, Inc.
9.4
DSC-4646/3
1
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
Military
Unit
Pin Names
Description
(2)
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
with Respect to
GND
V
OEA, OEB
INA, INB
3-State Output Enable Inputs (Active LOW)
Clock Inputs
(3)
OAn, OBn
Clock Outputs
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to VCC
+0.5
–0.5 to VCC
+0.5
V
3103 tbl 01
TA
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125 °C
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
CIN
Input
Capacitance
Output
VIN = 0V
4.5
5.5
6.0
pF
COUT
VOUT = 0V
8.0
pF
Capacitance
IOUT
–60 to +120 –60 to +120 mA
3103 lnk 02
NOTE:
1. This parameter is measured at characterization but not tested.
3103 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals.
3. Output and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
0.8
±1
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
V
µA
µA
µA
µA
µA
V
Input HIGH Current(5)
Input LOW Current(5)
High Impedance Output Current
(3-State Output pins)(5)
Input HIGH Current(5)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Max.
VCC = Max.
VCC = Max.
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
—
II L
—
—
±1
IOZH
IOZL
II
—
—
±1
—
—
±1
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN= –18mA
VCC = Max.(3), VO = GND
—
—
±1
VIK
IOS
VOH
—
–0.7
–1.2
–60
2.4
–120 –225
mA
V
VCC = Min.
IOH = –12mA MIL.
3.3
3.0
0.3
—
VIN = VIH or VIL
IOH = –15mA COM'L.
IOH = –24mA MIL.
IOH = –32mA COM'L.(4)
IOL = 32mA MIL.
2.0
—
—
VOL
Output LOW Voltage
VCC = Min.
0.55
V
VIN = VIH or VIL
IOL = 48mA COM'L.
IOFF
VH
Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V
—
—
—
—
150
5
±1
—
µA
mV
µA
Input Hysteresis for all inputs
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
500
3103 lnk 04
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
9.4
2
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
2.0
mA
∆ICC
ICCD
Dynamic Power Supply Current(4) VCC = Max.
Outputs Open
VIN = VCC
VIN = GND
—
60
100
µA/
MHz/bit
OEA = OEB = GND
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fo= 25MHz
VIN = VCC
VIN = GND
—
7.5
7.8
13
mA
50% Duty Cycle
OEA = GND, OEB =VCC
VIN = 3.4V
VIN = GND
—
—
14.0
VCC = Max.
Outputs Open
fo = 50MHz
VIN = VCC
VIN = GND
30.0 50.5(5)
30.5 52.5(5)
50% Duty Cycle
OEA = OEB = GND
VIN = 3.4V
VIN = GND
—
3103 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO= Output Frequency
NO= Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
9.4
3
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT54/74FCT810BT
IDT54/74FCT810CT
Com'l.
Mil.
Com'l.
Mil.
(2)
(2)
(2)
(2)
Condition(1)
CL = 50pF
RL = 500Ω
Unit
Min.
Max. Min.
Max. Min.
Max. Min.
Max.
Symbol
tPLH
Parameter
Propagation Delay
INA to OAn, INB to OBn
Output Rise Time
1.5
4.5
1.5
4.9
1.5
4.3
1.5
4.6
ns
tPHL
tR
—
—
—
1.5
1.5
0.5
—
—
—
2.0
1.5
0.9
—
—
—
1.5
1.5
0.3
—
—
—
2.0
1.5
0.7
ns
ns
ns
tF
Output Fall Time
tSK1(o) Output skew (same bank): skew between
outputs of same bank and same package
(same transition)
tSK2(o) Output skew (all banks): skew between
outputs of all banks of same package
(inputs tied together)
—
0.7
—
1.1
—
0.6
—
1.0
ns
tSK(p) Pulse skew: skew between opposite
transitions of same output |(tPHL-tPLH)|
—
—
0.7
1.2
—
—
1.2
1.5
—
—
0.7
1.0
—
—
1.1
1.2
ns
ns
tSK(t) Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
tPZL
tPZH
Output Enable Time
1.5
1.5
6.0
6.0
1.5
1.5
6.5
6.5
1.5
1.5
5.0
5.0
1.5
1.5
6.0
6.0
ns
OEA to OAn, OEB to OBn
Output Disable Time
OEA to OAn, OEB to OBn
tPLZ
ns
tPHZ
NOTES:
3103 tbl 06
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.4
4
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS
ENABLE AND DISABLE TIME
SWITCH POSITION
VCC
7.0V
Test
Disable LOW
Enable LOW
Switch
Closed
500Ω
500Ω
V OUT
VIN
Disable HIGH
Enable HIGH
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Open
Pulse
Generator
D.U.T.
3103 lnk 07
50pF
C L
R T
Generator.
3103drw04
TEST WAVEFORMS
PACKAGE DELAY
OUTPUT SKEW (SAME BANK) - tSK1(o)
3V
3V
1.5V
0V
1.5V
0V
INPUT
t
PLH1
tPHL1
INPUT
V
OH
t
PLH
tPHL
1.5V
V
OH
V
OL
OUTPUT 1
OUTPUT 2
2.0V
tSK1(o)
t
SK1(o)
1.5V
VOH
0.8V
1.5V
V
OL
OUTPUT
VOL
t
PLH2
t
F
tPHL2
t
R
3103 drw 05
tSK1(o) = |tPLH2 -
t
PLH1
|
or |tPHL2 -
t
PLH1
|
3103 drw 06
OUTPUT SKEW (ALL BANKS) - tSK2(o)
PULSE SKEW - tSK(p)
3V
1.5V
0V
3V
INPUT
t
PLH1
t
PHL1
1.5V
0V
V
1.5V
V
OH
INPUT
tPHL
t
PLH
OUTPUT 1
OUTPUT 2
VOH
OL
t
SK2(o)
t
t
SK2(o)
1.5V
V
OH
VOL
OUTPUT
1.5V
V
OL
t
SK(p) = |tPHL - tPLH|
t
PHL2
PLH2
t
SK2(o) = |tPHL2 -
tPLH1
|
or |tPLH2 -
t
PHL1
|
3103 drw 08
3103 drw 07
PACKAGE SKEW - tSK(t)
ENABLE AND DISABLE TIMES
3V
ENABLE
DISABLE
1.5V
0V
3V
INPUT
t
PD1a
CONTROL
INPUT
t
PD1b
1.5V
0V
VOH
1.5V
t
PZL
t
PLZ
VOL
3.5V
1.5V
3.5V
VOL
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
t
SK2(o)
tSK2(o)
V
OH
0.3V
0.3V
1.5V
t
PZH
tPHZ
VOL
V
OH
tPD2a
tPD2b
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
t
SK(t) = |tPD2a -
tPD1a| or |tPD2b- tPD1b
|
0V
Package 1 and Package 2 are same device type and speed grade
3103 drw 10
3103 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
9.4
5
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTXXFCT
Temp. Range Device Type
XXX
XX
Package
X
Process/
Temperature
Range
Blank
B
Commercial
Military (-55°C to +125°C) Compliant to
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
E
L
SO
PY
Q
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline IC
Inverting, Non-Inverting Buffer/Clock driver
810BT
810CT
-55°C to +125°C
0°C to + 70°C
3103 drw 13
54
74
9.4
6
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