IDT74LVC109AQ8 [IDT]
J-Kbar Flip-Flop, LVC/LCX/Z Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, QSOP-16;
| 型号： | IDT74LVC109AQ8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | J-Kbar Flip-Flop, LVC/LCX/Z Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, QSOP-16 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总6页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS DUAL
IDT74LVC109A
J-K FLIP-FLOP WITH SET AND
RESET, POSITIVE-EDGE TRIG-
GER, AND 5 VOLT TOLERANT I/O
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The LVC109A dual J-Kflip-flop with set and reset, positive-edge trigger
isbuiltusingadvanceddualmetalCMOStechnology. Thisdevicefeatures
individualJ,Kinputs, clock(CP)inputs, set(SD)andreset(RD)inputs;also
complementaryQandQoutputs.Thesetandresetareasynchronousactive
lowinputsandoperateindependentlyoftheclockinput. TheJandKinputs
controlthestatechangesoftheflip-flopsasdescribedinthefunctiontable.
TheJandKinputsmustbestableonesetuptimepriortothelow-to-highclock
transition for predictable operation. The J-K design allows operation as a
D-type flip-flop by tying the J and K inputs together.
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• All inputs, outputs, and I/Os are 5V tolerant
• Supports hot insertion
• Available in QSOP, SOIC, SSOP, and TSSOP packages
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC109A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
7
Q
3
C
C
C
C
C
C
K
6
Q
2
5
J
SD
RD
CP
C
C
1
4
C
C
NOTE:
Pin numbers are for section 1. Refer to pin configuration for section 2 pin numbers.
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
AUGUST 1999
1
©1999 Integrated Device Technology, Inc.
DSC-4744/1
IDT74LVC109A
3.3VCMOSDUALJ-K FLIP-FLOPWITHSETANDRESET
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
1
2
3
1RD
1J
16
15
14
13
VCC
2RD
°C
mA
mA
IOUT
DC Output Current
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
1K
2J
4
5
6
1CP
1SD
1Q
2K
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
2CP
2SD
2Q
12
11
10
9
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1Q
7
8
GND
2Q
QSOP/ SOIC/ SSOP/ TSSOP
TOP VIEW
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
FUNCTIONALDIAGRAM
COUT
CI/O
5.5
6.5
NOTE:
1. As applicable to the device type.
5
2
4
1SD
1J
SD
1Q
1Q
6
7
J
Q
1CP
1K
FF1
Q
CP
3
1
K
PINDESCRIPTION
RD
Pin Names
Description
1RD
xCP
xRD
ClockInputs,LOW-to-HIGH,edge-triggered
Asynchronous Reset Input (Active LOW)
Asynchronous Set Inputs (Active LOW)
SynchronousInputs
11
14
2SD
2J
xSD
SD
2Q
2Q
10
9
J
xJ, xK
xQ
Q
TrueFlip-FlopOutputs
2CP
2K
12
13
CP FF2
xQ
ComplementFlip-FlopOutputs
Q
K
RD
2RD
15
2
IDT74LVC109A
3.3VCMOSDUALJ-K FLIP-FLOPWITHSETANDRESET
INDUSTRIALTEMPERATURERANGE
FUNCTIONTABLE(1)
Inputs
Outputs
OperatingModes
Asynchronousset
Asynchronousreset
Undetermined
Toggle
xSD
L
xRD
H
xCP
X
xJ
X
X
X
h
xK
X
X
X
l
xQ
H
xQ
L
H
L
X
L
H
L
L
X
H
H
Q(3)
(2)
H
H
↑
Q
Load“0”(reset)
Load “1” (set)
H
H
↑
↑
l
l
L
H
H
H
h
h
H
L
(2)
Hold “no change”
H
H
↑
l
h
Q(3)
Q
NOTES:
1. H = HIGH Voltage Level
h = HIGH voltage level of input set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level of input set-up time prior to LOW-to-HIGH CP transition
X = Don't Care
↑ = LOW-to-HIGH transition
2. Complement of Q or level of Q before the indicated steady-state input conditions
were established.
3. Level of Q before the indicated steady-state input conditions were established.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
V
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
µA
IOZH
IOZL
IOFF
VIK
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
±50
µA
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
VH
Input Hysteresis
VCC = 3.3V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V, VIN = GND or VCC
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
500
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74LVC109A
3.3VCMOSDUALJ-K FLIP-FLOPWITHSETANDRESET
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2.2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
PowerDissipationCapacitanceperFlip-Flop
CL = 0pF, f = 10Mhz
—
pF
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPLH
tPHL
PropagationDelay
xCP to xQ or x Q
—
9
—
—
—
8.5
—
7.5
ns
ns
ns
tPLH
PropagationDelay
xSD to xQ or xRD xQ
—
—
11
10
9
—
—
8
9
tPHL
PropagationDelay
10
xSD to xQ or xRD xQ
tSU
tH
Set-up Time, xJ, xK to xCP
Hold Time, xJ, xK to xCP
2.5
2
—
—
—
—
—
—
2.5
2
—
—
—
—
—
—
2.5
2
—
—
ns
ns
ns
ns
ns
ps
tREM
tW
Removal Time, xSD, xRD to xCP
Pulse Width, CLK HIGH or LOW
Set or Reset Pulse Width, HIGH or LOW
OutputSkew(2)
3
3
3
—
3.3
3
3.3
3
3.3
3
—
tW
—
tSK(o)
—
—
—
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
Skew between any two outputs of the same package and switching in the same direction.
2
4
IDT74LVC109A
3.3VCMOSDUALJ-K FLIP-FLOPWITHSETANDRESET
INDUSTRIALTEMPERATURERANGE
VIH
VT
0V
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
SAME PHASE
INPUT TRANSITION
tPHL
tPHL
tPLH
tPLH
Symbol
VLOAD
VIH
VCC(1)=2.5V±0.2V
VCC(2)= 3.3V±0.3V & 2.7V
Unit
V
VOH
VT
VOL
OUTPUT
2 x Vcc
Vcc
6
2.7
1.5
300
300
50
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VT
Vcc / 2
150
V
VLZ
mV
mV
pF
LVC QUAD Link
VHZ
150
Propagation Delay
CL
30
VLOAD
Open
GND
VCC
DISABLE
ENABLE
VIH
VT
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
D.U.T.
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
Generator
SWITCH
CLOSED
VLZ
VOL
500Ω
RT
tPHZ
tPZH
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
LVC QUAD Link
0V
Test Circuit for All Outputs
LVC QUAD Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
Enable and Disable Times
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
SWITCHPOSITION
Test
Switch
VLOAD
GND
VIH
DATA
INPUT
VT
Open Drain
Disable Low
Enable Low
0V
tSU
tH
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
Disable High
Enable High
tREM
SYNCHRONOUS
CONTROL
All Other Tests
Open
VIH
VT
ASYNCHRONOUS
CONTROL
tSU
0V
tH
VIH
LVC QUAD Link
VT
0V
INPUT
Set-up, Hold, and Release Times
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
OUTPUT 1
tSK (x)
tSK (x)
VT
PULSE
VOH
tW
VT
OUTPUT 2
VOL
HIGH-LOW-HIGH
PULSE
VT
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
LVC QUAD Link
LVC QUAD Link
Pulse Width
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC109A
3.3VCMOSDUALJ-K FLIP-FLOPWITHSETANDRESET
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
IDT
XXXX
XX
LVC
Device Type Package
Temp. Range
Q
Quarter Size Outline Package
DC
PY
PG
Small Outline IC
Shrink Small Outline Package
Thin Shrink Small Outline Package
Dual J-K Flip-Flop with Set and Reset,
Postive-Edge Trigger, ±24mA
109A
74
-40°C to +85°C
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6
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