IDT74LVC161APGG [IDT]

Binary Counter, LVC/LCX/Z Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, TSSOP-16;


型号：	IDT74LVC161APGG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Binary Counter, LVC/LCX/Z Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, TSSOP-16 光电二极管输出元件逻辑集成电路触发器
文件：	总7页 (文件大小：137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVC161A

3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER

INDUSTRIALTEMPERATURERANGE

3.3V CMOS PRESETTABLE

IDT74LVC161A

SYNCHRONOUS 4-BIT BINARY

COUNTER WITH ASYNCHRONOUS

RESET, 5 VOLT TOLERANT I/O

FEATURES:

features an internal look-ahead carry and can be used for high-speed

counting. Synchronousoperationisprovidedbyhavingallflip-flopsclocked

simultaniouslyonthepositive-goingedgeoftheclock(CP). Outputs (Q₀to

Q₃)ofthe counters maybe presettoa highorlowlevel. Alowlevelatthe

parallelenableinput(PE)disables thecountingactionandcauses thedata

• 0.5 MICRON CMOS Technology

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• All inputs, outputs, and I/Os are 5V tolerant

• Supports hot insertion

atinputs (D toD )tobeloadedintothecounteronthepositive-goingedge

oftheclock⁰(providedthattheset-upandholdtimerequirements forPEare

met). Presettakes placeregardless ofthelevels atthecountenableinputs

(CEPandCET). Alowlevelatthemasterresetinput(MR)setsallfouroutputs

oftheflip-flops(Q₀toQ₃)tolowlevelregardlessofthelevelsatCP,PE,CET,

and CEP inputs (thus providing an asynchronous clear function).

The look-aheadcarrysimplifies serialcascadingofthe counters. Both

countenable inputs (CEPandCET)mustbe hightocount. The CETinput

is fedforwardtoenabletheterminalcountoutput(TC). TheTCoutputthus

enabledwillproduceahighoutputpulseofadurationapproximatelyequal

to a high level output of Q₀. This pulse can be used to enable the next

cascadedstage. Themaximumclockfrequencyforthecascadedcounters

isdeterminedbytheCPtoTCpropagationdelayandCEPtoCPset-uptime,

accordingtothefollowingformula:

• Available in SOIC and TSSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

f_max

DESCRIPTION:

tp_(max)(CP to TC) + t_su(CEP to CP)

TheLVC161Ais ahigh-performance,low-power,low-voltage,Si-gate

CMOSdevice,superiortomostadvancedCMOS-compatibleTTLfamilies.

The LVC161A is a presettable synchronous binary counter which

Inputs canbe drivenfromeither3.3Vor5Vdevices.This feature allows

the use of this device as a translator in a mixed 3.3V/5V supply system.

FUNCTIONALDIAGRAM

STATEDIAGRAM

PARALLEL LOAD

CIRCUITRY

CET

CEP

BINARY COUNTER

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

OCTOBER 1999

DSC-5156/3

IDT74LVC161A

3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER

INDUSTRIALTEMPERATURERANGE

FUNCTIONALBLOCKDIAGRAM

CET

CEP

FF3

FF0

FF1

FF2

IDT74LVC161A

3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

TYPICAL TIMING SEQUENCE

Symbol

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

VTERM

TSTG

IOUT

–0.5 to +6.5

–65 to +150

–50 to +50

–50

°C

DC Output Current

IIK

Continuous Clamp Current,

VI < 0 or VO < 0

IOK

ICC

ISS

Continuous Current through each

VCC or GND

±100

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

CEP

CET

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

5.5

6.5

NOTE:

RESET PRESET

COUNT

INHIBIT

1. As applicable to the device type.

PINDESCRIPTION

Pin Names

PINCONFIGURATION

Description

Asynchronous Master Reset (Active LOW)

VCC

ClockInput(LOW-to-HIGH,Edge-Triggered)

DataInputs

CEP

GND

CountEnableInputs

Ground(0V)

ParallelEnableInput(ActiveLOW)

Count Enable Carry Input

Flip-FlopOutputs

CET

TerminalCountOutput

Positive Supply Voltage

Vcc

CET

CEP

GND

SOIC/ SSOP

TOP VIEW

IDT74LVC161A

3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER

INDUSTRIALTEMPERATURERANGE

FUNCTION TABLE⁽¹⁾

OPERATING

INPUTS

OUTPUTS

MODES

CEP

CET

Reset(clear)

Parallelload

↑

Count

Hold

count

Q⁽²⁾

(donothing)

Q⁽²⁾

NOTE:

1. H = HIGH Voltage Level

h = HIGH Voltage level one setup time prior to the LOW-to-HIGH clock transition.

L = LOW Voltage Level

= LOW Voltage level one setup time prior to the LOW-to-HIGH clock transition.

X = Don’t care

= The TC output is HIGH when CET is HIGH and the counter is at Terminal Count (HHHH).

↑ = LOW-to-HIGH clock transition

2. Indicates the state of the referenced output one set up time prior to the LOW-to-HIGH clock transition.

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

(2)

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

IOFF

VIK

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V, VIN = GND or VCC

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

—

500

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. Clock Pin (CP) requires a minimum VIH of 2.5V.

IDT74LVC161A

3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitance

CL = 0pF, f = 10Mhz

—

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

tPLH

tPHL

PropagationDelay

CP to Qx

—

tPLH

tPHL

PropagationDelay

CP to TC

—

8.8

—

9.5

7.8

tPLH

tPHL

PropagationDelay

CET to TC

tPLH

PropagationDelay

MR to Qx

tPHL

PropagationDelay

—

MR to TC

Clock Pulse Width, HIGH or LOW

MasterResetWidthLOW

Removal Time, MR to CP

Set-Up Time, Dx to CP

Set-Up Time, PE to CP

Set-Up Time, CEP, CET to CP

Hold Time, Dx, PE, CEP, CET to CP

OutputSkew⁽²⁾

—

500

tREM

tSU

0.5

3.5

5.5

0.5

tSK(o)

—

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

Skew between any two outputs of the same package and switching in the same direction.

IDT74LVC161A

3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER

INDUSTRIALTEMPERATURERANGE

VIH

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

SAME PHASE

INPUT TRANSITION

tPHL

tPLH

Symbol

VLOAD

VIH

VCC⁽¹⁾=2.5V±0.2V

VCC⁽²⁾= 3.3V±0.3V & 2.7V

Unit

VOH

VOL

OUTPUT

2 x Vcc

Vcc

2.7

1.5

300

VIH

OPPOSITE PHASE

INPUT TRANSITION

Vcc / 2

150

VLZ

LVC QUAD Link

VHZ

150

Propagation Delay

VLOAD

Open

GND

VCC

DISABLE

ENABLE

VIH

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

(1, 2)

Pulse

D.U.T.

VLOAD/2

OUTPUT

NORMALLY

LOW

Generator

SWITCH

CLOSED

VLZ

VOL

500Ω

tPHZ

tPZH

OUTPUT

NORMALLY

HIGH

VOH

VHZ

SWITCH

OPEN

LVC QUAD Link

Test Circuit for All Outputs

LVC QUAD Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

Enable and Disable Times

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

SWITCHPOSITION

Test

Switch

V^LOAD

GND

VIH

DATA

INPUT

Open Drain

Disable Low

Enable Low

t^SU

VIH

TIMING

INPUT

Disable High

Enable High

tREM

VIH

SYNCHRONOUS

CONTROL

All Other Tests

Open

VIH

ASYNCHRONOUS

CONTROL

tSU

VIH

LVC QUAD Link

INPUT

Set-up, Hold, and Release Times

tPLH1

tPHL1

V^OH

VOL

LOW-HIGH-LOW

OUTPUT 1

tSK (x)

PULSE

VOH

VOL

OUTPUT 2

HIGH-LOW-HIGH

PULSE

tPLH2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

tPHL2

LVC QUAD Link

Pulse Width

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVC161A

3.3VCMOSPRESETTABLESYNCHRONOUS4-BITBINARYCOUNTER

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

Temp. Range

LVC

XXXX

Device Type Package

Small Outline IC

Thin Shrink Small Outline Package

161A

Presettable Synchronous 4-Bit Binary Counter with Asynchronous

Reset, 5 Volt Tolerant I/O, ±±4mA

–40°C to +85°C

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

logichelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

IDT74LVC161APGG [IDT]

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