IDT74LVC16543APA [IDT]
Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56;型号: | IDT74LVC16543APA |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, TSSOP-56 光电二极管 输出元件 逻辑集成电路 |
文件: | 总6页 (文件大小:83K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT74LVC16543A
3.3V CMOS 16-BIT
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
The LVC16543A 16-bit registered transceiver is built using advanced
dual metal CMOS technology. This high-speed, low-power device can be
used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-
enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are
provided for each register to permit independent control in either direction
of data flow. For example, theA-to-B enable (CEAB) must be low to enter
data from the A port or to output data from the B port. LEAB controls the
latch function. When LEAB is low, the latches are transparent. A subse-
quent low-to-high transition of LEAB signal puts theAlatches in the storage
mode. OEAB performs the output enable function on the B port. Data flow
from the B port to theAport is similar but requires using CEBA, LEBA, and
OEBA inputs. Flow-through organization of signal pins simplifies layout.All
inputs are designed with hysteresis for improved noise margin.
All pins of this 16-bit latched transceiver can be driven from either 3.3V
or 5V devices. This feature allows the use of this device as a translator in
a mixed 3.3V/5V supply system.
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
The LVC16543A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
FUNCTIONALBLOCKDIAGRAM
29
56
2OEBA
1OEBA
31
54
2CEBA
1CEBA
30
55
2LEBA
1LEBA
28
1
2OEAB
1OEAB
26
3
2CEAB
1CEAB
27
2
2LEAB
1LEAB
C1
C1
15
2A1
5
1A1
42
52
2B1
1D
1B1
1D
C1
1D
C1
1D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JULY 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4730/2
IDT74LVC16543A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
°C
mA
mA
1
2
56
55
54
53
52
1OEAB
1OEBA
1LEBA
IOUT
DC Output Current
1LEAB
1CEAB
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
3
1CEBA
GND
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
GND
4
5
6
1A1
1A2
VCC
1A3
1B1
1B2
VCC
1B3
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
51
50
49
48
7
8
9
1A4
1A5
1B4
1B5
CAPACITANCE (TA = +25°C, F = 1.0MHz)
10
47
46
45
44
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
11
12
13
14
15
16
17
18
GND
1A6
GND
1B6
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
COUT
CI/O
6.5
1A7
1A8
1B7
1B8
2B1
2B2
2B3
6.5
NOTE:
43
42
1. As applicable to the device type.
2A1
2A2
2A3
41
PINDESCRIPTION
Pin Names
40
39
38
Description
GND
xOEAB
xOEBA
xCEAB
xCEBA
xLEAB
xLEBA
xAx
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
GND
19
20
21
22
23
2A4
2A5
2A6
VCC
2A7
2A8
2B4
2B5
2B6
VCC
2B7
2B8
37
36
35
34
33
32
31
30
29
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-BDataInputsorB-to-A3-StateOutputs
B-to-ADataInputsorA-to-B3-StateOutputs
xBx
24
GND
25
26
27
GND
(1,2)
FUNCTION TABLE (EACH 8-BIT SECTION)
2CEBA
2LEBA
2CEAB
2LEAB
2OEAB
Inputs
Outputs
xCEAB
xLEAB
xOEAB
xAx
xBx
28
2OEBA
H
X
L
X
X
H
L
X
H
L
X
X
X
L
Z
Z
B(3)
SSOP/ TSSOP/ TVSOP
TOP VIEW
L
L
L
L
L
L
H
H
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2. A-to-B data flow is shown. B-to-A data flow is similar but uses CEBA, LEBA, and OEBA.
3. Output level before the indicated steady-state input conditions were established.
2
IDT74LVC16543A
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
µA
IOZH
IOZL
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
±50
µA
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
3.6 ≤ VIN ≤ 5.5V(2)
—
—
—
—
10
500
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2.2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74LVC16543A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
PowerDissipationCapacitanceperTransceiverOutputsenabled
PowerDissipationCapacitanceperTransceiverOutputsdisabled
CL = 0pF, f = 10Mhz
44
4
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
Max.
VCC = 3.3V ± 0.3V
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tSU
Parameter
Min.
Min.
Max.
Unit
PropagationDelay
—
6.1
1.2
5.4
ns
ns
ns
ns
ns
ns
xAx to xBx or xBx to xAx
PropagationDelay
—
—
—
—
—
7.4
7.9
7.6
7.1
6.9
1.5
1.2
1
6.1
6.6
6.3
6.6
6.3
xLEBA or xLEAB to xAx or xBx
OutputEnableTime
xCEBA or xCEAB to xAx or xBx
OutputEnableTime
xOEBA or xOEAB to xAx or xBx
OutputDisableTime
1.5
1.5
xCEBA or xCEAB to xAx or xBx
OutputDisableTime
xOEBA or xOEAB to xAx or xBx
Set-upTime,databeforeCE↑
Set-upTime, databeforeLE↑, CELOW
HoldTime, dataafterCE↑
Hold Time, data after LE↑, CE LOW
Pulse Duration, xLEBA or xLEAB, xCEBA or xCEAB LOW
OutputSkew(2)
1.1
1.1
1.9
1.9
3.3
—
—
—
—
—
—
—
1.1
1.1
1.9
1.9
3.3
—
—
—
ns
ns
ns
ns
ns
ps
tSU
tH
—
tH
—
tW
—
tSK(o)
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC16543A
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
tPHL
VLOAD
VIH
6
6
2 x Vcc
Vcc
tPLH
VOH
VT
VOL
OUTPUT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VT
Vcc / 2
150
V
tPHL
tPLH
VLZ
VHZ
CL
mV
mV
pF
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
150
30
LVC Link
VLOAD
Open
GND
Propagation Delay
VCC
DISABLE
ENABLE
VIH
VT
500Ω
CONTROL
INPUT
VIN
VOUT
0V
Pulse (1, 2)
tPZL
tPLZ
D.U.T.
Generator
VLOAD/2
VT
VLOAD/2
VOL+VLZ
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
500Ω
RT
CL
tPHZ
tPZH
VOH
VOH-VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
LVC Link
VT
0V
Test Circuit for All Outputs
0V
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
SWITCHPOSITION
DATA
INPUT
VT
0V
Test
Switch
VLOAD
GND
tSU
tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
Open Drain
Disable Low
Enable Low
tREM
ASYNCHRONOUS
CONTROL
Disable High
Enable High
SYNCHRONOUS
CONTROL
All Other Tests
Open
tSU
tH
LVC Link
VIH
VT
0V
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
VOH
LOW-HIGH-LOW
VT
VOL
VT
PULSE
OUTPUT 1
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
LVC Link
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC16543A
3.3VCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
X
XX
IDT
XXXX
XX
LVC
Device Type Package
Bus-Hold
Family
Temp. Range
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
16-Bit Registered Transceiver with 3-State Outputs,
5 Volt Tolerant I/O
543A
Double-Density with Resistors, ±24mA
16
Blank
74
No Bus-hold
-40°C to +85°C
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www.idt.com
6
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