IDT74LVC16952APVG8 [IDT]

Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56;


型号：	IDT74LVC16952APVG8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO56, 0.635 MM PITCH, SSOP-56 光电二极管
文件：	总6页 (文件大小：74K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVC16952A

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

IDT74LVC16952A

3.3V CMOS 16-BIT

REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS,

5 VOLT TOLERANT I/O

FEATURES:

DESCRIPTION:

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

This 16-bit registered transceiver is built using advanced dual metal

CMOStechnology. Thishigh-speed, lowpowerdeviceisorganizedastwo

independent 8-bit D-type registered transceivers with separate input and

output control for independent control of data flow in either direction. For

example, theA-to-BEnable(CEAB) mustbeLOW toenter datafromtheA

port.CLKABcontrolstheclockingfunction.WhenCLKABtogglesfromLOW-

to-HIGH, the data present on the A port will be clocked into the register.

OEABperformstheoutputenablefunctionontheBport. Dataflowfromthe

BporttoAportissimilarbutrequiresusingCEBA,CLKBA,andOEBAinputs.

Full16-bitoperationisachievedbytyingthe controlpinsoftheindependent

transceiverstogether.

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

• Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows

the use of this device as a translator in a mixed 3.3V/5V supply system.

The LVC16952A has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

1CEBA

2CEBA

1CLKBA

2CLKBA

1OEAB

2OEAB

1CEAB

2CEAB

1CLKAB

2CLKAB

1OEBA

2OEBA

1A1

2A1

1B1

2B1

TO SEVEN OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

MARCH 1999

DSC-4492/2

IDT74LVC16952A

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

1OEAB

CLKAB

1CEAB

1OEBA

°C

1CLKBA

IOUT

DC Output Current

CEBA

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

GND

1A1

GND

1B1

ICC

ISS

Continuous Current through each

VCC or GND

±100

1A2

V^CC

1B2

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

V^CC

1B3

1B4

1B5

1A3

1A4

1A5

GND

1B6

GND

1A6

1A7

1A8

1B7

PINDESCRIPTION

1B8

2A1

2A2

Pin Names

xOEAB

xOEBA

xCEAB

xCEBA

xCLKAB

xCLKBA

xAx

Description

2B1

2B2

A-to-B Output Enable Inputs (Active LOW)

B-to-A Output Enable Inputs (Active LOW)

A-to-B Clock Enable Inputs (Active LOW)

B-to-A Clock Enable Inputs (Active LOW)

A-to-B Clock Inputs

2A3

2B3

GND

2B4

2B5

2B6

2A5

2A6

V^CC

B-to-A Clock Inputs

A-to-BDataInputsorB-to-A3-StateOutputs

B-to-ADataInputsorA-to-B3-StateOutputs

xBx

V_CC

2B7

2A7

2A8

2B8

GND

2CEAB

CEBA

FUNCTIONTABLE^(1,2)

CLKAB

2OEAB

CLKBA

OEBA

Inputs

Outputs

xCEAB

xCLKAB

xOEAB

xAx

xBx

B⁽³⁾

SSOP/ TSSOP/ TVSOP

TOP VIEW

↑

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

NOTES:

Symbol

1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA,

and xOEBA.

2. H = HIGH Voltage Level

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

6.5

L = LOW Voltage Level

X = Don’t Care

Z = High Impedance

↑ = LOW-to-HIGH Transition

6.5

NOTE:

1. As applicable to the device type.

3. Output level of B before the indicated steady-state input conditions were established.

IDT74LVC16952A

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

3.6 ≤ VIN ≤ 5.5V⁽²⁾

—

500

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

IDT74LVC16952A

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperLatchOutputsenabled

PowerDissipationCapacitanceperLatchOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

Parameter

Min.

Max.

Unit

PropagationDelay

—

7.6

1.6

6.6

tPHL

xCLKAB, xCLKBA to xBx, xAx

tPZH

tPZL

tPHZ

tPLZ

tSU

OutputEnableTime

—

1.1

1.9

6.6

6.7

xOEBA, xOEAB to xAx, xBx

OutputDisableTime

7.1

xOEBA, xOEAB to xAx, xBx

Set-up Time, HIGH or LOW

3.4

0.5

1.8

1.1

—

2.8

0.5

1.4

1.9

—

xAx, xBx before xCLKAB↑, xCLKBA↑

Hold Time, HIGH or LOW

tSU

xAx, xBx after xCLKAB↑, xCLKBA↑

Set-up Time, HIGH or LOW

xCEAB, xCEBA before xCLKAB↑, xCLKBA↑

Hold Time, HIGH or LOW

xCEAB, xCEBA after xCLKAB↑, xCLKBA↑

xLE Pulse Width HIGH or LOW, xCLKAB or xCLKBA

OutputSkew⁽²⁾

3.3

—

3.3

—

tSK(o)

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVC16952A

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

tPHL

VLOAD

VIH

2 x Vcc

Vcc

tPLH

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

tPHL

tPLH

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

VLOAD

Open

GND

Propagation Delay

VCC

DISABLE

ENABLE

VIH

500Ω

CONTROL

INPUT

VIN

VOUT

Pulse ^{(1, 2)}

tPZL

tPLZ

D.U.T.

Generator

VLOAD/2

V^OL+VLZ

VOL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

SWITCHPOSITION

DATA

INPUT

Test

Switch

V^LOAD

GND

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

ASYNCHRONOUS

CONTROL

Disable High

Enable High

SYNCHRONOUS

CONTROL

All Other Tests

Open

tSU

LVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

VOL

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVC16952A

3.3VCMOS16-BITREGISTEREDTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

Device Type Package

XXXX

IDT

LVC

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

16-Bit Registered Transceiver

952A

Double-Density, ±24mA

Blank No Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

for Tech Support:

logichelp@idt.com

(408) 654-6459

www.idt.com

IDT74LVC16952APVG8 [IDT]

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