IDT74LVC823AP [IDT]

Bus Driver, LVC/LCX/Z Series, 1-Func, 9-Bit, True Output, CMOS, PDSO24, TSSOP-24;


型号：	IDT74LVC823AP
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Driver, LVC/LCX/Z Series, 1-Func, 9-Bit, True Output, CMOS, PDSO24, TSSOP-24 驱动光电二极管逻辑集成电路
文件：	总6页 (文件大小：73K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVC823A

3.3VCMOS9-BITBUS-INTERFACEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 9-BIT

IDT74LVC823A

BUS-INTERFACE FLIP-FLOP

WITH 3-STATE OUTPUTS

AND 5 VOLT TOLERANT I/O

DESCRIPTION:

FEATURES:

The LVC823A9-bitbus-interface flip-flopis builtusingadvanceddual

metalCMOStechnology.TheLVC823Adeviceis designedspecificallyfor

drivinghighlycapacitive orrelativelylow-impedance loads.The device is

particularly suitable for implementing wider buffer registers, I/O ports,

bidirectionalbus drivers withparity, andworkingregisters.

• 0.5 MICRON CMOS Technology

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4μ W typ. static)

• Rail-to-rail output swing for increased noise margin

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

Withtheclock-enable(CLKEN)inputlow,thenineD-typeedge-triggered

flip-flopsenterdataonthelow-to-hightransitionsoftheclock.TakingCLKEN

high disables the clock buffer, latching the outputs. This device has

noninvertingdata (D)inputs.Takingthe clear(CLR)inputlowcauses the

nine Qoutputs togolow,independentlyofthe clock.

• Available in TSSOP package

Abufferedoutput-enable(OE)inputcanbeusedtoplacethenineoutputs

ineitheranormallogicstate(highorlowlogiclevels)orahigh-impedance

state.OEdoes notaffectinternaloperations ofthelatch.Previouslystored

data can be retained or new data can be entered while the outputs are in

thehigh-impedancestate.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

The LVC823A has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

To ensure the high-impedance state during power up or power down,

OE shouldbe tiedtoVCC througha pullupresistor;the minimumvalue of

the resistoris determinedbythe current-sinkingcapabilityofthe driver.

Inputs canbe drivenfromeither3.3Vor5Vdevices.This feature allows

theuseofthisdeviceasatranslatorinamixed3.3V/5Vsystemenvironment.

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

FUNCTIONALBLOCKDIAGRAM

CLR

CLKEN

CLK

¹Q

¹D

TO EIGHT OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JANUARY 2004

2004 Integrated Device Technology, Inc.

DSC-4608/4

IDT74LVC823A

3.3VCMOS9-BITBUS-INTERFACEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

° C

IOUT

DC Output Current

V^CC

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

ICC

ISS

Continuous Current through each

VCC or GND

±100

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

5.5

6.5

NOTE:

1. As applicable to the device type.

CLKEN

CLR

CLK

GND

PINDESCRIPTION

Pin Names

Description

CLK

CLKEN

CLR

OutputEnableInput(ActiveLOW)

ClockInput

TSSOP

TOP VIEW

Clock Enable Input (Active LOW)

Clear Input (Active LOW)

DataInputs

DataOutputs

(1)

FUNCTION TABLE (EACH FLIP-FLOP)

Inputs

Outputs

CLR

CLKEN

CLK

↑

(2)

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High Impedance

↑ = LOW-to-HIGH transition

2. Output level before indicated steady-state input conditions were established.

IDT74LVC823A

3.3VCMOS9-BITBUS-INTERFACEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

µA

µ A

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

µ A

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

(2)

3.6 ≤ VIN ≤ 5.5V

—

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

500

µ A

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

2.2

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

IDT74LVC823A

3.3VCMOS9-BITBUS-INTERFACEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperFlip-FlopOutputsenabled

PowerDissipationCapacitanceperFlip-FlopOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

Parameter

Min.

150

—

Max.

—

Min.

150

1.4

Max.

—

Unit

MHz

fMAX

tPLH

tPHL

PropagationDelay

CLK to xQ

8.9

PropagationDelay

CLR to xQ

—

8.8

8.3

7.1

2.5

1.6

1.1

7.9

7.2

tPZH

tPZL

OutputEnableTime

OE to xQ

tPHZ

tPLZ

OutputDisableTime

OE to xQ

PulseDuration, CLRLOW

3.3

—

3.3

—

tSU

Pulse Duration, CLK HIGH or LOW

Set-upTime,CLRinactivebeforeCLK↑

Set-upTime,databeforeCLK↑

1.3

1.8

1.3

1.8

Set-up Time, CLKEN LOW before CLK↑

HoldTime,dataafterCLK↑

Hold Time, CLKEN LOW after CLK↑

1.3

—

1.3

—

(2)

tSK(o)

OutputSkew

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVC823A

3.3VCMOS9-BITBUS-INTERFACEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

(1)

(2)

tPHL

Symbol VCC =3.3V±0.3V VCC =2.7V VCC =2.5V±0.2V Unit

tPLH

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

VIH

OPPOSITE PHASE

INPUT TRANSITION

VLZ

VHZ

150

LVC Link

Propagation Delay

VLOAD

Open

GND

VCC

DISABLE

ENABLE

VIH

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

(1, 2)

Pulse

D.U.T.

VLOAD/2

Generator

OUTPUT

NORMALLY

LOW

SWITCH

VLOAD

V^OL+VLZ

VOL

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

GND

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

DATA

INPUT

SWITCHPOSITION

Test

Switch

V^LOAD

GND

Open

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

VIH

ASYNCHRONOUS

CONTROL

Disable High

Enable High

VIH

SYNCHRONOUS

CONTROL

All Other Tests

tSU

VIH

LVC Link

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

VOL

LOW-HIGH-LOW

OUTPUT 1

PULSE

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVC823A

3.3VCMOS9-BITBUS-INTERFACEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

LVC

XXXX

Bus-Hold

Temp. Range

Device Type Package

Thin Shrink Small Outline Package

823A

9-Bit Bus-Interface Flip-Flop with 3-State Outputs, 24mA

Blank No Bus-hold

–40°C to +85°C

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

logichelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

IDT74LVC823AP [IDT]

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