IDT74LVCH162374APF8 [IDT]

Bus Driver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TVSOP-48;


型号：	IDT74LVCH162374APF8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Driver, LVC/LCX/Z Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TVSOP-48 驱动光电二极管逻辑集成电路电视
文件：	总6页 (文件大小：67K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH162374A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

3.3V CMOS 16-BIT

IDT74LVCH162374A

EDGE TRIGGERED D-TYPE FLIP-

FLOP WITH 3-STATE OUTPUTS,

5 VOLT TOLERANT I/O, BUS-HOLD

FEATURES:

DESCRIPTION:

• Typical tSK(o) (Output Skew) < 250ps

The LVCH162374A 16-bit edge-triggered D-type flip-flop is built using

advanced dual metal CMOS technology. This high-speed, low-power

storage. The output enable (OE) and clock (CLK) controls are organized

to operate each device as two 8-bit registers or one 16-bit register with

commonclock. Flow-throughorganizationofsignalpinssimplifieslayout.

All inputs are designed with hysteresis for improved noise margin.

All pins of the LVCH162374A can be driven from either 3.3V or 5V

devices. Thisfeatureallowstheuseofthisdeviceasatranslatorinamixed

3.3V/5V supply system.

The LVCH162374A has series resistors in the device output structure

which will significantly reduce line noise when used with light loads. This

driver has been developed to drive ±12mA at the designated thresholds.

The LVCH162374A has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputs

and eliminates the need for pull-up/down resistors.

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4µ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEATURES:

• Balanced Output Drivers: ±12mA

• Low switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONALBLOCKDIAGRAM

2OE

1OE

2CLK

1CLK

2D1

1D1

2Q1

1Q1

TO SEVEN OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

AUGUST 1999

DSC-4678/1

IDT74LVCH162374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

°C

1CLK

1D1

1OE

1Q1

1Q2

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

1D2

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

1D3

GND

1Q3

1Q4

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1D4

VCC

1D5

VCC

1Q5

1D6

1Q6

GND

CAPACITANCE (TA = +25°C, F = 1.0MHz)

1D7

1D8

2D1

1Q7

1Q8

2Q1

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

6.5

2D2

6.5

2Q2

NOTE:

GND

1. As applicable to the device type.

2D3

2D4

VCC

2D5

2D6

GND

2D7

2D8

2CLK

2Q3

2Q4

VCC

2Q5

2Q6

GND

2Q7

2Q8

2OE

PINDESCRIPTION

Pin Names

Description

xDx

xCLK

xQx

Data Inputs⁽¹⁾

Clock Inputs

3-State Outputs

xOE

3-State Output Enable Inputs (Active LOW)

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

(1)

FUNCTION TABLE (EACH FLIP-FLOP)

Inputs

Outputs

xQx

SSOP/ TSSOP/ TVSOP

TOP VIEW

xOE

xCLK

xDx

↑

Q⁽²⁾

H or L

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

2. Output level before the indicated steady-state input conditions were established.

IDT74LVCH162374A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

±5

µA

IOZH

IOZL

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

±10

IOFF

VIK

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

±50

µA

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

3.6 ≤ VIN ≤ 5.5V⁽²⁾

—

500

∆ICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

µA

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µA

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-Hold Input Overdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µA

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74LVCH162374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

Max.

—

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 4mA

IOH = – 6mA

IOH = – 4mA

IOH = – 8mA

IOH = – 6mA

IOH = – 12mA

IOL = 0.1mA

IOL = 4mA

VCC – 0.2

VCC = 2.3V

VCC = 2.7V

VCC = 3V

1.9

1.7

2.2

—

2.4

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.55

0.4

0.6

0.55

0.8

IOL = 6mA

VCC = 2.7V

VCC = 3V

IOL = 4mA

IOL = 8mA

IOL = 6mA

IOL = 12mA

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

—

Unit

CPD

PowerDissipationCapacitanceperFlip-FlopOutputsenabled

PowerDissipationCapacitanceperFlip-FlopOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Parameter

Min.

Max.

Unit

PropagationDelay

6.5

6.2

xCLK to xQx

OutputEnableTime

1.5

6.3

6.2

1.5

6.1

xOE to xQx

OutputDisableTime

xOE to xQx

Set-up Time HIGH or LOW, xDx before xCLK

Hold Time HIGH or LOW, xDx after xCLK

xCLK Pulse Width HIGH or LOW

OutputSkew⁽²⁾

2.5

1.5

—

2.5

1.5

—

tSK(o)

—

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH162374A

INDUSTRIALTEMPERATURERANGE

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

Symbol VCC⁽¹⁾=3.3V±0.3V VCC⁽¹⁾=2.7V VCC⁽²⁾=2.5V±0.2V

Unit

tPHL

VLOAD

VIH

2 x Vcc

Vcc

tPLH

VOH

VOL

OUTPUT

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

tPHL

tPLH

VLZ

VHZ

VIH

OPPOSITE PHASE

INPUT TRANSITION

150

LVC Link

VLOAD

Open

GND

Propagation Delay

VCC

DISABLE

ENABLE

VIH

500Ω

CONTROL

INPUT

VIN

VOUT

Pulse ^{(1, 2)}

tPZL

tPLZ

D.U.T.

Generator

VLOAD/2

V^OL+VLZ

VOL

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

tPHZ

tPZH

VOH

VOH-VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

LVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

SWITCHPOSITION

DATA

INPUT

Test

Switch

V^LOAD

GND

t^SU

VIH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

tREM

ASYNCHRONOUS

CONTROL

Disable High

Enable High

SYNCHRONOUS

CONTROL

All Other Tests

Open

tSU

LVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

LOW-HIGH-LOW

VOL

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

LVC Link

tPLH2

tPHL2

Pulse Width

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH162374A

3.3VCMOS16-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

XXXX

LVC

IDT

Device Type Package

Temp. Range

Bus-Hold

Family

Shrink Small Outline Package

Thin Shrink Small Outline Package

Thin Very Small Outline Package

16-Bit Edge Triggered D-Type Flip-Flop

374A

Double-Density with Resistors, ±12mA

162

Bus-hold

-40°C to +85°C

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