IDT74LVCH16501APF8 [IDT]
Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TVSOP-56;
| 型号： | IDT74LVCH16501APF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, TVSOP-56 光电二极管 输出元件 逻辑集成电路 电视 |
| 文件： | 总7页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 18-BIT
IDT74LVCH16501A
REGISTERED BUS TRANSCEIVER
WITH 5V TOLERANT I/O
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
This 18-bit registered transceiver is built using advanced dual metal
CMOS technology. This high-speed, low power 18-bit registered bus
transceivercombinesD-typelatchesandD-typeflip-flopstoallowdataflow
in transparent latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable (LEAB and
LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in transparent mode when LEAB is high. When LEAB is
low,theAdataislatchedifCLKABisheldatahighorlowlogiclevel. IfLEAB
islow,theAbusdataisstoredinthelatch/flip-floponthelow-to-hightransition
of CLKAB. OEAB performs the output enable function on the B port. Data
flow from B port to A port is similar but requires using OEBA, LEBA and
CLKBA.Flow-throughorganizationofsignalpinssimplifieslayout.Allinputs
are designed with hysteresis for improved noise margin.
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
TheLVCH16501Ahasbeendesignedwitha ±24mAoutputdriver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
The LVCH16501A has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
1
OEAB
30
CLKBA
28
LEBA
27
OEBA
55
CLKAB
2
LEAB
C
C
D
54
3
B1
A1
D
C
D
C
D
TO 17 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-3688/1
IDT74LVCH16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERWITH5VOLTI/O
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
1
2
56
55
54
53
52
OEAB
LEAB
A1
GND
CLKAB
B1
°C
mA
mA
IOUT
DC Output Current
3
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
4
5
6
GND
A2
GND
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
B2
B3
A3
VCC
A4
51
50
49
48
NOTE:
7
VCC
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8
B4
B5
9
A5
10
47
46
45
44
B6
A6
11
12
13
14
15
16
17
18
GND
GND
A7
B7
B8
A8
A9
43
42
B9
B10
A10
A11
A12
CAPACITANCE (TA = +25°C, F = 1.0MHz)
41
B11
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
40
39
38
B12
GND
B13
B14
B15
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
GND
A13
COUT
CI/O
6.5
19
20
21
22
23
6.5
37
36
35
34
A14
NOTE:
1. As applicable to the device type.
A15
VCC
A16
VCC
B16
24
25
26
27
33
32
B17
A17
GND
GND
31
30
29
FUNCTIONTABLE(1,2)
B18
A18
OEBA
LEBA
CLKBA
GND
Inputs
Output
28
OEAB
LEAB
CLKAB
Ax
Bx
Z
L
H
H
H
H
H
H
X
H
H
L
X
X
X
↑
↑
L
X
L
SSOP/ TSSOP/ TVSOP
TOP VIEW
L
H
L
H
L
PINDESCRIPTION
L
H
X
X
H
Pin Names
Description
L
B(3)
B(4)
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
A-to-B Output Enable Input
L
H
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, and
CLKBA.
2. H = HIGH Voltage Level
B-to-A Latch Enable Input
A-to-B Clock Input
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
Bx
3. Output level before the indicated steady-state input conditions were established.
4. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74LVCH16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERWITH5VOLTI/O
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
µA
IOZH
IOZL
IOFF
VIK
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
±50
µA
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
VH
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
3.6 ≤ VIN ≤ 5.5V(2)
—
—
—
—
10
500
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
µA
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
—
—
—
µA
µA
IBHL
VI = 0.7V
—
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74LVCH16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERWITH5VOLTI/O
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
2
1.7
2.2
2.4
2
—
—
—
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
PowerDissipationCapacitanceperTransceiverOutputsenabled
PowerDissipationCapacitanceperTransceiverOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
4
IDT74LVCH16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERWITH5VOLTI/O
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
Min.
Max.
Min.
Max.
Unit
PropagationDelay
1.5
5.2
1.5
4.6
ns
Ax to Bx or Bx to Ax
PropagationDelay
1.5
1.5
1.5
1.5
3
6
6
1.5
1.5
1.5
1.5
3
5.3
5.3
5.6
5.8
—
ns
ns
ns
ns
ns
ns
ns
ns
LEBA to Ax, LEAB to Bx
PropagationDelay
CLKBA to Ax, CLKAB to Bx
OutputEnableTime
6
OEBA to Ax, OEAB to Bx
OutputDisableTime
6.5
—
—
OEBA to Ax, OEAB to Bx
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Set-up Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
Pulse Width HIGH, LEAB or LEBA
tH
tSU
tH
0
0
—
CLK LOW
3
2
—
—
—
3
2
—
—
—
CLK HIGH
1.5
1.5
tW
tW
3
3
—
—
—
3
3
—
—
ns
ns
ps
Pulse Width HIGH or LOW, CLKAB or CLKBA
OutputSkew(2)
tSK(o)
—
—
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2
Skew between any two outputs of the same package and switching in the same direction.
5
IDT74LVCH16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERWITH5VOLTI/O
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VT
Vcc / 2
150
V
VLZ
VHZ
CL
mV
mV
pF
LVC Link
150
Propagation Delay
30
DISABLE
ENABLE
VLOAD
Open
GND
VIH
VT
VCC
CONTROL
INPUT
0V
tPZL
tPLZ
500Ω
VIN
VLOAD/2
VT
VOUT
VLOAD/2
OUTPUT
NORMALLY
LOW
(1, 2)
Pulse
SWITCH
CLOSED
D.U.T.
VLZ
VOL
Generator
tPHZ
tPZH
500Ω
RT
VOH
VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
CL
VT
0V
0V
LVC Link
LVC Link
Test Circuit for All Outputs
Enable and Disable Times
NOTE:
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
VIH
DATA
INPUT
VT
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
0V
tSU
tH
SWITCHPOSITION
VIH
VT
0V
TIMING
INPUT
Test
Switch
VLOAD
GND
tREM
VIH
Open Drain
Disable Low
Enable Low
ASYNCHRONOUS
CONTROL
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
LVC Link
All Other Tests
Open
Set-up, Hold, and Release Times
VIH
VT
LOW-HIGH-LOW
INPUT
0V
tPLH1
tPHL1
VT
PULSE
VOH
VT
tW
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
HIGH-LOW-HIGH
PULSE
tSK (x)
VT
VOH
VT
VOL
LVC Link
Pulse Width
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74LVCH16501A
3.3VCMOS18-BITREGISTEREDTRANSCEIVERWITH5VOLTI/O
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
LVC
XX
Device Type Package
X
XX
XXXX
XX
Temp. Range
Bus-Hold
Family
PV
PA
PF
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
18-bit Registered Transceiver
501A
16
Double-Density, ±24mA
H
Bus-hold
-40°C to +85°C
74
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7
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