IDT74LVCH16601APVG8 [IDT]

Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, GREEN, SSOP-56;


型号：	IDT74LVCH16601APVG8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Registered Bus Transceiver, LVC/LCX/Z Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, GREEN, SSOP-56 光电二极管输出元件逻辑集成电路
文件：	总7页 (文件大小：101K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 18-BIT

IDT74LVCH16601A

UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS,

5 VOLT TOLERANT I/O, BUS-HOLD

FEATURES:

DESCRIPTION:

• Typical tSK(o) (Output Skew) < 250ps

The LVCH16601A 18-bit universal bus transceiver is built using ad-

vanceddualmetalCMOStechnology.TheLVCH16601AcombinesD-type

latches andD-type flip-flops toallowdata flowintransparent,latchedand

clockedmodes.

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4μ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

Data flow in each direction is controlled by output-enable (OEAB and

OEBA),latched-enable(LEABandLEBA),andclock(CLKABandCLKBA)

inputs. The clock can be controlled by the clock-enable (CLKENAB and

CLKENBA)inputs.

ForA-to-Bdata flow,the device operates inthe transparentmode when

LEABis high. WhenLEABis low, the Adata is latchedifCLKABis heldat

a highorlowlogiclevel.IfLEABis low,the A-bus data is storedinthe latch/

flip-floponthelow-to-hightransitionofCLKAB.OutputenableOEABisactive

low. When OEAB is low, the outputs are active. When OEAB is high, the

outputsareinthehigh-impedancestate. DataflowforBtoAissimilartothat

of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.

• Available in SSOP package

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

Allpins canbedrivenfromeither3.3Vor5Vdevices. This featureallows

the use of this device as a translator in a mixed 3.3V/5V supply system.

The LVCH16601Ahas beendesignedwitha ±24mAoutputdriver.This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

The LVCH16601A has “bus-hold” which retains the inputs’ last state

whenevertheinputgoes toahighimpedance.This prevents floatinginputs

andeliminates the needforpull-up/downresistors.

FUNCTIONALBLOCKDIAGRAM

OEAB

CLKENAB

CLKAB

LEAB

LEBA

CLKBA

CLKENBA

OEBA

CLK

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

TO 17 OTHER CHANNELS

INDUSTRIAL TEMPERATURE RANGE

OCTOBER 2008

DSC-4074/5

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

° C

OEAB

LEAB

CLKENAB

CLKAB

IOUT

DC Output Current

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

ICC

ISS

Continuous Current through each

VCC or GND

±100

GND

A²

GND

B²

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

VCC

A⁶

PINDESCRIPTION

Pin Names

OEAB

OEBA

LEAB

Description

A-to-B Output Enable Input (Active LOW)

B-to-AOutputEnable Input(Active LOW)

A-to-BLatchEnableInput

GND

LEBA

B-to-ALatchEnableInput

CLKAB

CLKBA

A-to-B Clock Input

A10

A11

B10

B11

B-to-A Clock Input

A-to-BDataInputsorB-to-A3-StateOutputs⁽¹⁾

B-to-ADataInputsorA-to-B3-StateOutputs⁽¹⁾

A-to-B Clock Enable Input (Active LOW)

A12

GND

A¹³

B12

GND

B13

CLKENAB

CLKENBA

B-to-A Clock Enable Input (Active LOW)

A14

A15

B14

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

B¹⁵

VCC

B16

FUNCTIONTABLE^(1,2)

VCC

A16

Inputs

Outputs

A17

CLKENAB

OEAB

LEAB

CLKAB

B17

↑

GND

B¹⁸

A¹⁸

CLKBA

OEBA

LEBA

(3)

CLKENBA

↑

(3)

SSOP

TOP VIEW

(4)

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

↑ = LOW-to-HIGH transition

2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA,

and CLKENBA.

3. Output level before the indicated steady-state input conditions were established.

4. Output level before the indicated steady-state input conditions were established,

provided that CLKAB was HIGH before LEAB went LOW.

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

6.5

NOTE:

1. As applicable to the device type.

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

µA

µ A

IOZH

IOZL

IOFF

VIK

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

µ A

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

(2)

3.6 ≤ VIN ≤ 5.5V

—

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

500

µ A

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µ A

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-HoldInputOverdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µ A

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperTransceiverOutputsenabled

PowerDissipationCapacitanceperTransceiverOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Parameter

Min.

Max.

Unit

PropagationDelay

—

5.4

6.2

6.3

6.8

—

4.6

Ax to Bx or Bx to Ax

PropagationDelay

—

1.5

0.8

—

1.5

0.8

5.2

5.3

5.6

5.2

—

LEBA to Ax, LEAB to Bx

PropagationDelay

CLKBA to Ax, CLKAB to Bx

OutputEnableTime

OEBA to Ax, OEAB to Bx

OutputDisableTime

OEBA to Ax, OEAB to Bx

Set-up Time HIGH or LOW

Ax to CLKAB, Bx to CLKBA

Hold Time HIGH or LOW

Ax to CLKAB, Bx to CLKBA

Set-up Time HIGH or LOW

Ax to LEAB, Bx to LEBA

Set-up Time, CLKENAB to CLKAB

Set-up Time, CLKENBA to CLKBA

Hold Time HIGH or LOW

Ax after LEAB, Bx after LEBA

Hold Time, CLKENAB after CLKAB

Hold Time, CLKENBA after CLKBA

LEAB or LEBA Pulse Width HIGH

—

tSU

Clock LOW

Clock HIGH

—

tSU

2.1

1.8

2.1

1.8

0.5

—

0.5

—

500

CLKAB or CLKBA Pulse Width HIGH or LOW

(2)

tSK(o)

OutputSkew

—

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

tPHL

tPLH

(1)

(2)

Symbol VCC =3.3V±0.3V VCC =2.7V VCC =2.5V±0.2V Unit

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

VIH

OPPOSITE PHASE

INPUT TRANSITION

Vcc / 2

150

VLZ

VHZ

LVC Link

150

Propagation Delay

DISABLE

ENABLE

VLOAD

Open

GND

VIH

VCC

CONTROL

INPUT

tPZL

tPLZ

500Ω

VIN

VLOAD/2

VOUT

VLOAD/2

OUTPUT

NORMALLY

LOW

(1, 2)

Pulse

SWITCH

CLOSED

D.U.T.

VLZ

VOL

Generator

tPHZ

tPZH

500Ω

VOH

VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

Enable and Disable Times

NOTE:

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

DATA

INPUT

tSU

SWITCHPOSITION

VIH

TIMING

INPUT

Test

Switch

V^LOAD

GND

Open

tREM

VIH

Open Drain

Disable Low

Enable Low

ASYNCHRONOUS

CONTROL

VIH

SYNCHRONOUS

CONTROL

Disable High

Enable High

tSU

LVC Link

All Other Tests

Set-up, Hold, and Release Times

VIH

LOW-HIGH-LOW

INPUT

tPLH1

tPHL1

PULSE

VOH

OUTPUT 1

OUTPUT 2

VOL

tSK (x)

HIGH-LOW-HIGH

PULSE

tSK (x)

VOH

VOL

LVC Link

Pulse Width

tPLH2

tPHL2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH16601A

3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVER

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

LVC

XXXX

Device Type Package

Bus-Hold

Family

Temp. Range

Shrink Small Outline Package

SSOP - Green

PVG

18-Bit Universal Bus Transceiver with 3-State Outputs

601A

Double-Density, 24mA

Bus-hold

-40°C to +85°C

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www.idt.com

IDT74LVCH16601APVG8 [IDT]

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