IDT74LVCR16952APA [IDT]

3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O; 具有三态输出和5V兼容我的3.3V CMOS 16位寄存收发器/ O
IDT74LVCR16952APA
型号: IDT74LVCR16952APA
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
具有三态输出和5V兼容我的3.3V CMOS 16位寄存收发器/ O

总线驱动器 总线收发器 触发器 逻辑集成电路 光电二极管 输出元件
文件: 总6页 (文件大小:77K)
中文:  中文翻译
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IDT74LVCR16952A  
3.3V CMOS 16-BIT  
REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
AND 5 VOLT TOLERANT I/O  
DESCRIPTION:  
FEATURES:  
This 16-bit registered transceiver is built using advanced dual metal  
CMOStechnology. Thishigh-speed, lowpowerdeviceisorganizedastwo  
independent 8-bit D-type registered transceivers with separate input and  
output control for independent control of data flow in either direction. For  
example, theA-to-BEnable(CEAB) mustbeLOW toenter datafromtheA  
port.CLKABcontrolstheclockingfunction. WhenCLKABtogglesfromLOW-  
to-HIGH, the data present on the A port will be clocked into the register.  
OEABperformstheoutputenablefunctionontheBport. Dataflowfromthe  
BporttoAportissimilarbutrequiresusingCEBA,CLKBA,andOEBAinputs.  
Full16-bitoperationisachievedbytyingthecontrolpinsoftheindependent  
transceiverstogether.  
• Typical tSK(o) (Output Skew) < 250ps  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ± 0.3V, Normal Range  
• VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µ W typ. static)  
• All inputs, outputs, and I/O are 5V tolerant  
• Supports hot insertion  
• Available in TSSOP package  
DRIVE FEATURES:  
• Balanced Output Drivers: ±12mA  
• Low switching noise  
Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows  
the use of this device as a translator in a mixed 3.3V/5V supply system.  
The LVCR162952A has series resistors in the device output structure  
which will significantly reduce line noise when used with light loads.This  
driver has been developed to drive ±12mA at the designated threshold  
levels.  
APPLICATIONS:  
• 5V and 3.3V mixed voltage systems  
• Data communication and telecommunication systems  
FUNCTIONALBLOCKDIAGRAM  
54  
31  
1CEBA  
2CEBA  
55  
30  
1CLKBA  
2CLKBA  
28  
1
1OEAB  
2OEAB  
3
26  
1CEAB  
2CEAB  
27  
2
1CLKAB  
2CLKAB  
29  
56  
1OEBA  
2OEBA  
C
CE  
D
C
CE  
D
15  
5
1A1  
2A1  
52  
42  
1B1  
2B1  
C
C
CE  
CE  
D
D
TO SEVEN OTHER CHANNELS  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JANUARY 2004  
1
© 2004 Integrated Device Technology, Inc.  
DSC-4484/2  
IDT74LVCR16952A  
3.3VCMOS16-BITREGISTEREDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
ABSOLUTEMAXIMUMRATINGS(1)  
PINCONFIGURATION  
Symbol  
VTERM  
TSTG  
Description  
Terminal Voltage with Respect to GND  
Storage Temperature  
Max  
Unit  
V
–0.5 to +6.5  
–65 to +150  
–50 to +50  
–50  
1
2
3
56  
55  
54  
53  
52  
1 OEAB  
1CLKAB  
1OEBA  
°C  
mA  
mA  
IOUT  
DC Output Current  
1
CLKBA  
CEBA  
IIK  
IOK  
Continuous Clamp Current,  
VI < 0 or VO < 0  
1
CEAB  
GND  
1A1  
1
4
5
6
GND  
1B1  
ICC  
ISS  
Continuous Current through each  
VCC or GND  
±100  
mA  
51  
50  
49  
48  
NOTE:  
1A2  
VCC  
1B2  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
7
VCC  
1B3  
1B4  
1B5  
8
1A3  
1A4  
1A5  
9
10  
47  
46  
45  
44  
11  
12  
13  
14  
15  
16  
17  
18  
GND  
1B6  
GND  
1A6  
1A7  
1A8  
1B7  
PINDESCRIPTION  
43  
42  
1B8  
Pin Names  
xOEAB  
xOEBA  
xCEAB  
xCEBA  
xCLKAB  
xCLKBA  
xAx  
Description  
2A1  
2A2  
2B1  
2B2  
A-to-B Output Enable Inputs (Active LOW)  
B-to-A Output Enable Inputs (Active LOW)  
A-to-B Clock Enable Inputs (Active LOW)  
B-to-A Clock Enable Inputs (Active LOW)  
A-to-B Clock Inputs  
41  
40  
39  
38  
2A3  
2B3  
GND  
2B4  
GND  
2A4  
2A5  
2A6  
VCC  
19  
20  
21  
22  
23  
37  
36  
35  
34  
2B5  
B-to-A Clock Inputs  
A-to-BDataInputsorB-to-A3-StateOutputs  
B-to-ADataInputsorA-to-B3-StateOutputs  
2
B6  
xBx  
VCC  
2B7  
2A7  
24  
25  
26  
27  
33  
32  
31  
2A8  
2B8  
GND  
GND  
2CEAB  
2
CEBA  
2
FUNCTIONTABLE(1,2)  
CLKAB  
30  
29  
2
CLKBA  
28  
Inputs  
Outputs  
2
OEAB  
2
OEBA  
xCEAB  
xCLKAB  
xOEAB  
xAx  
X
xBx  
B(3)  
B(3)  
L
H
X
L
X
L
L
L
TSSOP  
TOP VIEW  
X
X
L
L
L
L
H
H
X
H
X
Z
CAPACITANCE (TA = +25°C, F = 1.0MHz)  
Parameter(1)  
Conditions  
VIN = 0V  
VOUT = 0V  
VIN = 0V  
Typ.  
Max. Unit  
NOTES:  
Symbol  
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA,  
and xOEBA.  
2. H = HIGH Voltage Level  
CIN  
Input Capacitance  
Output Capacitance  
I/O Port Capacitance  
4.5  
6
8
8
pF  
pF  
pF  
COUT  
CI/O  
6.5  
L = LOW Voltage Level  
X = Don’t Care  
Z = High Impedance  
= LOW-to-HIGH Transition  
6.5  
NOTE:  
1. As applicable to the device type.  
3. Output level of B before the indicated steady-state input conditions were established.  
2
IDT74LVCR16952A  
3.3VCMOS16-BITREGISTEREDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
FollowingConditionsApplyUnlessOtherwiseSpecified:  
Operating Condition: TA = –40°C to +85°C  
Symbol  
Parameter  
Test Conditions  
Min.  
1.7  
2
Typ.(1)  
Max.  
Unit  
VIH  
Input HIGH Voltage Level  
VCC = 2.3V to 2.7V  
VCC = 2.7V to 3.6V  
V
VIL  
Input LOW Voltage Level  
Input Leakage Current  
VCC = 2.3V to 2.7V  
VCC = 2.7V to 3.6V  
0.7  
0.8  
V
IIH  
IIL  
VCC = 3.6V  
VI = 0 to 5.5V  
±5  
µA  
µA  
IOZH  
IOZL  
High Impedance Output Current  
(3-State Output pins)  
VCC = 3.6V  
VO = 0 to 5.5V  
±10  
IOFF  
VIK  
VH  
Input/Output Power Off Leakage  
Clamp Diode Voltage  
VCC = 0V, VIN or VO 5.5V  
±50  
µA  
V
VCC = 2.3V, IIN = –18mA  
–0.7  
–1.2  
Input Hysteresis  
VCC = 3.3V  
VCC = 3.6V  
100  
10  
mV  
µA  
ICCL  
ICCH  
ICCZ  
Quiescent Power Supply Current  
VIN = GND or VCC  
3.6 VIN 5.5V(2)  
10  
500  
ICC  
Quiescent Power Supply Current  
Variation  
One input at VCC - 0.6V, other inputs at VCC or GND  
µA  
NOTES:  
1. Typical values are at VCC = 3.3V, +25°C ambient.  
2. This applies in the disabled state only.  
OUTPUTDRIVECHARACTERISTICS  
Symbol  
Parameter  
TestConditions(1)  
VCC = 2.3V to 3.6V  
Min.  
Max.  
Unit  
V
VOH  
Output HIGH Voltage  
IOH = – 0.1mA  
IOH = – 4mA  
IOH = – 6mA  
IOH = – 4mA  
IOH = – 8mA  
IOH = – 6mA  
IOH = – 12mA  
IOL = 0.1mA  
IOL = 4mA  
VCC – 0.2  
VCC = 2.3V  
VCC = 2.7V  
VCC = 3V  
1.9  
1.7  
2.2  
2
2.4  
2
VOL  
OutputLOWVoltage  
VCC = 2.3V to 3.6V  
VCC = 2.3V  
0.2  
0.4  
0.55  
0.4  
0.6  
0.55  
0.8  
V
IOL = 6mA  
VCC = 2.7V  
VCC = 3V  
IOL = 4mA  
IOL = 8mA  
IOL = 6mA  
IOL = 12mA  
NOTE:  
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.  
TA = – 40°C to + 85°C.  
3
IDT74LVCR16952A  
3.3VCMOS16-BITREGISTEREDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C  
Symbol  
Parameter  
Test Conditions  
Typical  
Unit  
CPD  
PowerDissipationCapacitanceperTransceiverOutputsenabled  
PowerDissipationCapacitanceperTransceiverOutputsdisabled  
CL = 0pF, f = 10Mhz  
pF  
CPD  
SWITCHINGCHARACTERISTICS(1)  
VCC = 2.7V  
Max.  
VCC = 3.3V ± 0.3V  
Symbol  
tPLH  
Parameter  
Min.  
Min.  
Max.  
Unit  
PropagationDelay  
2
7.6  
2
6.6  
ns  
ns  
ns  
tPHL  
xCLKAB, xCLKBA to xBx, xAx  
tPZH  
tPZL  
tPHZ  
tPLZ  
tSU  
OutputEnableTime  
1.5  
1.5  
8
1.5  
1.5  
7
xOEBA, xOEAB to xAx, xBx  
OutputDisableTime  
7.5  
6.5  
xOEBA, xOEAB to xAx, xBx  
Set-up Time, HIGH or LOW  
2.5  
1.5  
1.8  
2
2.5  
1.5  
1.4  
2
ns  
ns  
ns  
ns  
xAx, xBx before xCLKAB, xCLKBA↑  
Hold Time, HIGH or LOW  
tH  
tSU  
tH  
xAx, xBx after xCLKAB, xCLKBA↑  
Set-up Time, HIGH or LOW  
xCEAB, xCEBA before xCLKAB, xCLKBA↑  
Hold Time, HIGH or LOW  
xCEAB, xCEBA after xCLKAB, xCLKBA↑  
Pulse Width HIGH or LOW, xCLKAB or xCLKBA  
OutputSkew(2)  
tW  
3
3
ns  
ps  
tSK(o)  
500  
NOTES:  
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.  
2. Skew between any two outputs of the same package and switching in the same direction.  
4
IDT74LVCR16952A  
3.3VCMOS16-BITREGISTEREDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
TESTCIRCUITSANDWAVEFORMS  
TESTCONDITIONS  
VIH  
VT  
0V  
SAME PHASE  
INPUT TRANSITION  
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V  
Unit  
V
tPHL  
tPHL  
tPLH  
tPLH  
VLOAD  
VIH  
6
6
2 x Vcc  
Vcc  
VOH  
VT  
VOL  
OUTPUT  
2.7  
1.5  
300  
300  
50  
2.7  
1.5  
300  
300  
50  
V
VT  
Vcc / 2  
150  
V
VIH  
VT  
0V  
VLZ  
VHZ  
CL  
mV  
mV  
pF  
OPPOSITE PHASE  
INPUT TRANSITION  
150  
LVC Link  
30  
Propagation Delay  
DISABLE  
ENABLE  
VLOAD  
Open  
GND  
VIH  
VT  
VCC  
CONTROL  
INPUT  
0V  
tPZL  
tPLZ  
500  
VIN  
VLOAD/2  
VOUT  
VLOAD/2  
OUTPUT  
NORMALLY  
LOW  
Pulse (1, 2)  
Generator  
SWITCH  
CLOSED  
D.U.T.  
VT  
VLZ  
VOL  
tPHZ  
tPZH  
SWITCH  
OPEN  
500Ω  
RT  
VOH  
VHZ  
OUTPUT  
NORMALLY  
HIGH  
CL  
VT  
0V  
0V  
LVC Link  
Test Circuit for All Outputs  
LVC Link  
DEFINITIONS:  
CL = Load capacitance: includes jig and probe capacitance.  
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.  
Enable and Disable Times  
NOTE:  
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.  
NOTES:  
1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.  
2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.  
VIH  
DATA  
INPUT  
VT  
0V  
tSU  
tH  
SWITCHPOSITION  
VIH  
VT  
0V  
VIH  
VT  
0V  
VIH  
VT  
0V  
TIMING  
INPUT  
Test  
Switch  
VLOAD  
GND  
Open Drain  
Disable Low  
Enable Low  
tREM  
ASYNCHRONOUS  
CONTROL  
Disable High  
Enable High  
SYNCHRONOUS  
CONTROL  
tSU  
tH  
All Other Tests  
Open  
LVC Link  
VIH  
VT  
0V  
Set-up, Hold, and Release Times  
LOW-HIGH-LOW  
INPUT  
tPLH1  
tPHL1  
VT  
PULSE  
VOH  
VT  
tW  
OUTPUT 1  
VOL  
tSK (x)  
HIGH-LOW-HIGH  
PULSE  
tSK (x)  
VT  
VOH  
VT  
VOL  
LVC Link  
OUTPUT 2  
tPLH2  
tPHL2  
Pulse Width  
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1  
LVC Link  
Output Skew - tSK(X)  
NOTES:  
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.  
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.  
5
IDT74LVCR16952A  
3.3VCMOS16-BITREGISTEREDTRANSCEIVER  
INDUSTRIALTEMPERATURERANGE  
ORDERINGINFORMATION  
XX  
X
XX  
XXXX  
IDT  
XX  
LVC  
Device Type Package  
Bus-Hold  
Family  
Temp. Range  
Thin Shrink Small Outline Package  
PA  
16-Bit Registered Transceiver with 3-State Outputs  
Double-Density, ±12mA  
952A  
R16  
Blank No Bus-hold  
74  
-40°C to +85°C  
CORPORATE HEADQUARTERS  
2975StenderWay  
Santa Clara, CA 95054  
for SALES:  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
for Tech Support:  
logichelp@idt.com  
(408) 654-6459  
www.idt.com  
6

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