IDT74SSTUBF32869ABKG8 [IDT]
D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PBGA150, BGA-150;
| 型号： | IDT74SSTUBF32869ABKG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PBGA150, BGA-150 逻辑集成电路 触发器 |
| 文件： | 总21页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL
IDT74SSTUBF32869A
The IDT74SSTUBF32869A includes a parity checking
function. The IDT74SSTUBF32869A accepts a parity bit
from the memory controller at its input pin PARIN one or
two cycles after the corresponding data input, compares it
with the data received on the D-inputs and indicates on its
opendrain PTYERR pin (active low) whether a parity error
has occurred. The number of cycles depends on the setting
of C1.
Description
The IDT74SSTUBF32869A is 14-bit 1:2 registered buffer
with parity, designed for 1.7 V to 1.9 V VDD operation.
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8V CMOS drivers optimized to drive the
DDR2 DIMM load. They provide 50% more dynamic driver
strength than the standard SSTU32864 outputs.
When used as a single device, the C1 input is tied low.
When used in pairs, the C1 inputs is tied low for the first
register (front) and the C1 input is tied high for the second
register. When used as a single register, the PPO and
PTYERR signals are produced two clock cycles after the
corresponding data input. When used in pairs, the PTYERR
signals of the first register are left floating. The PPO outputs
of the first register are cascaded to the PARIN signas on the
second register (back). The PPO and PTYERR signals of
the second register are produced three clock cycles after
the corresponding data input. Parity implimentation and
device wiring for single and dual die is described in the
diagram below.
The IDT74SSTUBF32869A operates from a differential
clock (CLK and CLK). Data are registered at the crossing of
CLK going high, and CLK going low.
The device supports low-power standby operation. When
the reset input (RESET) is low, the differential input
receivers are disabled, and undriven (floating) data, clock
and reference voltage (VREF) inputs are allowed. In
addition, when RESET is low all registers are reset, and all
outputs except PTYERR are forced low. The LVCMOS
RESET input must always be held at a valid logic high or
low level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the low
state during power up.
If an error occurs, and the PTYERR is driven low, it stays
low for two clock cycles or until RESET is driven low. The
DIMM-dependent signals (DCKE, DCS, CSR and DODT)
are not included in the parity check computations.
In the DDR2 RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be
cleared and the outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. IDT74SSTUBF32869A must ensure that the
outputs remain low as long as the data inputs are low, the
clock is stable during the time from the low-to-high
transition of RESET and the input receivers are fully
enabled. This will ensures that there are no glitches on the
output.
All registers used on an individual DIMM must be of the
same configuration, i.e single or dual die.
Features
• 14-bit 1:2 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs
and outputs
• 50% more dynamic driver strength than standard
SSTU32864
• Supports LVCMOS switching levels on C1 and RESET
inputs
• Low voltage operation: VDD = 1.7V to 1.9V
• Available in 150 BGA package
The device monitors both DCS and CSR inputs and will
gate the Qn, PPO (Paritial-Parity-Out) and PTYERR (Parity
Error) Parity outputs from changing states when both DCS
and CSR are high. If either DCS and CSR input is low, the
Qn, PPO and PTYERR outputs will function normally. The
RESET input has priority over the DCS and CSR controls
and will force the Qn and PPO outputs low and the
PTYERR high.
Applications
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS98ULPA877A or IDTCSPUA877A
• Ideal for DDR2 667 and 800
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Parity Implementation and Device Wiring
PTYERR, W1
PPO, W8
PPO, W4
PARIN, W4
Register 1
(Front)
Register 2
(Back)
PARIN
NC, A11
NC, A8
NC, A4
NC, A8
Set C=0 for Register 1, and C=1 for Register 2
Block Diagram
(CS Active)
VREF
2
2
PPO
2
2
Q
D
R
PARITY GENERATOR
AND CHECKER
PARIN
2
PTYERR
Q1A
Q
Q
D
R
D1
Q1
B
11
(1)
Q14
A
D14(1)
D
R
(1)
Q14
B
QCS
A
DCS0
Q
D
R
QCS
B
CSR
QCKE
A
DCKE
Q
Q
D
R
QCKE
B
QODT
A
DODT
D
R
QODT
B
RESET
CLK
CLK
NOTE:
1.This range does not include D1, D4, and D7, and their corresponding outputs.
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Block Diagram
RESET
LPS0
(Internal Node)
CLK
CLK
CE
CLK
D
D2 - D3,
D5 - D6,
D8 - D14
11
R
Q2 A- Q3A,
Q5A - Q6A,
Q8A - Q14A
D2 - D3,
D5 - D6,
D8 - D14
CE
11
11
D
R
VREF
11
CLK
Q2B - Q3B,
Q5B - Q6B,
Q8B - Q14B
D2 - D3,
D5 - D6,
D8 - D25
11
Parity
Check
0
1
2
PPO
D
R
D
R
CLK
CE
CLK
2
2
PARIN
PTYERR
C1, C2
CLK
0
1
2-Bit
Counter
D
R
R
CLK
NOTE:
1.PARIN is used to generate PPO and PTYERR.
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Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
(1)
(1)
NC
NB
VDD
GND
VREF
GND
VDD
A
B
C
D
NC
MCL
VDD
NB
NC
MCL
VDD
NB
VDD
NB
GND
GND
NB
GND
NB
GND
GND
NB
GND
NB
GND
GND
NB
NB
VDD
VDD
VDD
QCKEB
Q2B
QCKEA VDD
Q2A
Q3A
VDD
VDD
GND
DCKE
D2
GND
NB
D3
NB
NC
NB
DODT
NB
C1
Q3B
E
QODTA VDD
GND
GND
NB
D5
NC
NB
NB
NC
NB
NB
D6
GND
GND
VDD
VDD
QODTB
Q5B
F
Q5A
Q6A
VDD
NB
CLK
G
GND
NB
NC
NB
NC
NB
GND
NB
Q6B
H
QCSA
VDD
VDD
VDD
NB
GND
NB
NC
NB
NB
NB
RESET
NB
NB
NB
NB
CSR
GND
D8
NB
VDD
NB
VDD
VDD
QCSB
VDD
J
GND
DCS
K
L
Q8A
VDD
CLK
VDD
Q8B
Q9A
Q10A
Q11A
NB
VDD
VDD
GND
GND
GND
NB
D9
NB
NC
NB
NC
NB
NC
NB
NC
NB
NC
NB
GND
GND
GND
NB
VDD
VDD
Q9B
Q10B
Q11B
M
N
P
D10
NB
Q12A
Q13A
Q14A
VDD
C1
VDD
VDD
NB
NB
GND
NB
D11
NB
NB
D13
NB
NC
NB
NB
D14
NB
D12
NB
NB
GND
NB
VDD
VDD
VDD
NB
Q12B
Q13B
Q14B
VDD
R
T
GND
GND
GND
GND
VREF
GND
GND
PPO
U
V
VDD
GND
GND
GND
GND
VDD
(1)
(1)
PTYERR
VDD
VDD
NB
MCL PARIN
MCL
W
150-Ball BGA
TOP VIEW
NOTE:
1.NC denotes a no-connect (ball present but not connected to the die). NB indicates no ball is populated at that
gridpoint.
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150 Ball CTBGA Package Attributes
Top
Marking
11 10
9
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
10 11
A
B
A
B
C
D
E
F
C
D
E
F
G
H
G
H
J
J
K
L
K
L
M
N
P
M
N
P
R
T
R
T
U
V
U
V
W
W
TOP VIEW
BOTTOM VIEW
SIDE VIEW
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Function Table
Inputs1
Outputs
RESET
DCS
L
CSR
L
CLK
CLK
Dn, DODT, DCKE
Qn
QCS QODT, QCKE
H
H
H
H
H
H
H
H
H
H
H
H
L
↑
↓
L
L
L
L
L
L
L
↑
L or H
↑
↓
L or H
↓
H
H
H
2
2
2
2
2
2
2
2
2
L
L
X
Q
Q
Q
0
0
0
L
H
L
L
L
L
L
L
H
↑
↓
H
H
H
2
L
H
L or H
↑
L or H
↓
X
Q
Q
Q
0
0
0
H
L
L
L
H
H
L
H
L
↑
↓
H
H
H
2
2
2
2
H
L
L or H
↑
L or H
↓
X
Q
Q
Q
0
0
0
0
0
0
H
H
L
Q
Q
Q
H
L
H
H
↑
↓
H
X
H
H
H
H
L or H
L or H
Q
Q
0
0
X or
X or
X or
X or
X or Floating
L
L
L
Floating Floating Floating Floating
1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
Output Level before the indicated steady-state conditions were established.
2
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Terminal Functions
Signal
Group
Terminal
Name
Type
Description
Ungated
Inputs
DCKE, DODT
SSTL_18
SSTL_18
DRAM function pins not associated with Chip Select
Chip Select
Gated Inputs
1
D1...D14
DRAM inputs, re-driven only when Chip Select is LOW
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will be
LOW when a valid address/command is present.
Chip Select
Inputs
DCS, CSR
SSTL_18
SSTL_18
1
Q1A...Q14A ,
1
Q1B...Q14B ,
Re-Driven
Outputs
Outputs of the register, valid after the specified clock count and
immediately following a rising edge of the clock
QCSnA, B
QCKEnA, B
QODTnA, B
Input parity is received on pin PARIN, and should maintain odd
parity across the D1:D14 inputs, at the rising edge of the clock,
one cycle after Chip Select is LOW.
Parity Input
PARIN
PPO
SSTL_18
SSTL_18
Parity Output
Partial Parity Output. Indicates parity out of D1-D14.
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
Parity Error
Output
Open Drain PTYERR will be active for two clock cycles, and delayed by in
total two clock cycles for compatibility with final parity out timing
on the industry-standard DDR2 register with parity (in JEDEC
definition).
PTYERR
Configuration
Inputs
When LOW, the register is configured as Register 1. When
SSTL_18
C1
HIGH, the register is configured as Register 2.
Differential master clock input pair to the register. The register
Clock Inputs
CLK, CLK
SSTL_18
operation is triggered by a rising edge on the positive clock
input (CLK).
Asynchronous Reset Input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET also
resets the PTYERR signal.
SSTL_18
Input
RESET
VREF
Input reference voltage for SSTL_18 inputs. Two pins
0.9V nominal (internally tied together) are used for increased
Inputsreliability.
Miscellaneous
Inputs
VDD
Power Input Power Supply Voltage
Ground Input Ground
GND
1
This range does not include D1, D4, and D7, and their corresponding outputs.
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Parity and Standby Function Table
Inputs1
Outputs
RESET
DCS
CSR
CLK
CLK Σ of Inputs = H
PARIN3
PPO
PTYERR4
(D1 - D14)2
H
H
H
H
H
H
H
H
H
H
L
L
L
X
X
↑
↓
Even
Odd
L
L
H
L
↑
↓
L
H
L
X
↑
↓
Even
Odd
H
H
L
L
X
↑
↓
H
L
H
H
L
L
L
↑
↑
↓
↓
Even
Odd
L
L
H
L
L
L
L
L
↑
↓
Even
Odd
H
H
L
L
L
↑
↓
H
L
H
H
X
H
X
↑
↓
X
X
X
PPOn
PTYERRn
0
0
L or H
L or H
X
PPOn
L
PTYERRn
0
0
X or
X or
X or
X or
X or Floating
X or Floating
H
Floating Floating Floating Floating
1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2
3
4
This range does not include D1, D4, and D7.
PARIN arrives one clock cycle (C1 = 0), or two clock cycles (C1 = 1), after the data to which it applies.
This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. PARIN is used to
generate PPO and PTYERR.
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Absolute Maximum Ratings
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Item
Rating
Supply Voltage, VDD
-0.5V to 2.5V
1
Input Voltage Range, VI
-0.5V to VDD + 2.5V
-0.5V to VDDQ + 0.5V
±50mA
1,2
Output Voltage Range, VO
Input Clamp Current, IIK
Output Clamp Current, IOK
±50mA
Continuous Output Clamp Current, IO
±50mA
Continuous Current through each VDD or GND
±100mA
0m/s Airflow
1m/s Airflow
40° C/W
3
Package Thermal Impedance (θja)
29° C/W
Storage Temperature, TSTG
-65 to +150°C
1
The input and output negative voltage ratings may be exceeded if the ratings of the I/P and
O/P clamp current are observed.
2
3
This current will flow only when the output is in the high state level VO > VDDQ.
The package thermal impedance is calculated in accordance with JESD 51.
Mode Select
C1
0
Device Mode
First device in pair, Front
Second device in pair, Back
1
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range
VDD = 1.8V ± 0.1V
Parameter
dV/dt_r
Min.
Max.
Units
V/ns
V/ns
V/ns
1
1
4
4
1
dV/dt_f
1
dV/dt_∆
1
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
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Operating Characteristics, TA = 25°C
The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
The differential inputs must not be floating unless RESET is LOW.
Symbol
VDD
VREF
VTT
VI
Parameter
Min.
1.7
Typ.
1.8
Max.
1.9
Units
I/O Supply Voltage
V
V
V
V
Reference Voltage
0.49 * VDD
VREF - 0.04
0
0.5 * VDD
VREF
0.51 * VDD
VREF + 0.04
VDD
Termination Voltage
Input Voltage
VIH
AC High-Level Input Voltage
AC Low-Level Input Voltage
DC High-Level Input Voltage
DC Low-Level Input Voltage
High-Level Input Voltage
Low-Level Input Voltage
Common Mode Input Range
Differential Input Voltage
High-Level Output Current
Low-Level Output Current
VREF + 0.25
Dn, PARIN,
DCS, CSR,
DCKEn,
VIL
VREF - 0.25
V
V
VIH
VREF + 0.125
0.65 * VDDQ
DODTn
VIL
VREF - 0.125
VIH
RESET, C1
CLK, CLK
VIL
0.35 * VDDQ
1.125
VICR
VID
0.675
600
V
mV
IOH
-12
12
mA
IOL
IERROL
TA
PTYERR Low-Level Output Current
Operating Free-Air Temperature
25
0
mA
+70
°C
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DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDDQ/VDD = 1.8V ± 0.1V.
Symbol
Parameter
Test Conditions
Min.
Typ. Max.
Units
VIK
II = -18mA
-1.2
V
VDDQ = 1.7V, IOH = -100µA
VDDQ = 1.7V, IOH = -12mA
VDDQ = 1.7V, IOL = 100µA
VDDQ = 1.7V, IOL = 12mA
IERROL = 25mA; VDD = 1.7V
VDDQ-0.2
1.2
VOH
VOL
V
0.2
0.5
0.5
V
V
PTYERR Output
Low Voltage
VERROL
IIL
All Inputs
VI = VDD or GND
-5
+5
µA
µA
Static Standby
IO = 0, VDD = 1.9V, RESET = GND
200
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = CLK = VIH(AC)
or VIL(AC)
10
IDD
Static Operating
mA
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = VIH(AC), CLK
= VIL(AC)
140
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle
Dynamic Operating
(clock only)
µA/Clock
MHz
247
IO = 0, VDD = 1.8V, RESET = VDD, VI =
Dynamic Operating VIH(AC) or VIL(AC), CLK and CLK
IDDD
µA/Clock
MHz/
Data
(per each data
input)
switching 50% duty cycle. One data
input switching at half clock frequency,
50% duty cycle.
52
Dn, PARIN, DSCn
inputs
VI = VREF ± 250mV
VICR = 0.9V, VIPP = 600mV
VI = VDD or GND
2
3
4.5
CIN
CLK and CLK
inputs
3.5
pF
RESET
4.5
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Timing Requirements Over Recommended Operating Free-Air Temperature
Range
VDD = 1.8V ± 0.1V
Symbol
fCLOCK
tW
Parameter
Min.
Max.
Units
MHz
ns
Clock Frequency
410
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
1
1
tACT
10
15
ns
2
tINACT
ns
DCS before CLK↑ , CLK↓, CSR HIGH; CSR before
CLK↑ , CLK↓, DCS HIGH
0.6
Setup
Time
DCS before CLK↑ , CLK↓, CSR LOW
0.5
0.5
0.5
0.4
0.4
tSU
ns
DODT, DOCKE, and data before CLK↑ , CLK↓
PAR_IN before CLK↑ , CLK↓
DCS, DODT, DCKE, and data after CLK↑ , CLK↓
PAR_IN after CLK↑ , CLK↓
Hold
Time
tH
ns
1
VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
minimum time of tACT(max) after RESET is taken HIGH.
VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
2
time of tINACT(max) after RESET is taken LOW.
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
VDD = 1.8V ± 0.1V
Symbol Parameter
Min.
340
1.1
Max.
Units
MHz
ns
fMAX
Max Input Clock Frequency
1
tPDM
Propagation Delay, single-bit switching, CLK↑ / CLK↓to Qn
Propagation Delay, single-bit switching, CLK↑ / CLK↓to Qn
Propagation Delay, simultaneous switching, CLK↑ / CLK↓to Qn
LOW to HIGH Propagation Delay, CLK↑ / CLK↓to PTYERR
HIGH to LOW Propagation Delay, CLK↑ / CLK↓to PTYERR
Propagation Delay from CLK↑ / CLK↓to PPO
1.5
0.8
1.6
3
2
tPD
tPDMSS
tLH
0.4
ns
1
ns
1.2
0.4
0.5
ns
tHL
3
ns
tPD
1.6
3
ns
tPHL
tPLH
HIGH to LOW Propagation Delay, RESET↓to Qn↓
ns
LOW to HIGH Propagation Delay, RESET↓to PTYERR↑
3
ns
1
2
Design target as per JEDEC specifications.
Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
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Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range
VDD = 1.8V ± 0.1V
Parameter
dV/dt_r
Min.
Max.
Units
V/ns
V/ns
V/ns
1
1
4
4
1
dV/dt_f
1
dV/dt_∆
1
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
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Register Timing
RESET
DCS
CSR
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
tSU
tH
D1 - D14(1)
Q1 - Q14(1)
tPD
CLK to Q
tH
tSU
(2)
PARIN
tPD
CLK to PPO
PPO (2)
tPD
tPD
CLK to PTYERR
CLK to PTYERR
PTYERR (2)
NOTES:
1.This range does not include D1, D4, and D7, and their corresponding outputs.
2.PARIN is used to generate PPO and PTYERR.
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Register Timing
RESET
DCS
CSR
n
n + 1
n + 2
n + 3
n + 4
CLK
CLK
tSU
tH
D1 - D14(1)
tPD
CLK to Q
Q1 - Q14(1)
PARIN(2)
tH
tSU
tPD
CLK to PPO
PPO(2)
(not used)
tPD
CLK to PTYERR
tPD
CLK to PTYERR
PTYERR (2)
NOTES:
1.This range does not include D1, D4, and D7, and their corresponding outputs.
2.PARIN is used to generate PPO and PTYERR.
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Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
VDD/2
VDD
Test
Point
DUT
CLK
ZO = 50
RL = 1K
DUT
RL = 50
Test
Point
TL = 50
ZO = 50
TL = 350ps, 50
CLK
Out
CLK Inputs
Test
Point
Out
Test Point
RL = 1K
CLK Inputs
CLK
ZO = 50
CLK
CL = 30 pF
Test Point
RL = 100
Test Point
Production-Test Load Circuit
Simulation Load Circuit
CLK
CLK
V
ID
VICR
VICR
t
PLH
tPHL
VDD
0V
LVCMOS
RESET
Input
V
V
OH
OL
Output
VTT
VTT
VDD/2
VDD/2
tINACT
tACT
Voltage Waveforms - Propagation Delay Times
90%
IDD
10%
LVCMOS
V
IH
IL
RESET
Input
VDD/2
V
Voltage and Current Waveforms Inputs Active and Inactive
Times
tRPHL
V
OH
OL
VTT
Output
V
tW
Voltage Waveforms - Propagation Delay Times
VID
Input
VICR
VICR
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and
Io = 0mA
Voltage Waveforms - Pulse Duration
3. All input pulses are supplied by generators having the following
characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns
±20% (unless otherwise specified).
CLK
CLK
VID
VICR
4. The outputs are measured one at a time with one transition per
measurement.
5. VTT = VREF = VDD/2
tSU
tH
VIH
VIL
Input
VREF
VREF
6. VIH = VREF + 250mV (AC voltage levels) for differential inputs.
VIH = VDD for LVCMOS input.
7. VIL = VREF - 250mV (AC voltage levels) for differential inputs.
VIL = GND for LVCMOS input.
Voltage Waveforms - Setup and Hold Times
8. VID = 600mV.
9. tPLH and tPHL are the same as tPDM.
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Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
VDD
VDD
DUT
DUT
RL = 50
RL = 1K
Out
Out
Test Point
Test Point
CL = 10 pF
CL = 10 pF
Load Circuit: Error Output Measurements
Load Circuit: High-to-Low Slew-Rate Adjustment
LVCMOS
RESET
Input
VCC
0V
VCC/2
Output
VOH
80%
tPLH
VOH
0V
20%
dt_f
0.15V
Output
Waveform 2
dv_f
VOL
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to RESET input)
Timing
Inputs
VICR
tHL
VICR
VI(PP)
DUT
Out
Test Point
RL = 50
CL = 10 pF
VCC
VOL
Output
Waveform 1
VCC/2
Voltage Waveforms: Open Drain Output High-to-Low
Transition Time (with respect to clock inputs)
Load Circuit: Low-to-High Slew-Rate Adjustment
Timing
Inputs
dt_r
VICR
tHL
VICR
VI(PP)
VOH
dv_r
80%
VOH
0V
0.15V
Output
Waveform 2
20%
VOL
Output
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to clock inputs)
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
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Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
DUT
OUT
Testpoint
RL = 1K
(1)
CL = 5pF
Partial Parity Out Load Circuit
CLK
CLK
VI(PP)
VICR
VICR
t
PHL
tPLH
VTT
V
TT
Output
Partial Parity Out Voltage Waveform, Propagation Delay Time with Respect to CLK Input
VTT = VTT/2
VICR Cross Point Voltage
VI(PP) = 600mV
tPLH and tPHL are the same as tPD.
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Application Information
The typical values below are measured on standard JEDEC raw cards, using the JEDEC DDR2 register validation
board running patterns 0x43, 0x4F, and 0x5A.
Raw Card Values
Raw Card1
tPDMSS
Overshoot
Undershoot
W
1.48
446
444
1
All values are valid under nominal conditions and minimum/maximum of typical sig-
nals on one typical DIMM. Measurements include all jitter and ISI effects.
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Ordering Information
XX
XXX
XX
X
IDT74SSTUBF
Family Device Type Package Shipping
Carrier
8
Tape and Reel
BKG Low Profile, Fine Pitch, Ball Grid Array
869A 14-Bit Configurable Registered Buffer for DDR2
32
Double Density
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800-345-7015
408-284-8200
Fax: 408-284-2775
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+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
IDT74SSTV16857APA
D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, TSSOP-48
IDT
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