IDT74SSTVN16859 [IDT]
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O; 13位到26位寄存缓冲器与SSTL I / O型号: | IDT74SSTVN16859 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O |
文件: | 总7页 (文件大小:65K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
13-BIT TO 26-BIT REGISTERED IDT74SSTVN16859
BUFFER WITH SSTL I/O
FEATURES:
DESCRIPTION:
• 1:2 registered output buffer
The SSTVN16859 is a 13-bit to 26-bit registered buffer designed for
• 2.3V to 2.7V operation for PC1600, PC2100, and PC2700
• 2.5V to 2.7V operation for PC3200
• Single bit propagation delay, TSSOP : 2.2ns, VFQFPN : 1.8ns
• SSTL_2 Class I style data inputs/outputs
• Differential CLK input
• RESET control compatible with LVCMOS levels
• Latch-up performance exceeds 100mA
• ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
2.3V-2.7VVDD forPC1600-PC2700and2.5V-2.7VVDD forPC3200, and
supports low standby operation. All data inputs and outputs are SSTL_2
level compatible with JEDEC standard for SSTL_2.
RESETisanLVCMOSinputsinceitmustoperatepredictablyduringthe
power-upphase.RESET,whichcanbeoperatedindependentofCLKand
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET, when in the low state, will disable all input receivers, reset all
registers,andforcealloutputstoalowstate,beforeastableclockhasbeen
applied. Withinputsheldlowandastableclockapplied,outputswillremain
low during the Low-to-High transition of RESET.
• Available in 56 pin VFQFPN and 64 pin TSSOP packages
APPLICATIONS:
• Ideally suited for stacked DIMM DDR registered applications
• Along with CSPT857C/D, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 DIMMs
FUNCTIONALBLOCKDIAGRAM
51
RESET
48
CLK
49
CLK
45
VREF
35
D1
16
Q1A
1D
C1
32
R
Q1B
TO 12 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 2004
1
c
2004 Integrated Device Technology, Inc.
DSC-6836/13
IDT74SSTVN16859
COMMERCIALTEMPERATURERANGE
13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O
PINCONFIGURATIONS
Q13A
Q12A
Q11A
Q10A
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDQ
GND
D13
2
3
4
D12
5
VDD
Q9A
Q7A
1
42
D10
D9
VDDQ
6
VDDQ
Q6A
Q5A
7
GND
Q8A
Q7A
GND
D11
D8
D7
8
Q4A
Q3A
Q2A
9
D10
D9
RESET
GND
Q6A
Q5A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
D8
Q1A
CLK
GND
Q4A
Q3A
Q13B
VDDQ
CLK
VDDQ
VDD
VREF
D6
D7
RESET
GND
CLK
CLK
VDDQ
VDD
Q2A
GND
Q1A
Q12B
Q11B
Q10B
Q13B
D5
Q9B
VDDQ
29 D4
14
Q8B
Q12B
Q11B
Q10B
VREF
D6
GND
D5
Q9B
Q8B
Q7B
D4
VFQFPN
TOP VIEW
D3
Q6B
GND
GND
VDDQ
VDD
VDDQ
Q5B
Q4B
Q3B
D2
ABSOLUTE MAXIMUM RATINGS (1)
D1
Symbol
Description
Max.
–0.5to3.6
–0.5 to VDD +0.5
–0.5toVDDQ +0.5
–50
Unit
V
GND
Q2B
Q1B
VDD orVDDQ SupplyVoltageRange
VDDQ
(2)
VI
InputVoltageRange
V
(3)
VO
OutputVoltageRange
Input Clamp Current, VI < 0
OutputClampCurrent,
VO < 0 or VO > VDDQ
ContinuousOutputCurrent,
VO = 0 to VDDQ
V
TSSOP
TOP VIEW
IIK
mA
mA
IOK
IO
±50
±50
±100
mA
mA
°C
FUNCTION TABLE (1)
VDD
ContinuousCurrentthrougheach
VDD, VDDQ or GND
Input
RESET
CLK
↑
↑
CLK
↓
↓
D
L
Q Outputs
TSTG
StorageTemperatureRange
–65to+150
H
H
H
L
H
Qo(2)
H
X
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. The output current will flow if the following conditions are observed:
a) Output in HIGH state
L or H
L or H
L
X
X
X
L
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
b) VO = VDDQ
2. Qo = Output level before the indicated steady-state conditions were established.
2
IDT74SSTVN16859
COMMERCIALTEMPERATURERANGE
13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O
PINDESCRIPTION
Pin Names
Description
Q1 - Q13
DataOutput
GND
Ground
VDDQ
Output-stagedrainpowervoltage
Logicpowervoltage
VDD
RESET
VREF
Asynchronousresetinput-resetsregistersanddisablesdataandclockdifferentialinputrecievers
Inputreferencevoltage
CLK
Positivemasterclockinput
CLK
Negativemasterclockinput
D1 - D13
Center PAD
Data Input - clocked in on the crossing of the rising edge of CLK and the falling edge of CLK
Ground(MLFpackageonly)
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFORPC1600-
PC2700
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V
Symbol
VIK
Parameter
Test Conditions
Min.
Typ.
—
—
—
—
—
—
—
—
6
Max.
–1.2
—
Unit
V
ControlInputs
VDD = 2.3V, II= −18mA
VDD = 2.3V to 2.7V, IOH = -100µA
VDD = 2.3V, IOH = -8mA
—
VDD – 0.2
1.95
—
VOH
V
—
VOL
VDD = 2.3V to 2.7V, IOL = 100µA
VDD = 2.3V, IOL = 8mA
0.2
0.35
±5
0.01
20
V
—
II
AllInputs
VDD = 2.7V,VI = VDD or GND
—
µA
mA
IDD
StaticStandby
IO = 0, VDD = 2.7V, RESET = GND
IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC)
IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),
CLK and CLK Switching 50% Duty Cycle.
IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),
CLK and CLK Switching 50% Duty Cycle. One Data Input
Switching at Half Clock Frequency, 50% Duty Cycle.
VDD = 2.5V, VI = VREF ± 310mV
—
StaticOperating
—
Dynamic Operating (Clock Only)
—
—
µA/Clock
MHz
IDDD
CI
DynamicOperating
(PerEachDataInput)(1)
—
43
—
µA/Clock
MHz/Data
Input
DataInputs
CLK and CLK
RESET
2
2
2
—
—
—
3
3
3
VICR = 1.25V, VI (PP) = 360mV
pF
VI = VDD or GND
NOTE:
1. Power dissipation levels will allow operation at DDR333 speeds without excessive die temperature.
3
IDT74SSTVN16859
COMMERCIALTEMPERATURERANGE
13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFORPC3200
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, VDD = 2.6V ±0.1V, VDDQ = 2.6V ±0.1V
Symbol
VIK
Parameter
Test Conditions
Min.
Typ.
—
—
—
—
—
—
—
—
6
Max.
–1.2
—
Unit
V
ControlInputs
VDD = 2.5V, II= −18mA
VDD = 2.5V to 2.7V, IOH = -100µA
VDD = 2.5V, IOH = -8mA
—
VDD – 0.2
1.95
—
VOH
V
—
VOL
VDD = 2.5V to 2.7V, IOL = 100µA
VDD = 2.5V, IOL = 8mA
0.2
0.35
±5
V
—
II
AllInputs
VDD = 2.7V,VI = VDD or GND
—
µA
mA
IDD
StaticStandby
IO = 0, VDD = 2.7V, RESET = GND
IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC)
IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),
CLK and CLK Switching 50% Duty Cycle.
IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),
CLK and CLK Switching 50% Duty Cycle. One Data Input
Switching at Half Clock Frequency, 50% Duty Cycle.
VDD = 2.6V, VI = VREF ± 310mV
—
0.01
StaticOperating
—
20
Dynamic Operating (Clock Only)
—
—
µA/Clock
MHz
IDDD
CI
DynamicOperating
(PerEachDataInput)(1)
—
43
—
µA/Clock
MHz/Data
Input
DataInputs
CLK and CLK
RESET
2
2
2
—
—
—
3
3
3
VICR = 1.3V, VI (PP) = 360mV
pF
VI = VDD or GND
NOTE:
1. Power dissipation levels will allow operation at DDR400 speeds without excessive die temperature.
OPERATING CHARACTERISTICS, TA = 25ºC (1)
Symbol
VDD
Parameter
Min.
Typ.(1)
—
Max.
Unit
V
SupplyVoltage
OutputSupplyVoltage
VDDQ
2.7
VDDQ
PC1600 - PC12700
PC3200
2.3
2.5
2.6
1.25
1.3
VREF
—
2.7
V
2.5
2.7
VREF
ReferenceVoltage(VREF=VDDQ/2) PC1600 - PC2700
1.15
1.35
V
PC3200
TerminationVoltage
1.25
1.35
VTT
VI
VREF– 40mV
VREF+ 40mV
V
V
InputVoltage
0
VDD
VIH
VIL
AC High-Level Input Voltage
AC Low-Level Input Voltage
DCHigh-LevelInputVoltage
DCLow-LevelInputVoltage
High-LevelInputVoltage
DataInputs
DataInputs
DataInputs
DataInputs
RESET
VREF+ 310mV
—
—
V
—
—
VREF–310mV
V
VIH
VIL
VREF+ 150mV
—
—
V
—
1.7
—
—
VREF–150mV
V
VIH
VIL
—
—
0.7
1.53
—
V
Low-LevelInputVoltage
RESET
—
V
VICR
VI(PP)
IOH
IOL
Common-ModeInputRange
Peak-to-PeakInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingFree-AirTemperature
CLK, CLK
CLK, CLK
0.97
360
—
—
V
—
mV
mA
—
–16
16
—
—
TA
0
—
+70
°C
NOTE:
1. The RESET input of the device must be held at VDD or GND to ensure proper device operation.
4
IDT74SSTVN16859
COMMERCIALTEMPERATURERANGE
13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O
TIMINGREQUIREMENTSOVERRECOMMENDEDOPERATINGFREE-AIR
TEMPERATURERANGE
PC1600-PC2700
Max.
PC3200
Symbol
CLOCK
tw
Parameter
Min.
—
Min.
—
Max.
220
—
Unit
MHz
ns
Clock Frequency
200
—
22
22
—
—
—
—
Pulse Duration, CLK, CLK HIGH or LOW
DifferentialInputsActiveTime(1)
DifferentialInputsInactiveTime(2)
Setup Time, Fast Slew Rate(3, 5) Data Before CLK↑, CLK↓
Setup Time, Slow Slew Rate(4, 5)
Hold Time, Fast Slew Rate(3,5)
Hold Time, Slow Slew Rate(2,5)
2.5
2.5
tACT
—
—
22
ns
tINACT
tSU
—
—
22
ns
0.65
0.75
0.75
0.9
0.65
0.75
0.65
0.8
—
ns
—
ns
tH
Data Before CLK↑, CLK ↓
—
ns
—
ns
NOTES:
1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH.
2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW.
3. For data signal input slew rate is ≥1V/ns.
4. For data signal input slew rate is ≥0.5V/ns and <1V/ns.
5. CLK, CLK signal input slew rates are ≥1V/ns.
SWITCHINGCHARACTERISTICSOVERRECOMMENDEDFREE-AIROPERATING
RANGE(UNLESSOTHERWISENOTED)
PC1600-PC2700
PC3200
Symbol
fMAX
Parameter
Package
Min.
200
1.1
1.1
—
Max.
—
Min.
Max.
—
Unit
MHz
ns
TSSOP, VFQFPN
TSSOP
220
1.1
1.1
—
tPDM
CLK and CLK to Q
2.4
2.2
2.7
2.5
5
2.2
VFQFPN
1.8
tPDMSS
tPHL
CLK and CLK to Q (simultaneous switching)
RESET to Q
TSSOP
2.5
ns
ns
VFQFPN
—
—
((TBD))
5
TSSOP, VFQFPN
—
—
5
IDT74SSTVN16859
COMMERCIALTEMPERATURERANGE
13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O
TEST CIRCUITS AND WAVEFORMS
FOR PC1600 - PC2700, VDD = 2.5V ± 0.2V
FOR PC3200, VDD = 2.6V ± 0.1V
VTT
RL = 50Ω
Test Point
CL = 30 pF
(see note 1)
Load Circuit
LVCMOS
RESET
Input
VDD
0V
Timing
Input
VI(PP)
VDD/2
VDD/2
VICR
VICR
tINACT
tACT
tPLH
tPHL
VTT
VOH
VOL
90%
VTT
IDD
10%
Output
(see note 2)
Voltage and Current Waveforms
Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
LVCMOS
RESET
Input
VIH
VIL
VDD/2
tPHL
VTT
tW
VOH
VOL
VIH
VIL
Output
Input
VREF
VREF
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Pulse Duration
Timing
Input
VICR
VI(PP)
tSU
tH
VIH
VIL
Input
VREF
VREF
Voltage Waveforms - Setup and Hold Times
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.
3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPDM is tPD with one output switching. tPDMSS is tPD with all outputs switching.
6
IDT74SSTVN16859
COMMERCIALTEMPERATURERANGE
13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O
ORDERINGINFORMATION
XX
XX
XXX
XX
IDT74SSTVN
Family Device Type Package Process
0°C to +70°C (Commercial)
Blank
PA
PAG
NL
Thin Shrink Small Outline Package
TSSOP - Green
Thermally Enhanced Plastic Very Fine Pitch
Quad Flat No Lead Package
VFQFPN - Green
NLG
859
13-Bit to 26-Bit Registered Buffer with SSTL I/O
Double-Density
16
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
7
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