IDT75T43100S66BS304 [IDT]
Microprocessor Circuit, CMOS, PBGA304, 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304;
| 型号： | IDT75T43100S66BS304 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Microprocessor Circuit, CMOS, PBGA304, 31 X 31 MM, LOW PROFILE, THERMALLY ENHANCED, SBGA-304 外围集成电路 |
| 文件： | 总46页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance
Information
IDT75T43100
IP Co-PROCESSOR
32K Entries
Features
Abstract
◆
32K x72 bit Data Cells and 32K x72 bit Mask Cells
TheIDT75T43100isdesignedtobeusedinapplicationsthatrequire
high speed data searching such as routers, high layer switching and
applications involvedinthe convergence ofvoice, data andvideo.
IDT’s IP Co-Processors (IPCs) expedite multi level routing of IP
(InternetProtocol)andincludesonchiplogictofacilitatevarioustypesof
IPheaderlookups andprocessingoftheresults.
◆
◆
◆
◆
◆
◆
◆
Fullternarycontentaddressablememory
36/72/144/288multiplewidthlookups
66Msustainedlookups persecondat72and144widthlookups
Synchronouspipelineoperation
Dualbusinterface
Thefeaturesofthisdeviceaddresstheperformancerequirementsof
communicationsystems,whichcanrequireasustainedbandwidthof tens
ofmillionsoflookupspersecond. IDT’sIPCo-Processorisdesignedto
provide a scalable solution to one of the major bottlenecks facing the
bandwidthchallengeofInternettraffic.
Cascadable to8devices withnoglue logicorlatencypenalty
GluelessinterfacetostandardZBT™or
SynchronousPipelinedBurstSRAMs
BoundaryScanJTAGInterface(IEEE1149.1compliant)
2.5V core power supply
◆
◆
◆
◆
◆
User selectable 3.3V or 2.5V I/O supply
1.5Vmatchsupply
PackagedinaJEDECstandard,thermallyenhanced,
low profile 304 Ball Grid Array (BGA)
Overview
IDT’s75T43100isahighperformancepipelined,synchronous 32K
x72 IP Co-Processor (IPC). It utilizes content addressable memory
(CAM)technologytoperformpatternrecognitionfunctions. Eachlocation
intheIPChasbothaDataentryandanassociatedMaskentrywiththe
total array size of 32K x72 Data entries and 32K x72 Mask entries.
The IDT75T43100 has a 72-bit bi-directional bus, which is a 15-bit
multiplexed address and 72-bit data bus that can support 66 million
sustainedsearchespersecond.
Thisdevicewasdevelopedforawiderangeofcommunicationand
networkingapplications,givingittheabilitytosupporttherequirementsof
multiplenetworks. IPC'sareusedinapplicationsthatrequirehighspeed
datasearchingrouters,highlayerswitchingandintheconvergenceof
voice, data, and video. IDT's IPC increases the throughput for the
demandingnetworkingandInternetsystems.
75T43100
S66BS304
The IDT75T43100 utilizes IDT’s latest high-performance 0.18 u
CMOSprocessingtechnologyandis packagedinaJEDECStandard,
thermally enhanced, low profile, 304 Ball Grid Array (BGA).
532 5 d00
MAY 2001
1
©2001IntegratedDeviceTechnology,Inc.
DSC-5325/00
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
BlockDiagram
CONFIGOUT
RDACK
CONFIGIN
Configuration Registers
MATCHIN [6:0]
CE OE
/
and
WE
Ram Control Circuits
VALID
CLK2X
HITACK
÷ 2
CCLK
PHASEN
RST
REQSTB
INST
R/W
Decode
CMD [3:0]
P
R
Command
Bus
G M R
and
I
S
CMD [6:4]
O
R
I
I
S R R
De c o de
Z
E
Index
Bus
INDX
[19:0]
T
Y
32K X 72
L
O
G
I
E
N
C
O
D
E
R
D
E
C
O
D
E
C
Address
A0 - A14
Request
Bus
REQDATA
[71:0]
Bypass
MATCHOUT
DATA
[71:0]
Global Mask Registers
Search Result Registers
5325 drw 01
TMS
TDI
JTAG
TDO
TCK
TRST
2
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
DatasheetFeatures
◆
Figure 1.0B - ASIC / IP Co-Processor configuration
SystemConfigurationsandFunctionalHighlights
◆
SignalDescriptionsandPinout
◆
DCOperatingCharacteristics
◆
RegisterDescription
ASIC
or
- ConfigurationRegisters
IDT
- ReplyWidthRegisters(RWRs)
- SearchResultRegisters(SRRs)
- GlobalMaskRegisters(GMRs)
IPCo-Processor
FPGA
A5325 drw 02b
◆
BusDescription
- CommandBusFormat
- GMRandSRRSelect
- RequestBusFormat
- IndexBus Format
FunctionalHighlights
Data and Mask Array
TheIDT75T43100has32Kx72Datacell
entries and 32K x 72 associated Mask cell
entriesasshowninFig.1.1. Thiscombination
of Data and Mask cell entries enables the
IDT75T43100tostore0,1orX,makingitafull
ternary array IP Co-Processor. During a
lookupoperation,botharraysareusedalong
withaGlobalMaskRegistertofindamatchto
a requested data word.
- AdditionalSignals
Mask
Data
◆
Initialization
◆
ACOperatingCharacteristics
◆
TimingDiagrams
◆
SequenceDiagrams
◆
JTAGInterfaceSpecifications
◆
PackageDiagramOutline
32K x 72
◆
OrderingInformation
Figure 1.1
A5325 drw 03
SystemConfigurations
TheIDT75T43100isdesignedtofulfilltheneedsofvarioustypesof
Networking systems. In solutions requiring data searching such as
routers,anetworkinterfaceasshowninFig1.0Amayberealized.Here
theIDTIPCo-Processor(IPC)interfacesdirectlytoanASIC/FPGA for
lookupsandroutesanindextoanassociatedSRAMdevice,thatsupplies
thenexthopaddressviaanSRAMDataBustotheASIC.TheIPCalso
provides the required control signals to directly hookup to ZBT™ or
SynchronousPipelineBurstSRAM.
Bus Interface
The IP Co-Processor utilizes a dual bus interface consisting of the
Request Bus and the Index Bus.
The72bitbi-directionalRequestBusfunctionsasamultiplexedaddress
anddatabus,which performsthewritingandreadingof IPCo-Processor
resources, as wellas presentinglookupdata tothe device.
TheIndexBusisanindependentunidirectionalbuswhichdrivesthe
result of the lookup (or index) to either an SRAM device or an ASIC. In
addition to driving the Index, the IPC also drives the associated SRAM
control signals (CE/OE, and WE) for either ZBT™ or Synchronous
PipelineBurst SRAMdevices.
Figure 1.0A ASIC / IP Co-Processor / SRAM configuration
Readingdata,maskorregisterentrieswillalwaysresultin72bitsofdata
drivenonthe RequestBus. Writes willalsobe 72bits ofdata.
ASIC
Sync
IDT
or
or
IPCo-Processor
ZBT SRAM
FPGA
Command Bus
A5325 drw02a
TheIDT75T43100carriesa7-bitCommandBus,whichloadsspecific
instructionsintotheIPCo-Processor.Theseinclude:
◆ Read or Write
AReadorWriteinstructionplacedontheCommandBusoperateson
aspecifieddataentry,maskentry,orregister. Duringtheinitiationofa
Readcommand,theRequestBuswillbedrivenwithanaddress,afixed
numberofclockcycleslaterthissamebuswillbedrivenwith therespective
databack. DuringtheinitiationofaWritecommand,theRequestBuswill
receivetheaddressduringthe1stcyclefollowedbytherespectivedata
on the 2nd cycle. All reads and writes are 72-bit entities.
IDT’sIPCcanalsobeconfiguredwithoutusingtheSRAMinterface
as shown in Fig. 1.0B Here the IDT75T43100 processes the lookups
submittedbythecontrollerandfeedstheresultdirectlybacktotheASIC/
FPGA.Inthismanner, thefullcapabilitiesoftheIPCarefullyutilizedwithout
requiring the use of an external SRAM.
The IPC provides the user control of the associated handshake
signalstoadapttoeitherconfiguration.
6.42
3
SystemConfigurationsandFunctionalHighlights
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
FunctionalHighlightscontinued
Registers
TheIDT75T43100canalsoprovidetheaddressandcontrolsignals
for a read or write to an associated SRAM memory. The IPC pipelines
the address from the Request Bus to the Index Bus, driving it out to the
associatedSRAM. TheASIC/FPGAhandlesthepipeliningofthedatato
andfromtheSRAM.
TheIDT75T43100utilizes31registerstoprovideadditionalfeatures
and convenience. There are four basic types of registers supported:
- 4ConfigurationRegisters
- 4ReplywidthRegisters (RWRs)
- 8SearchResultRegisters (SRRs)
◆ SRAM No Wait Read
AnSRAMNoWaitRead is a ReadinstructiontoanexternalSRAM
that can be pipelined within a series of operations. A standard Read
instruction to an external SRAM requires the read to complete prior to
submitting the next instruction. However, the SRAM No Wait Read
instructiondoesnotrequiretheusertowaitforaReadtocomplete. The
nextinstructioncanbeloadedsequentiallyonthefollowingcycle.
◆ Lookup
Alookupcanberequestedin72-bit,144-bitor288-bitwidths. A36-bit
lookup can be accomplished by using GMRs 10 and 11, refer to the
applicationnote(AN-270),"Implementingx36-bitLookups". TheCom-
- 15GlobalMaskRegisters(GMRs)
GMRsareprovidedtosupportLookupinstructionstomaskindividual
bits during a search. Initialization of the IPC uses the Configuration
RegisterstodefinethetimingofoutputsandtheSRAMinterfaceconfigu-
ration. The Configuration registers are also used to specify certain
parameterswhentheIDT75T43100isusedinamultipleIPCimplemen-
tation.
Furtherdetailsofeachtypeofregisterandtheirspecificimplementation
arediscussedinthesectionstitledundertheirrespectiveregistertype. Also
refer to the “Command Bus Format, GMR and SRR Select" and
“Initialization”sectionsforaddressingandsetupoftheseregisters.
mandBusidentifiesthespecificregisterstobeusedwithaparticularlookup.
All the instructions and associated commands are described in the
“Command Bus Format" and "GMR and SRRSelect” sections. Please
refertothesesectionsforfurtherdefinitionoftheinstructioncode.
SRAM Interface
TheIDT75T43100 providesallrequiredaddressandcontrolsignals
foragluelessSRAMinterface.Whentheuserreadsfromorwritestothe
externalSRAM,theIPCprovidesapipelinedbypasspaththattakesthe
19AddressbitsofftheRequestBusanddrivesthemtotheIndexBus. Refer
totheRequestBusFormatandtheIndexBusFormatformoreinformation.
TheASIC/FPGAhandlesthepipeliningofthedatatoandfromtheSRAM.
Controlsignaltimingisprogrammedtoaccommodatestandard ZBT
SRAMs,aswellasSynchronousPipelinedBurstSRAMs.Moredetailed
information,alongwithhowtoconfigurethisinterfaceisdiscussedinthe
“Initialization”section.
Width Capability
TheIDT75T43100iscapableofperforminglookupsorcomparisons
ondatastructuresof72bits,144bitsand288bits. Theinternalmemory
bankofthedevicecanbeusedinthreestandardwidtharrays,asshown
in Figure 1.2.
◆ - 32K x72
◆ - 16K x144
◆ - 8K x288
Figure 1.2
32K X 72
16K X 144
8K X 288
A5325 drw 03a
4
FunctionalHighlights
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
SignalDescriptions
Symbol
Pin Function
# Pins
I/O
Description
IPC Buses:
The Command Bus defines the operation to be performed by the IPC. It also specifies the
lookup type and Global Mask Register to select. It is qualified by the Request Strobe signal to
define a valid IPC operation.
Command
Bus
CMD
REQDATA
INDX
7
72
20
1
Input
Input/Output The Request Bus is a multiplexed address/data bus used to perform reads (and writes) from
Three State (to) the IPC, and to present search data for lookups.
Request Bus
Index Bus
This bus is used to drive the address of an external SRAM, or feedback Lookup result
information directly to the IPC's controller. Bits [14:0] of the Index Bus contain the encoded
location at which the compare was found.
Output
Three State
This input signifies a valid input request. It is an active high signal that indicates the start of an
IPC operation cycle, it must be active for two CLK2X cycles.
REQSTB
Request Strobe
Input
IPC and SRAM Control:
This is an active high signal that is sent back with data being read from the IPC on the Request
Data Bus, or with data being read from the associated external SRAM. In the case of SRAM
Read
Acknowledge
Read, RDACK is sent with the Index, or up to six cycles after the Index as defined by the
Pipeline Delay (PD) field. In a depth expanded configuration, only the last (lowest priority) IPC
RDACK
1
Output
device in the IPC system must have the LC bit set and will drive the RDACK signal. Refer to
System Configuration Register for details on the PD and LC bits.
This is an active high signal that is sent with the Index, or up to six CLK2X cycles after the Index
as defined by the Pipeline Delay (PD) field. In a depth expanded configuration, only the last
(lowest priority) IPC device in the IPC system musthave the LC bit set and will drive the HITACK
signal. This signal will be driven low if there was no match, high if a match was found. Refer
to System Configuration Register for details on the PD and the LC bits.
Match
Acknowledge
HITACK
VALID
1
1
Output
Output
This is an active high signal that is sent with the Index, or up to six CLK2X cycles after the Index
as defined by the Pipeline Delay (PD) field. In a depth expanded configuration, only the last
(lo west priority) IPC device in the IPC syste m must have the LC bit set and will drive the VALID
signal. It will be driven high upon the completion of a lookup, even if the lookup did not result
in a hit. Refer to System Configuration Register for details on the PD and LC bits.
Valid
Lookup Bit
This is an active low output signal that is driven along with the Index Bus. It is connected to the
CE input pin of a ZBTSRAM or to the OE pin of a PBSRAM. In a depth expanded configuration,
only the last (lowest priority) IPC device in the IPC group must have the LS bit set and will drive
the CE/OE signal. Refer to System Configuration Register for details on the LS bit.
Output
Three State
Chip Enable/
Output Enable
1
1
CE / OE
This is an active low output signal which is driven along with the Index bus. It may be used to
Output
assert the WE pin of an external SRAM. In a depth expanded configuration, only the last (lowest
Write Enable
WE
Three State priority) IPC device in the IPC group must have the LS bit set and will drive the WE signal.
Refer to System Configuration Register for details on the LS bit.
Clock and Initialization:
CLK2X
Clock Input
1
1
Input
Input
All inputs and outputs are referenced to the positive edge of this clock.
Clock Phase
Enable
This signal is used to generate an internal clock at ½ the frequency of CLK2X. A similar external
clock may be optionally generated by the user to clock the external synchronous SRAM.
PHASEN
This pin is used to set the Device ID internally at power up and whenever the RST pin is held
low. In a depth expanded configuration, only the first device in the IPC system needs to be
set high.
Configuration
Address
CONFIGIN
CONFIGOUT
RST
1
1
1
Input
Ouput
Input
This pin is used at power up and when RST is active to set the Device ID. In a depth expanded
configuration, the CONFIGOUT signal is connected to the CONFIGIN signal of the next
subsequent downstream IPC device.
Configuration
Address
This pin must be active (low) during power up. This will force all outputs to a high impedence
condition, as well as clearing the IPC enable (EN) bit in the System Configuration Register. This
function does not initialize the contents of the IPC entries.
Reset
B5325 tbl 01
6.42
5
SignalDescriptionsandPinout
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
SignalDescriptionscontinued
Description
Symbol
Pin Function # Pins
I/O
Depth Expansion:
Match Output is an active high signal that is driven one cycle before the Index is driven on the
bus. This signal signifies that a match has occurred in the IPC. The Match Output signal is active
high and is fed into a Match Input line of all lower priority IPC(s).The Match Output signal is
reference to 2.5V operating characteristic, regardless of selected VDDQ.
Match
Output
MATCHOUT
1
7
Output
Input
The Match Input signal is driven by all upstream Match Output signals. This indicates to all down
stream IPCs that a hit in a higher priority IPC has occurred. This will prevent a lower priority IPC
from driving the Index bus if a higher priority IPC encountered a match.
Match
Input
MATCHIN
JTAG Signals:
Te s t Mo d e
Select
JTAG instruction input. This is 1149 compliant and has Input levels the same as the other input
pins of the device. If set at 2.5V or 3.3V VDDQ This pin has an internal pullup
TMS
TDI
1
1
1
1
1
Input
Input
JTAG data input. This pin has an internal pullup
Test Data Input
Te s t Data
Output
Output
Tristate
JTAG Data output pin. This pin is driven on the high to low edge of Test Clock.
TDO
TCK
A maximum of 10Mhz test clock. This pin has an internal pullup
Test Clock
Input
Input
Asynchronous JTAG Reset. This is an active low signal that will reset only JTAG associated
logic. This will have no affect on the other IPC functional logic. This pin has an internal pullup
JTAG Reset
TRST
Power Supply:
VDD
Core Power
I/O Power
Match Power
I/O Power
Ground
29
26
46
1
Supply
Supply
Supply
Input
2.5V core power supply pins for the device
2.5V or 3.3V I/O supply voltages for the device
VDDQ
VMATCH
1.5V match supply voltage for the device
This is a DC signal that defines the output drive to be either 3.3V or 2.5V. To select 3.3V output
VDDQ Select
drive set V
Select Low (Vss), for 2.5V output drive set V Select High (V ).
DDQ DDQ
DDQ
Vss
Other:
DNU
69
Supply
Common ground pins for IPC supply voltages
Do Not Use
No Connect
9
1
N/A
N/A
Do not connect these pins
This pin is not connected to the die, can be left floating or connected to Vss to minimize thermal
impedance
NC
B5325 tbl 01a
6
SignalDescriptionsandPinout
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
Pin Configuration -304 Ball Grid Array
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
REQ
DATA
18
REQ
DATA
0
VDDQ
VMATCH VMATCH VMATCH
VMATCH
A
B
C
D
E
F
A
B
C
D
E
F
VSS VSS VSS
VDD
VSS VDD VSS VSS VSS
VSS
VSS
VDD TRST VSS VSS VSS
REQ REQ REQ
DATA DATA DATA VMATCH VDDQ
19
REQ REQ
VDDQ DATA DATA
VMATCH VMATCH VMATCH
VMATCH
VMATCH
VMATCH
DNU
TDI VSS VSS VSS
VSS VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16
REQ REQ REQ REQ REQ REQ REQ
DATA DATA DATA DATA DATA DATA DATA VDDQ
14
3
1
REQ
DATA
21
VMATCH VMATCH VMATCH
VSS VSS
VDD
VSS VDD TMS VSS VSS
17
15
12
10
8
6
4
REQ REQ
REQ
REQ REQ REQ REQ REQ REQ
CONFIG
RD-
ACK
VDDQ
VMATCH
SELECT
DATA DATA VDDQ DATA VDDQ VMATCH DATA DATA DATA DATA DATA DATA
VMATCH
TCLK
TDO NC
IN
24
23
20
13
11
9
7
5
2
REQ REQ
DATA DATA
REQ
DATA
22
HIT
ACK
VA LID
VDD
VDD
RST
26
25
REQ
DATA
28
REQ
CE/
OE
DATA VDDQ
27
VDDQ
VDD
VDD
WE
REQ REQ
DATA DATA VDDQ DATA
REQ
CONFIG
OUT
VDDQ
G
H
J
DNU DNU
G
H
J
31
30
29
VMATCH VMATCH VMATCH
REQ REQ
VMATCH VMATCH VMATCH
VSS
VSS
VDDQ DATA DATA
VDDQ
DNU DNU
VDD
VDD
33
32
REQ REQ
DATA DATA
INDX
17
REQ-
STB
INDX INDX
K
K
VDD
VDD
19
18
35
34
75T43100
CMD CMD CMD
INDX
16
INDX
15
304-BGA
VDDQ
L
M
N
L
M
N
VSS
VSS
4
5
6
VSS VDD
VDD MATCH
OUT
VSS
DNU
CMD CLK-
INDX
14
2X
2
PHA- CMD CMD
INDX
VSS
VDDQ
VSS
SEN
3
1
13
REQ REQ
DATA DATA
CMD
0
INDX INDX
10
INDX
12
P
P
VDD
VDD
11
36
37
REQ REQ
VDDQ DATA DATA
INDX INDX
VDDQ
R
T
U
R
T
U
VDD
VDD
8
9
38
39
VMATCH VMATCH VMATCH
VMATCH VMATCH VMATCH
VSS
VSS
REQ REQ
DATA DATA VDDQ DATA
REQ
INDX
5
INDX INDX
6
VDDQ
7
40
41
42
REQ
DATA
43
REQ
DATA VDDQ
44
INDX
3
INDX
4
VDDQ
V
W
V
W
VDD
VDD
REQ REQ
DATA DATA
45
REQ
DATA
49
MATCH
IN
5
INDX INDX
VDD
VDD
1
2
46
REQ REQ
REQ
REQ REQ REQ REQ REQ REQ
MATCH MATCH MATCH
INDX
0
DATA DATA VDDQ DATA VDDQ VMATCH DATA DATA DATA DATA DATA DATA
VMATCH
VMATCH
VMATCH
VMATCH
VMATCH
IN
2
IN
4
IN
6
Y
DNU
DNU
DNU
Y
VSS
VSS
VSS
VDD
VSS
VSS
VSS
47
48
51
58
REQ REQ REQ REQ REQ REQ REQ
DATA DATA DATA DATA DATA DATA DATA VDDQ
60
62
64
66
69
REQ
DATA
50
MATCH
VMATCH VMATCH VMATCH
VMATCH VMATCH VMATCH
VMATCH VMATCH VMATCH
IN
3
AA
AB
AC
AA
AB
AC
VSS VSS
VDD
VDD
VSS VSS
54
56
59
61
63
65
67
REQ REQ REQ
DATA DATA DATA VMATCH VDDQ
52
REQ REQ
MATCH
VDDQ DATA DATA
IN
1
VSS VSS VSS
VSS VSS VSS
VSS
VSS VSS VSS
VSS VSS VSS
55
57
68
70
REQ
DATA
53
REQ
DATA
71
MATCH
IN
0
VDDQ
VMATCH
VDD
VSS VDD VSS VSS VSS
VSS
13
VSS
17
VDD
19
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
18
20
21
22
23
B5325 tbl 02A
6.42
7
SignalDescriptionsandPinout
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
RecommendedDCOperating
Conditions with VDDQ at 2.5V
RecommendedDCOperating
Conditions with VDDQ at 3.3V
Symbol
Parameter
Min.
2.375
1.425
2.375
0
Typ.
2.5
1.5
2.5
Max.
2.625
1.575
2.625
0
Unit
V
Symbol
Parameter
Min.
2.375
1.425
3.135
0
Typ.
2.5
1.5
3.3
Max.
2.625
1.575
3.465
0
Unit
V
VDD
Core Supply Voltage
V
DD
Core Supply Voltage
VMATCH Match Supply Voltage
VDDQ I/O Supply Voltage
V
VMATCH Match Supply Voltage
VDDQ I/O Supply Voltage
V
V
V
VSS
VIH
VIH
VIL
Ground
0
V
VSS
VIH
VIH
VIL
Ground
0
V
____
(2)
____
(2)
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
1.7
VDDQ +0.3
V
Input High Voltage - Inputs
Input High Voltage -I/O
Input Low Voltage
2.0
VDDQ + 0.3
V
____
____
(2)
____
____
(2)
1.7
VDDQ +0.3
0.7
V
2.0
VDDQ + 0.3
0.8
V
-0.3(1)
V
-0.3(1)
V
C5325 tbl 01
C5325 tbl 02
NOTES:
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = VDDQ+1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = VDDQ+1.0V for pulse width less than tCYC/2, once per
cycle.
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Parameter
Commercial
Unit
VTERM
VDD Terminal Voltage
with Respect to GND
V
-0.5 to 3.575
(VDD)
Symbol
Parameter
Cas e Te mpe rature
Ambie nt Te mpe rature
Ground
Commercial
0°C to 90
0°C to 70
0
Unit
°C
°C
V
(2)
tc
VTERM
(VDDQ)
VDDQ Terminal Voltage
with Respect to GND
V
V
V
-0.5 to V
+0.5
DDQ
Te mpe rature
tA
(2)
VTERM
(INPUTS)
Input Terminal Voltage
with Respect to GND
V
S S
-0.5 to V
+0.5
+0.5
DDQ
V
DD
Core Supply Voltage
2.5V ± 5%
2.5 ± 5%
3.3V ± 5%
1.5V±75mV
V
(2)
VTERM
(I/O)
I/O Terminal Voltage with
Respect to GND
-0.5 to V
DDQ
V
DDQ
I/O Supp ly Voltage
V
TBIAS
TSTG
PT
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-55 to +125
TBD
oC
oC
W
V
MATCH
Match Supply Voltage
V
C5325 tbl 04
IOUT
DC Output Current
50
mA
304BGACapacitance
(TA = +25°C, f = 1.0MHz)
C5325 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 0V
Max. Unit
7
7
pF
CI/O
VOUT = 0V
pF
C5325 tbl05
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
8
DCOperatingCharacteristic
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange
(VDD = 2.5V ±5%, VDDQ= 2.5V ± 5% or VDDQ = 3.3V ± 5%)
Symbol
Parameter
Input Leakage Current
Test Conditions
DD = 2.625V, VIN = 0V to VDD
Min.
Max.
Unit
____
|ILI
|ILI
|ILO
VDDQ=2.5V)(2)
VDDQ=2.5V)(2)
VDDQ=3.3V)
VDDQ=3.3V)
|
V
5
µA
(1)
____
JTAG Input Le akage Curre nt
Output Leakage Current
|
V
DD = 2.625V, VIN = 0V to VDD
30
5
µA
V
OUT = 0V to VDDQ, Outputs in High
|
____
____
Impe dance state
µA
V
V
OL
(
Output Low Voltage
I
OL = +6mA, VDDQ = 2.375V
OH = -6mA, VDDQ = 2.375V
OL = +8mA, VDDQ = 3.135V
OH = -8mA, VDDQ = 3.135V
0.4
____
V
OH
OL
OH
(
Output High Voltage
Output Low Voltage
Output High Voltage
I
2.0
V
V
____
V
(
I
0.4
____
V
(
I
2.4
V
C5325 tbl 06
NOTE:
1. The TMS, TDI, TCK, and TRST pins will be internally pulled to VDD if it is not actively driven in the application.
2. The MATCHOUT signal is referenced to 2.5V operating characteristics, regardless of selected VDDQ.
DC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange(1)
(VDD = 2.5V ±5%, VDDQ= 2.5V ± 5% or VDDQ = 3.3V ±5%)
Symbol
Parameter
Test Conditions
66MLookups/sec 50MLookups/sec
Unit
Outputs Open,
Operating Core Power
Supply Current
DD
I
1
DD
V
= 2.625V,
2,900
2,400
mA
(2)
IN
IH
IL
MAX
V > V or < V , f = f
Outputs Open,
3.3V VDDQ Supply
2.5V VDDQ Supply
250
200
250
200
mA
mA
(2)
Operating I/O
Power
Supply Current
DDQ
V
IN IH IL
= 3.465V, V > V or < V , f=fMAX
DD
I
2
Outputs Open,
(2)
DDQ
V
IN IH IL
= 2.625V, V > V or < V , f=fMAX
Operating Match Power
Supply Current
Outputs Open,
MATCH
I
1,700
1,500
mA
(2)
MATCH
IN IH IL
= 1.575V, V > V or < V , f=fMAX
V
C5325 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency.
6.42
9
DCOperatingCharacteristics
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
RegisterDescription
TheIDT75T43100utilizes31registerstoprovideadditionalfeatures
andconvenience. Alltheregistersandtheirrespectiveaddressesare
shown in Table 2.0.
There are fourbasictypes ofregisters:
- 4ConfigurationRegisters
- 4ReplyWidthRegisters(RWRs)
- 8SearchResultRegisters (SRRs)
- 15GlobalMaskRegisters(GMRs)
Theseregistersarediscussedinthefollowingsections.
Table 2.0 — Register Addressing
Address
0000 0000
0000 0001
0000 0010
Register
Function
Address
0001 0000
0001 0001
0001 0010
Register
Function
Global Mask Register 10
Global Mask Register 11
Global Mask Register 12
72 bit Lookup / Write
72 bit Lookup / Write
72 bit Lookup / Write
Identification Register
Size Register
Read only
Read only
Depth Expansion Register
Device Initialization
0001 0011
Global Mask Register 13
72 bit Lookup
0000 0011 System Configuration Register
Device Initialization
Device Operation
Device Operation
Device Operation
Device Operation
0001 0100
0001 0101
0001 0110
0010 0000
0010 0001
0010 0100
0010 0101
0011 0000
0011 0001
0011 0010
0011 0011
Global Mask Register 14
Global Mask Register 15
Global Mask Register 16
Global Mask Register 20
Global Mask Register 21
Global Mask Register 24
Global Mask Register 25
Global Mask Register 30
Global Mask Register 31
Global Mask Register 32
Global Mask Register 33
72 bit Lookup
72 bit Lookup
72 bit Lookup
144 bit Lookup
144 bit Lookup
144 bit Lookup
144 bit Lookup
288 bit Lookup
288 bit Lookup
288 bit Lookup
288 bit Lookup
0000 0100
0000 0101
0000 0110
0000 0111
Reply Width Register 0
Reply Width Register 1
Reply Width Register 2
Reply Width Register 3
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
Search Result Register 0
Search Result Register 1
Search Result Register 2
Search Result Register 3
Search Result Register 4
Search Result Register 5
Search Result Register 6
Search Result Register 7
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
D5325 tbl 01a
D5325 tbl 01
10
RegisterDescription
IDT75T43100
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IP Co-Processor 32K Entries
Commercial Temperature Ranges
Identification Register (IDR)
Address [0000 0000]
DepthExpansionRegister(DER)
Address [0000 0010]
TheIdentificationRegisterisa32-bitreadonlyregister. Theinformation
The Depth Expansion Register is a 32-bit read only register. The
stored in the Identification Register is encoded in the device during information stored in the Depth Expansion Register is hardware con-
manufacturing. Bits 0-7 are used for the die Revision code. The first trolledbytheuseratpowerup. TheCONFIGIN signalisusedtosetthe
released revision code for the 75T43100 is “0000 0001”, this code will DeviceID. Inadepthexpandedconfiguration, eachIPCdevicewillhave
changewitheachnewrevision.Bits8-15definetheIDTImplementation auniqueDeviceIDthatrepresents its positionintheIPCsystem. Bits
number, the 75T43100code is "00000001". Bits 16-31are designated 0-7are usedtodefine the IPCpositioninthe depthexpansion. Bits 8-
IDT's manufacturers ID code, “0000 0000 1011 0011” as assigned by 31 are Reserved and will read as zero's. Figure 2.6c shows the bit
JEDEC. Figure 2.6a shows the bit assignments for the Identification assignmentsfortheDepthExpansionRegister.
Register.
Figure 2.6a — IDR Format
Figure 2.6c — DER Format
31
8
7
0
31
16 15
8
7
0
Re se rve d(1)
De vice ID
Mfgr. #
Impl. #
Re v. #
D5325 tbl 02c
D5325 tbl 02a
NOTE:
1. All reserved bits are read as "0's".
Internal Test Register (ITR)
Address [0000 0001]
TheInternalTestRegisterisa32-bitreadonlyregister. Theinformation
stored in the Internal Test Register is encoded in the device during
manufacturingandisusedbytheIPCdeviceforinternaloperationsonly.
There is noneedforthe usertouse this registerfornormaloperationof
the IPC device. The register can be read and the hex code will read as
following 0x0008 0040. Figure 2.6b shows the Internal Test Register
Format.
Figure 2.6b — ITR Format
31
0
Fo r Inte rnal Ope ratio n Only
D5325 tbl 02b
6.42
11
ConfigurationRegisters
IDT75T43100
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Commercial Temperature Ranges
Reply Width Registers (RWRs)
There are four 64-bit read/write Reply Width Registers. The four
RWRsaddressesarelistedinTable2.1. Eachregisterisdividedintofive
fields. Thereisonefieldassignedforeachofthelookupwidthsasshown
inFigure2.6d. Bits[31:24]areusedfor288-bitlookups;bits[7:0]areused
for144-bitlookups;and bits[15:8]areusedfor72-bitlookups. Thelower
fivebitsoftherequestedLookupwidthareusedtospecifyIndexBusbits
[19:15] for the specify Lookup operation. The other two fields are
reserved,theReservedBits[63:32]and[23:16]needtobewrittento0's
forproper operation ofthe device.
Figure 2.6d — RWR Format
63
32 31
24 23
16 15
8
7
0
Re se rve d(1)
x288 Width
Re se rve d(1)
x72 Width
x144 Width
D5325 tbl 04a
NOTE:
1. All reserved bits should be set to "0's".
During a Lookup operation, bits [65:64] at the Request Bus are
usedtoselectwhichofthefourRWRswillsupplytheinformationofthe
requested Lookup to the Index Bus. Table 2.1 shows how the Reply
WidthRegistersareselected. Inmultiplewidthdatalookupi.e.,144/
288, onlythe last(orleastsignificant)wordofthe Lookupdata is used
todefinewhichRWRtouse.
Table 2.1 — RWR Addresses
Request Data of Lookup
Address
Register
Bit 65
0
Bit 64
0
0000 0100
Reply Width Register 0
0000 0101
0000 0110
0000 0111
Reply Width Register 1
Reply Width Register 2
Reply Width Register 3
0
1
1
1
0
1
D5325 tbl 04b
12
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
System Configuration Register (SCR)
Address [0000 0011]
The System Configuration Register is a 40-bit read/write register
dividedupintoninefieldsusedtoconfiguretheIPC. TheSCRdefinesthe
system Pipeline Delay (PD), IPC configuration (LC, IPC Grp), SRAM
configuration (SR, LS) and IPC Enable (EN). These functions are
describedbelow. Figure2.7shows thebitassignments fortheSystem
ConfigurationRegister.
Figure 2.7— System Configuration Register Format
39
32 31
30
29
28
27
12 11
5 4
2 1
0
Reserved
EN
SR
LS
LC
Reserved
IPC Grp
Reserved
PD
D5325 tbl 03
Reserved Bits [39:32]
Thesebitsarereservedforfutureupgrades. Thesebitsshouldbe
setto"0".
Reserved Bits [27:12]
Thesebitsarereservedforfutureupgrades. Thesebitsshouldbe
setto"0".
EN is the IPC Enable Bit [31].
IPC Grp is the IPC group Bits [11:5].
This bit is cleared to a 0 when RST is pulled low, which forces the
ThesesevenbitsallowtheusertodefinetheIPCgroupswithinthe
outputsonIndexBustogointotri-state.TheIndexBusremainstri-stated IPCsystem. AnIPCsystemcanhaveuptoeightIPC'sinonesystem. An
untiltheenablebitissetto“1”. InadditionCE/OE,WE,VALID,HITACK IPCgroupisdefinedaseitherasingledeviceormultipledevicesthatare
andMATCHOUTsignalswillallremainun-drivenuntilENissettoa“1”. hooked up to a specific bank of SRAM. For the case of a single device
(one group within an IPC system), bits [14:8] should be set to "0". For
multipledevices,refertotheInitializationApplicationNote(AN-269)forthe
settingofthesesevenbits.
SR is the SRAM type Bit [30].
ThisbitdefinesthetypeofSRAMdrivenbytheIPC. A“1”inthisbit
means that ZBT SRAM is on the Index Bus and a “0” means that
Synchronous SRAM is on the Index Bus.
Reserved Bits [4:2]
Thesebitsarereservedforfutureupgrades. Thesebitsshouldbe
setto"0".
LS is the Last SRAM Bit [29].
TheLSbitdefines whichdeviceintheIPCgroupwilldrivetheCE/
OEandWEsignalstotheassociatedSRAM. Italsodefaultsthisdevice PD is the Pipeline Delay Bits [1:0].
todrivingtheIndexBus whenthereis noongoingoperationpreventing
ThesebitsallowtheusertosetthepipelinedelayfortheVALIDand
theIndexBusfromfloating.Thisbitissettoa"1"intheIPCthatisthelast HITACKsignals. Thiswilldefinethenumberofadditionalclockcyclesafter
(lowestpriority)deviceintheIPCgroupandisthesoledeviceintheIPC theIndexissentbeforetheVALIDandHITACKsignalswillbedriven. In
grouptohavethisbitset. AnIPCgroupisdefinedaseitherasingledevice the case ofSRAMRead, PDwillalsodefine whenthe RDACKsignalis
ormultipledevices thatarehookeduptoaspecificbankofSRAM.
driven. Eachpipelinedelayconsistsof2CLK2Xcycles. Thisallowsthe
usertoeitherreceivethesesignalswiththeIndexordelaythesesignals
two,fourorsixCLK2XclockcyclesaftertheIndexfortheSRAMreadcycle.
00 = Driven with Index
LC is the Last IPC Bit [28].
TheLCbitdefineswhichofthedevicesintheIPCsystemwilldrive
theRDACK,VALID,andHITACKsignals.Thisbitissettoa"1"inthedevice
thatisthelast(lowestpriority)deviceintheIPCsystemandisthesoledevice
tohavethisbitset. AnIPCsystemcanhaveuptoeightIPC'sinonesystem.
01 = 1 pipeline delay (2 CLK2X cycles)
10 = 2 pipeline delays (4 CLK2X cycles)
11 = 3 pipeline delays (6 CLK2X cycles)
6.42
13
ConfigurationRegisters
IDT75T43100
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Commercial Temperature Ranges
SearchResultRegisters (SRRs)
Table 2.3 - SRRs Addresses
Address
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
Register
Function
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
TheIPCo-Processorcontainseight32bitreadonlySearchResult
Registers touse forstorage ofthe resultingIndexofa search.
TheSearchResultRegistercontainsinformationstoredbytheIPC
after a Lookup is completed. This informationincludes the 15-bit Index
result,theLookupType,andiftheLookupresultedinavalidhit. Figure
2.8showsthebitassignmentsforaSRR.
Bits0-15areusedfortheIndexoftheassociatedsearchresult. Bits
16-27arereservedandthesebits willreturnto"0"onareadcommand.
Bits 28-30definetheLookuptypeas showninTable2.2. Bit31is used
todefineifavalidhitwasdetected,a"1"signalsthataLookupresultedin
a validhit.
Search Result Register 0
Search Result Register 1
Search Result Register 2
Search Result Register 3
Search Result Register 4
Search Result Register 5
Search Result Register 6
Search Result Register 7
The user can also read the contents of a particular Search Result
Register by directly using the address shown in Table 2.3.
D5325 tbl 05c
Figure 2.8 - SRR Format
31
30
28 27
16
15
14
13
0
(2)
(2)
Valid Hit
Lookup Type
Reserved(1)
A
14
A
13
A
13
Index
A
0
D5325 tbl 05a
NOTE:
1. All reserved bits are read as "0's".
2. Address 13 will be read on Bit 13 and Bit 14.
Table 2.2 - Lookup Type
Result Register [30:28]
Lookup Type
bit 30
bit 29
bit 28
0
1
1
0
0
1
1
0
0
x288 Lookup
x72 Lookup
x144 Lookup
All other bit combinations are
reserved
X
X
X
D5325 tbl 05b
SearchResultRegistersareusedwithLookupinstructions.During
theinitiationoftheLookupinstructions,CMDbits[6:4]oftheCommandBus
willidentifywhichofthe8Resultregisterswillbeusedtostoretheresulted
Index. Table 3.2shows howthe SearchResultRegisters are selected.
14
SearchResultRegisters
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
Table 2.5 — GMRs Addresses
Global Mask Registers (GMRs)
Thereareatotaloffifteen72bitread/writeGlobalMaskRegistersin
the IPCthatare usedduringLookupandWrite operations.
ForlookupsiftheGMRbitissettoa1thiswillenablethecompareto
lookatthisbit,ifthebitissettoa0thisbitbecomesa“X”ordon’tcarebit
inthelookup.
ForwritingifthebitintheGMRissettoa1thedatapresentedonthe
devicedatapinswillbewrittenintothedesiredlocation. IftheGMRbitis
set to a 0, the data that already exists in this stored location will remain
unchanged. All writes are 72 bit only and will use only GMRs 10, 11 or
12.
Address
0001 0000
0001 0001
0001 0010
Register
Function
Global Mask Register 10
Global Mask Register 11
Global Mask Register 12
72 bit Lookup / Write
72 bit Lookup / Write
72 bit Lookup / Write
0001 0011
Global Mask Register 13
72 bit Lookup
0001 0100
0001 0101
0001 0110
0010 0000
0010 0001
0010 0100
0010 0101
0011 0000
0011 0001
0011 0010
0011 0011
Global Mask Register 14
Global Mask Register 15
Global Mask Register 16
Global Mask Register 20
Global Mask Register 21
Global Mask Register 24
Global Mask Register 25
Global Mask Register 30
Global Mask Register 31
Global Mask Register 32
Global Mask Register 33
72 bit Lookup
72 bit Lookup
72 bit Lookup
144 bit Lookup
144 bit Lookup
144 bit Lookup
144 bit Lookup
288 bit Lookup
288 bit Lookup
288 bit Lookup
288 bit Lookup
Table 2.4 shows the mask functions for the Lookup and Write
operations. TheusercanalsoreadthecontentsofaparticularGlobalMask
Register by directly using the address shown in Table 2.5.
Table 2.4 — Mask Function
Operation
Mask Bit Values
Function
1
Compare Bit
Lookup
0
1
0
X, Don't Care
Write to Bit
Write
D5325 tbl 01a
Bit Unaltered
D5325 tbl 08a
TheGMRsareselectedusingtheCMDbits[3:0]andCMDbits[6:4]
oftheCommandBus. RefertotheCommandBusformoredetail. Table
3.1shows howtheGlobalMaskRegisters areselected.
6.42
15
GlobalMaskRegisters
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
BusDescription
Table 3.0 Instruction Set
The IPC utilizes the Command Bus to load the specific operational
instructions. TheCommandBusisa7-bitbuswhichisusedtospecifythe
operationoftheIPCo-Processor.
CMD [3:0]
Instruction
0010
0011
x72 Lookup Pe rforms a x72 lookup in the IPC array.
x144 Lookup Pe rforms a x144 lookup in the IPC array.
TheIPCutilizestwobusinterfacesfordataflow:theRequestBus,and
theIndexBus. TheRequestBusisa72-bitbususedforreadingandwriting
IPCentriesandpresentingLookupdatatothedevice. TheIndexBusis
a20-bitbus,whichis usedtodrivetheresultoftheLookup(orIndex)to
either a SRAM or an ASIC.
Write to Data ce lls , Write to Mas k Ce lls ,
Write
0100
Write to Re giste rs , Write to Exte rnal SRAM
Re ads of Data ce lls, Re ad of Mask Ce lls ,
Re ad
0101
1010
◆ Command Bus
Re ad of Re giste rs , Re ad of Exte rnal SRAM
◆ Request Bus
x288 Lookup Pe rforms a x288 lookup in the IPC array.
◆
Index Bus
This ins truction allows for a dire ct acce s s to
the ass ociate d SRAM on the Inde x Bus . In
this cas e no acce s s to the IPC core will be
A Request Strobe is used to define the start of an IPC operation
sequence. Please refer to the "Instruction/Command Bus Timing
Diagrams" which illustrates the timing for a generic IPC operation.
Additionalsignalsarealsoprovidedforinitialization,SRAMcontrolsand
fordepthexpansion.
SRAM No
1011
made . An acce ss through this path will
Wait Re ad
mimic the same de lays of the IPC to allow
for SRAM acce s s e s to be pipe line d with
re s t of the IPC functio ns .
XXXX
Re se rved
All othe r bit combinations are re s e rve d.
CommandBus
E5325 tbl 02
The Command Bus is used to specify the operation of the IP Co-
Processor. It is divided into two fields, as illustrated in Fig 3.0. The
Instruction field (CMD[3:0]) is used to designate the required Lookup,
Write,ReadortheSRAMNoWaitRead. TheGMRandSRRSelectfield
(CMD[6:4])isusedtoaccessbothaGlobalMaskRegisterandaSearch
ResultRegisterfortherequestedLookup.
Figure 3.0 Command Bus Format
6
4 3
0
GMR and SRR Select
Instruction
E5325 tbl 01
Instruction Field
The Instruction field consists of 4 bits, and defines 6 commands as
showninTable 3.0. The Lookupcommands are operationalinnature,
whereas the Read, Write and SRAM No Wait Read commands are
primarilyusedfortablemaintenance. Theoperationalcommandsutilize
additionalbitsintheCommandBustodefinetheSearchResultRegister
andGlobalMaskRegister,whilethemaintenancecommandsignorethese
additionalbitfields. However,thereisoneexceptionwhendoingaWrite
InstructiontotheDataorMaskcells,theadditionalbitsCMD[6:4]areused
toselecttheGlobalMaskRegisters. AswithallCMOSinputsthesepins
should always be driven (or pulled up), and never be left floating.
GMR and SRR Select Field
TheGMRandSRRselect fieldconsistsof3bitsthatdefinewhichof
theGlobalMaskRegisterandSearchResultRegisterareused. Table
3.1defineswhichGMRscanbeselectedforeachLookupmode.Table
3.2defines whichSRRs canbe selectedtostore the Indexresult.
16
Bus Description & Command Bus Format
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
GMR and SRR Select
Table 3.2 SRR Select
(2nd CLK2X rising edge)
TheCommandBusbits[6:4] areusedfortwofunctions. Onefunction
istospecifywhichGlobalMaskRegister(s) tousefortheWrite(Data/Mask)
andLookupcommands. TheotherfunctionistospecifywhichSearch
ResultRegister(SRR)willstoretheresultingIndexofthesearch.
TheCommandBusbits[6:4]aresampledontherisingedgeofeach
CLK2X. The Global Mask Register(s) are selected on the 1st CLK2X
cycle,followedbytheSearchResultRegistersonthe2ndCLK2Xcycle.
TheGlobalMaskregistersareusedtomaskoutthespecifiedbitsin
theRequestBuswhenperforminglookupsandwrites. For72-bitlookups
thereare8scenarios(7GMRsand1NoMask),for144-bitlookupsthere
are3scenariosand for288-bitlookupsthereare2scenarios available.
All writes are 72-bit only and will use GMRs 10, 11 and 12 only.
TheSearchResultRegistersareusedtostoretheresultingIndexof
asuccessfullookupasspecifiedbytheCommandBusduringaLookup
command. Asubsequent IndirectWrite(orRead) commandcanspecify
whichSearchResultRegisterwillsupplytheaddressforthe(Data/Mask)
array.
Selected
Mode
CMD [3:0]
CMD [6:4]
SRR Selected
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
SRR 0
SRR 1
SRR 2
SRR 3
SRR 4
SRR 5
SRR 6
SRR 7
SRR 0
SRR 1
SRR 2
SRR 3
SRR 4
SRR 5
SRR 6
SRR 7
SRR 0
SRR 1
SRR 2
SRR 3
SRR 4
SRR 5
SRR 6
SRR 7
x72 bit
Lookup
0010
x144 bit
Lookup
0011
Table 3.1 GMR Select
(1st CLK2X rising edge)
Selected
Mode
CMD [3:0] CMD [6:4]
GMR Selected
000
001
010
GMR 10 (use for Write)
GMR 11 (use for Write)
GMR 12 (use for Write)
GMR 13
011
x72 bit
Lookup
0010
100
GMR 14
x288 bit
Lookup
1010
101
110
111
000
GMR 15
GMR 16
No Mask
GMR 20, GMR 21
GMR 24, GMR 25
No Mask
x144 bit
Lookup
E5325 tbl 04
0011
1010
001
111
XXX
All other bit combinations are
reserved
000
111
GMR 30, GMR 31, GMR 32, GMR 33
No Mask
x288 bit
Lookup
XXX
All other bit combinations are
reserved
E5325 tbl 03a
6.42
17
GMR and SRR Select
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
RequestBus
TheRequestBusisa72-bitbus.Oneofitstwomainfuncitionsistosupply
the data forthe Lookupcommand. The orderofthe data suppliedfora
72-bit,144-bitand288-bitLookupcommandsisspecifiedinFigure3.1.
Figure 3.1 Request Bus for Lookup Commands
71
0
Available for 2 Clk2x Cycles
72 Bit Lookup
143
287
72 71
0
Available in 1st Clk2x Cycle
Available in 2nd Clk2x Cycle
144 Bit Lookup
216 215
144 143
72 71
0
1st Clk2x
2nd Clk2x
3rd Clk2x
4th Clk2x
288 Bit Lookup
E5325 tbl 05
ForallotherReadandWriteCommands,theRequestBusisusedto
specifytheaddressfollowedbytherelevantdata.
For Read and Write commands of the Data cells, Mask cells and
Registers. TheformatoftheRequestBusisillustratedinthetoppartof
Figure 3.2. Each of the fields are described on the next page.
ForSRAMRead,SRAMWriteandSRAMNoWaitReadcommands,
theformatoftheRequestBusisillustratedinthebottompartofFigure3.2.
Note:Forallcommands,theSAMEADDRESSmustbedrivenonRequest
Bus Bit14andRequestBus Bit15.
Figure 3.2 Format of Address for Request Bus
INSTRUCTION TYPE
71
34 33
26 25
24 23
22
21
20
17 16
15 14
1
0
d(1)
0
Read & Writes
of Data, Mask
& Registers
Access
Typ e
GMR
Select
0:Direct
1:Indirect
SRR
Address
(2)
Reserved(1)
Reserved(1)
Device ID
A14 A13
Reserve
(2)
Select
A13
A0
71
34 33
26 25
24 23
21 20
16 15 14
SRAM Read,
Write and No
Wait Read
Access
Typ e
Address
Address
(3)
Device ID
Reserved(1)
A14
(3)
A19
A15
A14
A0
E5325 tbl 06
NOTES:
1. Reserved bits should be set to "0's".
2. For Read and Write commands of Data, Mask and Registers, Address 13 must be driven on Bit 14 and Bit 15.
3. For SRAM Write, SRAM Read and SRAM No Wait Read commands, Address 14 must be driven on Bit 14 and Bit 15.
18
RequestBusFormat
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◆ Device ID
Table 3.8 GMR Select
ThisfeatureisneededwhenusingmultipleIPCsfordepthexpansion.
The Device ID is defined at power up and automatically assigned after
Reset. Table3.6showswhichIPCisaccessedusingDeviceIDfield. In
thecaseofaReadofalltheIPC's,onlyIPC0willdrivetheRequestBus.
Request Bus
GMR Select for a Write Operation
Bit 23
Bit 22
0
0
1
1
0
1
0
1
GMR 10
GMR 11
Table 3.6 Device ID
GMR 12
Request Bus
IPC Device
No Masking
Accessed
bit 33 bit 32 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26
E5325 tbl 10
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
0
1
◆ Direct/Indirect
If“0”,indicatesthattheaddresstothe(Data/Mask)arraywillcomefrom
theAddressfieldoftheRequestDatabus. If“1”,indicatesthattheaddress
to the (Data/Mask) array will come from the Search Result Register as
specifiedintheSRRSelectfieldoftheRequestBus.
2
3
4
◆ SRR Select
5
ThisfieldisonlyusedforIndirectaddressing. ItspecifieswhichSearch
ResultRegisterwillbeusedtosupplytheaddresstothe(Data/Mask)array
as shown in Table 3.9.
6
7
All
Table 3.9 SRR Select
All other bit
combinations
are reserved
X
X
X
X
X
X
X
X
Request Bus
SRR Select
Bit 20 Bit 19 Bit 18 Bit 17
E5325 tbl 07
◆ Access Type
There are four possible access types: a) Data array; b) Mask array; c)
SRAM; and, d) Register, as specified in Table 3.7.
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
SRR 0
SRR 1
SRR 2
Table3.7 AccessType
SRR 3
SRR 4
Request Bus
Access Type
Bit 25
SRR 5
Bit 24
SRR 6
SRR 7
0
0
1
1
0
1
0
1
Internal IPC Reg
Data Array
All other bit combinations are reserved
E5325 tbl 11
Mask Array
External SRAM
E5325 tbl 08
◆ Address
◆ GMR Select
ThisfieldspecifiestheaddressoftheAccessTypewhenusingDirect
addressing(asspecifiedbytheDirect/Indirectbit). Theaddressmaybe
usedtoaccessthe(Data/Mask)array,externalSRAM,oraninternalIPC
register. TheaddressdecodemapoftheinternalIPCregistersisfound
in Table 2.0.
ThisfieldisonlyusedtospecifywhichofthethreeGMRswillbeused
inawriteoperation. Therearefourpossibleoptions ofGMRstousefor
a write operation, as shown in Table 3.8.
InaWriteoperation,theGMRselecteddefineswhichbitsinthearray
willbeupdated.ForeachbitintheselectedGMRthatissettoa“1”,data
fromtheRequestBuscorrespondingtothisbitlocationwillbewritteninto
thearray.ForallotherbitsintheselectedGMRthatarea“0”,datainthe
arraycorrespondingtothisbitlocationwillremainunchanged.
6.42
19
RequestBusFormat
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IndexBus
TheIndexBusisa20-bitbusdividedintotwofields.Itconsistsofthe CONFIGOUT
following: a) ADDRESS; and b) RWB as illustrated in Fig 3.4.
Inadepthexpandedconfiguration,theCONFIGOUTsignalisused
to set the Device ID in the following downstream IPC devices. The
◆ ADDRESSBits [14:0]
This is the location where the resulting Index is placed from the CONFIGOUT signal is connected to the CONFIGIN signal of the next
requestedsearch. TheADDRESSfieldcontainstheencodedlocationat subsequentdownstreamdeviceintheIPCsystem.
whichthecomparewasfoundforLookupcommand. Itisusedtoaccess
thecorrespondingassociativememoryinanexternalSRAM. Whenwide CLK2X
lookupsareperformed,thecorrespondingleastsignificantbitswillalways
be zero (bit 0 for 144-bit, bits 1:0 for 288-bit).
◆ RWBBits[19:15]
TheCLK2XistheclockthatoperatestheIPCdevice.Itshouldrunat
twice the lookupfrequency(133MHzfor66Mlookups/sec).
TheRWBbitsareassociatedwiththeLookuprequested. Theseare Phase Enable (PHASEN)
thefivelowerbitsoftherequestedLookupwidththatareprogrammedin
theReplyWidthRegisters.
ThePhaseEnablesignalisusedtosynchronizetheinternalIPCclock
totheclockoftheexternalSRAM.PleaserefertotheClockTimingdiagram
foranillustrationofthissignal.
Figure 3.4 Index Bus
Reset (RST)
19
15 14
0
TheResetsignalinitializestheIPCdevice.Itmustbelow,andremain
lowfor32CLK2XcyclesafteravalidclockhasbeengeneratedtotheIPC
device.
RWB
ADDRESS
E5325 tbl 09
Bypass Mode
Read Acknowledge signal (RDACK)
WheninstructingtheIPCtodoaSRAMWrite,SRAMRead,orSRAM
NoWaitRead,theIPCwillgrabthe19AddressbitsofftheRequestBus
anddirectlypassthemto theIndexBus. TheIPCautomaticallyaddsthe
appropriatenumberofpipelinedelaysneededtoinsurethattheinstruction
hasthesamepipelinedelaysasanyotherinstruction.
TheReadAcknowledgesignalisusedtoidentifythecycletimeofvalid
databeingdrivenduetoaRead(IPCreg,DataorMaskarray,orexternal
SRAM)command. Inthe case ofSRAMRead, RDACKis sentwiththe
IndexoruptothreePipelineDelays(PD)aftertheIndex. Note:thissignal
isnotgeneratedinconjunctionwithanSRAMNoWaitReadcommand.
Chip Enable/Output Enable signal (CE/OE)
TheChipEnable/OutputEnablesignalisdesignedtobeconnectedto
theOEpinonSingleCycleDe-selectpipelinedburstSRAMs(PBSRAMs),
and the CE pin on ZBT SRAMs and Double Cycle De-select pipelined
burstSRAMs(PBSRAMs).
Additional Signals
Match Output (MATCHOUT)
The Match Output signal is used for depth expanding multiple IPC
devices.ItisdrivenonecyclebeforetheIndexBusisdriven,andshould
be connected to a Match Input pin on all lower priority IPC devices. All
downstreamIPCdevicesusethissignaltopreventthemfromdrivingthe
Index Bus.
Write Enable signal (WE)
TheWriteEnablesignalisdesignedtobeconnecteddirectlytotheWE
pin on PBSRAMs and ZBT SRAMs.
Valid signal (VALID)
Match Input (MATCHIN 0-6)
TheValidsignalindicateswhenaLookupcommandhascompleted
regardlessofwhetherthelookupresultedinamatch.Thetimingforthis
signalisprogrammablebasedonthePDbitintheSystemConfiguration
Register.ItcanbeassertedasearlyasconcurrentlywiththeIndex,orup
to three Pipeline Delays (PD) after the Index.
There are seven Match Input signals that correspond to the seven
(possible)upstreamIPCdevices.WhenusingtheIPCinamultipledepth
expanded configuration, each upstream IPC device must prevent the
lower priority downstream IPC device from driving the external SRAM
(and control signals) if a match was found in lower priority and higher
prioritydevice(s)whenperforminga lookupoperation.
Match Acknowledge signal (HITACK)
TheMatchAcknowledgesignalindicateswhenaLookupcommand
resultedinamatch.Thetimingforthissignalisprogrammablebasedon
thePDbitintheSystemConfigurationRegister.Itcanbeassertedasearly
asconcurrentlywiththeIndex,oruptothreePipelineDelays(PD)after
the Index.
CONFIGIN
The CONFIGIN signal is used to set the Device ID in the Depth
ExpansionRegister. ThisisdoneatpoweruporwhenevertheRSTpin
is held Low. Only the first device in the IPC system should have its
CONFIGIN signal set high. In a depth expanded configuration, the
CONFIGINsignalisconnectedtotheCONFIGOUTsignaloftheprevious
upstreamdeviceintheIPCsystem.
20
Index Bus Format and Additional Signals
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Initialization
Hot Reset
Ahotresetconditionoccurswhentheresetpinispulledlow,sometime
TheIPCrequires thattheResetsignal(RST)beactive(Low)upon
powerupandremainlowuntilboththepowersuppliesandtheclocksignals after the device had been in use and no power sequencing has taken
becomestable.Inaddition,atpowerup theJTAGReset(TRST)pinmust place. TheRSTpinshouldbeheldlowfortenclockcycles tocomplete
also be low. The IPC will respond to the RST signal in both an the proper re-initialization. In this case the data in the memory is not
asynchronous andsynchronous manner.
corrupted. HoweverthestatestoredintheDepthExpansionRegisterand
At Reset, the IPC will respond to the reset by asynchronously tri- SystemConfigurationRegister must bere-initialized. Thesetworegisters
statingtheI/Opinsandoutputpins,whichpreventsbuscontentionfrom willbeclearedduetotheapplicationoftheresetsignal. AfterRSTpingoes
occurring between IPC devices or the IPC and another device.
highwaitsixteenCLK2XcyclestoallowfortheDeviceExpansionRegister
TheIPCwillcomeoutofaresetconditionsynchronously. TheIPC tobere-configured,nextre-initializetheSystemConfigurationRegisterto
requirestheRSTsignaltobeactive(Low)andtheCLK2XandPHASEN thedesiredstateandresumeoperation. The registersandData andMask
signalsbestableforthirty-twoclockcyclestoinsureproperinitialization. Arrays are affected by a Hot Reset as shown in Table 4.1.
The internallogicofthe IPCis dependentonthe clocktobe presentfor
thedevicetobeinitialized. Thiswillaffectinternalstatemachinesandcertain
registers.
Table 4.1 Condition after Hot Reset
Array / Register
De pth Expans ion Re giste r
Data and Mask Arrays
Contents
Mus t be Re-programme d
Not affe cte d
Cold Reset
Acoldresetconditionoccurswheneverpoweristobeappliedtothe
IPC. Inthis case the IPCwillhave nodefineddata ineitherthe Data or
Mask arrays. In addition the Depth Expansion Register, Global Mask
Registers,andSearchResultRegisters willalsohaveundefineddata.
ResethasnoaffectontheIdentificationandSizeRegisters.The registers
andData andMaskArraysareaffectedbyaColdResetasshowninTable
4.0.
Global Mask Re gis te rs
Reply Width Re giste rs
Not affe cte d
A ll b its s e t to '0'
Mus t be Re-programme d
Sys te m Configuration Re giste r
Se arch Re sults Re gis te rs
Not affe cte d
Not affe cte d
Ide ntification Re giste r
Size Re giste r
Table 4.0 Condition after Cold Reset
F5325 tbl 01b
Array / Register
Contents
Unde fine d
Mus t be programme d
De pth Expans ion Registe r
Unde fine d
Mus t be programme d
Data and Mask Arrays
Global Mask Re gisters
Re ply Width Re gis te rs
Unde fine d
Mus t be programme d
Unde fine d
Mus t be programme d
Syste m Configuration Registe r
Se arch Re sults Re gisters
Unde fine d
Ide ntification Re giste r
Size Re gister
Not affe cte d
F5325 tb l 01a
6.42
21
Initialization
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Initialization Sequence of a Single Device
Step 1
Step 5
After RST goes high wait 16 CLK2X cycles to allow for the internal
The Global Mask Registers (GMRs) also do not have any defined
initializedstate. IftheuserintendsonusingtheGMRsthentheappropriate
register(s)mustbeinitialized. IftheuserdoesnotintendonusingtheGMRs,
noinitializationisrequired.
circuitrytoconfiguretheDeviceExpansionRegister.
Step 2
TheusermustinitiallysettheLC bitintheSystemConfigurationRegister
tostartthehandshakingofsignalsbacktotheASIC/FPGA. Thisenables Step 6
theRDACK,HITACKandVALID signalstobedriven. TheEnable(EN)
The Reply Width Registers (RWRs) also do not have any defined
bitintheSystemConfigurationRegisterisinitiallyresettozero. IftheASIC/ initializedstate. Ifthereisaneedtousetheseregistersthentheusermust
FPGAdoesnotrequirethehandshakesignalsduringinitializationthenthe initializetheappropriateregister(s). Iftheuserdoesnotintendonusing
LCbitdoesnothavetobeenableduntiltheSystemConfigurationRegister theRWRs,noinitializationisrequired.
isconfigured.
Step 7
Step 3
ThefinalprocedureistoupdatetheSystemConfigurationRegisterto
The user must initialize the entire Data array with 0’s. It should be enablethedeviceforoperation. TheIndexBuswillremainintri-stateuntil
realizedthatiftheentirearrayisnotinitializedtoaknownstateafalsematch theENbitissettoa"1"intheSystemConfigurationRegister. AftertheSCR
mightberealizedatanun-initializedlocation.
is configuredthe device is readyforoperation.
Step 4
Note:
The user must initialize the entire Mask array with 1’s. It should be
The Search Result Registers will be dynamically changing as the
realizedthatiftheentirearrayisnotinitializedtoaknownstateafalsematch deviceisused. InfacttheSearchResultRegistersarereadonlyregisters
mightberealizedatanun-initializedlocation.
andcannotbeinitializedthroughaIPCwriteoperation. Itisimportantto
realizethattheseregistersinitializeinarandomstateandshouldnotbe
useduntilaftertheyhavebeenupdatedfromapreviousLookupoperation.
Foramoreindepthprocedureonhowtoinitializeasingledeviceor
multipledevicesrefertotheapplicationnote(AN-269),"InitializationofIDT
75T43100 IP Co-Processor."
Table4.2InitializationSequence
Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Wait 16 CLK2X cycles
Designate Last IPC by setting LC bit in SCR
Write 0's to Data Array
Write 1's to Mask Array
Configure the GMRs that are to be used
Configure the RWRs if needed
Finish the Configuration of the SCR
F5325 tbl 02
22
Initialization
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AC Electrical Characteristics
(VDD = 2.5V +/-5%, TA = 0 TO 70°C)
66M Lookups
50M Lookups
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
Clock Parameters
____
____
____
____
CYC
t
CLK2X Cycle Time
7.5
3.0
10
ns
ns
(1)
CLK2X High Pulse Width
CLK2X Low Puls e Width
3.0
t
CH
____
____
(1)
CL
3.0
3.0
ns
t
Output Parameters
t
CRD
Clock High toIPC Re ad Valid Data
Clock High to Data Change
1.0
1.0
5.0
1.0
1.0
5.0
ns
ns
____
____
t
CDC
____
____
(2)
CLZ
Clo ck Hig h to Outp ut Active
Clock High to Data High-Z
0
0
ns
ns
t
(2)
CHZ
1.0
3.5
1.0
3.7
t
t
CRAK
Clock High to RDACK Active
Clock High to Inde x Valid
Clock High to Match Data Valid
Clock High to Data Valid
1.0
5.0
5.0
5.0
5.0
1.0
5.0
5.0
5.0
5.0
ns
ns
ns
ns
____
____
t
CIV
t
CMDV
1.0
1.0
1.0
1.0
t
CDV(3)
Set Up Parameters
____
____
____
____
t
S U
Input Se tup Tim e
1.8
2.3
1.8
2.3
ns
ns
t
S R
RST Se tup Time
Hold Parameters
____
____
____
____
t
H
Input Hold Tim e
0.5
0.5
0.5
0.5
ns
t
HR
ns
RST Hold Time
H5325 tbl 01
NOTES:
1. Measured as HIGH above VIH and Low below VIL.
2. Transitionismeasured +200mVfromsteady-state.Thisparameterisguaranteedbydevicecharacterization,butnotproductiontested.
3. This parameterapplies tothe CE/OE, WE, HITACKandVALIDsignals.
AC Test Conditions
(VDDQ = 2.5V / 3.3V)
AC Test Load
V ddq/2
Input Pulse Levels
0 to V
DDQ
50 OH M
Z0
= 50 Ohm
Input Rise/Fall Times
1.5ns
(V /2)
H 532 5 drw 0 0
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
DDQ
(V /2)
DDQ
See Figure
H5325 tbl 03
6.42
23
ACOperatingCharacteristics
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ClockTiming
t
t
15
t
t
t
t
t
t
13
(CLOCKs)
14
8
9
10
11
12
tCH
tCYC
CCL2X
tCL
tSU
tSU
PHASEN
tH
t
H
CCLK(1)
tSR
RST
(Note 2)
tHR
H5325 drw01
NOTES:
1. CCLK is an internal signal not seen by the user.
2. See Reset/Initialization Sequence Diagram for reset.
24
TimingDiagrams
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Instruction/CommandBusTiming
t
t
t
t
(Instruction Timing)
0
1
2
3
CLK2X
(1)
CCLK
Note 2
t
t
SU
SU
.
Note 4
REQSTB
CMD[3:0]
CMD[6:4]
t
H
t
SU
t
SU
COMMAND
Note 4
t
H
t
t
t
SU
SU
SU
SRR
REGISTER
GMR
REGISTER
Note 4
t
H
t
H
t
t
t
SU
SU
SU
72 BIT
DATA B
(Note 3)
72 BIT
DATA A
72 BIT
DATA C
REQDATA
t
t
H
H
H5325d02
NOTES:
1. CCLK is an internal signal not seen by the user.
2. The Request Strobe needs to be High at t1. It does not initiate a new command. However
at time t2 it will be sampled and if High will initiate a new command.
3. For an IPC Writes and 72 bit Lookups, Data B is ignored.
4. Depending on the current and following operations these signals are driven High, Low
or Don't Care.
6.42
25
TimingDiagrams
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Output Timing (with IPC Read)
t
t
t
t
t
t
t
t
t
t
9
(IPC READ)
0
1
2
3
4
5
6
7
8
CLK2X
CCLK
t
SU
REQSTB
CMD[3:0]
CMD[6:4]
t
H
t
SU
IPC R E AD
t
H
t
t
(
CHZ
(MAX.)
CRD
t
)
MAX.
SU
Read Data
REQDATA
Address
t
t
H
t
CLZ
(MIN.)
CDC
(MIN.)
INDX
tCRACK
(
)
MAX.
RDACK
tCRACK
(MIN.)
H5325 drw 03
Don't Care
Driven HIGH or LOW, but to an indeterminate state.
LOW impedance state.
26
TimingDiagrams
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Output Timing (with ZBT SRAM)
(OUTPUT TIMING for
all commands except
IPC Read and Write)
t
t
t
t
t
t
t
t
16
t
t
t
17
8
9
10
11
12
13
14
18
15
CLK2X
(1)
CCLK
tCIV
(MAX.)
VALID INDEX
NOTE 2
INDX
NOTE 2
tCDC
(MIN.)
tCMDV
(MAX.)
.
MATCHOUT
tCMDV
(MIN.)
tCDV
(MAX.)
(4)
CE/OE
tCDV
(MIN.)
tCDV
(MAX.)
NOTE 3
WE
tCDV
(MIN.)
(NOTE 5)
SRAM READ or
WRITE DATA
SRAMDATA
t
CR AK
(MA X.)
(7)
NOTE 3
NOTE 3
NOTE 3
RDACK
tCRAK
(MIN.)
tCDV
(MAX.)
HITACK
tCDC
(MIN.)
Pipeline Delay (PD)
(NOTE 6)
PD=0
PD=1
PD=2
PD=3
tCDV
(MAX.)
VALID
tCDC
(MIN.)
H5325 d04
NOTES:
1. CCLK is an internal signal not seen by the user.
2. The Index Bus is driven but to an indeterminate state.
3. Signal will drive LOW or HIGH depending on command; see sequence diagram for state.
4. This pin will be tied to the CE input of ZBT and OE input will be tied LOW.
5. Refer to the SRAM datasheet for timing specifications.
6. HITACK and VALID signals can be valid based on the rising edge of CLK2X at time tCDV dependent on the Pipeline Delay (PD) value that
is programmed into the System Configuration Register (SCR). These signals will drive for 2 CLK2X cycles. A PD value of 3 is shown for
clarity. Typically, the PD would be set to 2.
7. RDACK signal can be valid based on the rising edge of CLK2X, at time tCRAK, dependent on the Pipeline Delay (PD)
value that is programmed into the System Configuration Register (SCR). This signal will drive for 2 CLK2X cycles. A PD value of 3 is shown
for clarity. Typically, the PD would be set to 2.
6.42
27
TimingDiagrams
IDT75T43100
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Output Timing (with Synchronous Pipeline Burst)
28
TimingDiagrams
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Reset/InitializationSequence
6.42
29
SequenceDiagrams
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IPC Read (Register, Data, Mask)
30
SequenceDiagrams
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IPC Write (Register, Data, Mask)
t
t
t
t
t
t
t
t
7
(IPC WRITE)
CLK2X
0
1
2
3
4
5
6
(1)
CCLK
REQSTB
CMD[3:0]
CMD6:4]
REQDATA
INDX
NOTE 3
IPC WRITE
COMMAND
NEXT COMMAND
NEXT COMMAND
ADDRESS OR DATA
WRITE ADDRESS
WRITE DATA
NOTE 2
RDACK
HITACK
VALID
I5325 drw03
NOTES:
1. CCLK is an internal signal not seen by the user.
2. The Index Bus is driven, but to an indeterminate state.
3. Next command can be initiated as early as the cycle t4.
6.42
31
SequenceDiagrams
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SRAM Read (ZBT)
32
SequenceDiagrams
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SRAM Write (ZBT)
6.42
33
SequenceDiagrams
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SRAM No Wait Read (ZBT)
34
SequenceDiagrams
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SRAMRead(PBSRAM)
6.42
35
SequenceDiagrams
IDT75T43100
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B
SRAM Write (PBSRAM)
36
SequenceDiagrams
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SRAM No Wait Read (PBSRAM)
6.42
37
SequenceDiagrams
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
72-Bit Lookup (with ZBT SRAM)(5)
38
SequenceDiagrams
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
144-Bit Lookup (with ZBT SRAM)(5)
6.42
39
SequenceDiagrams
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
288-Bit Lookup (with ZBT SRAM)(5)
40
SequenceDiagrams
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
72 Bit Lookup Followed by an IPC Write (with ZBT SRAM)(5)
6.42
41
SequenceDiagrams
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
JTAGInterfaceSpecification
JCYC
t
t
JR
JF
t
t
JCL
t
JCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
3)
(
x
TRST
M5325 drw 01
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST should be driven low.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
____
____
____
ScanRegisterSizes
JCYC
t
JCH
t
ns
Register Name
Bit Size
JCL
t
40
ns
Instruction (IR)
Bypass (BYR)
4
1
3(1)
ns
____
JR
t
3(1)
ns
____
JF
t
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
____
JRST
t
100
ns
Note (1)
____
I5325 tbl 03
JRSR
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
100
ns
____
JCD
t
20
ns
NOTE:
____
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JDC
t
0
ns
____
____
JS
t
15
15
ns
JH
t
JTAG Hold
ns
I5325 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (stated earlier in this document) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
42
JTAGInterfaceSpecification
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
JTAG Identification Register Definitions
Instruction Field
Revision Number (31:28)
Value
0x1
Description
Reserved for version number
Defines IDT part number
IDT Device ID (27:12)
0x200
0x33
1
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
I5325 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5325 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS and TRST.
6.42
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JTAGInterfaceSpecification
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
Package Diagram Outline - 304 Ball Grid Array
44
PackageDiagramOutline
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
OrderingInformation
IDT XXX
Device
S
XX
X
X
Power
Speed
Package
Type
BS304
304 Ball Grid Array (BGA)
50
66
Mega Lookups per second
75T43100
,
L5325 drw 01
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
ipchelp@idt.com
800-754-4555
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
45
OrderingInformation
IDT75T43100
Advance Information
IP Co-Processor 32K Entries
Commercial Temperature Ranges
RevisionHistory
REV
DATE
PAGES
DESCRIPTION
00
05/04/2001
1 - 46
Advance Information Datasheet, Public Release
46
RevisionHistory
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