IDT77V1253L25PGI8 [IDT]
ATM Network Interface, 1-Func, CMOS, PQFP144, 28 X 28 MM, PLASTIC, QFP-144;
| 型号： | IDT77V1253L25PGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ATM Network Interface, 1-Func, CMOS, PQFP144, 28 X 28 MM, PLASTIC, QFP-144 ATM 异步传输模式 |
| 文件： | 总44页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TRIPLE PORT PHY (PHYSICAL LAYER)
IDT77V1253
FOR 25.6 AND 51.2 MBPS ATM NETWORKS
FEATURES:
DESCRIPTION:
• Performs the PHY-Transmission Convergence (TC) and Physical
Media Dependent (PMD) Sublayer functions for three 25.6 Mbps
ATMchannels
• Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
• Also operates at 51.2Mbps
The IDT77V1253 is a member of IDT's family of products supporting
AsynchronousTransferMode(ATM)datacommunicationsandnetworking.
TheIDT77V1253implementsthephysicallayerfor25.6MbpsATM,connect-
ingthreeserialcopperlinks(UTPCategory3)tooneATMlayerdevicesuch
asaSARoraswitchASIC. TheIDT77V1253alsooperatesat51.2Mbps,and
iswellsuitedtobackplanedrivingapplications.
• UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface
• 3-Cell Transmit & Receive FIFOs
• LED Interface for status signalling
The 77V1253-to-ATMlayerinterfaceisselectableasoneofthreeoptions:
16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or triple 4-bit DPI
(DataPathInterface).
• Supports UTP Category 3 physical media
• Interfaces to standard magnetics
TheIDT77V1253isfabricatedusingIDT'sstate-of-the-artCMOStechnol-
ogy,providingthehighestlevelsofintegration,performanceandreliability,with
thelow-powerconsumptioncharacteristicsofCMOS.
• Low-Power CMOS
• 3.3V supply with 5V tolerant inputs
• 144-pin PQFP Package (28 x 28 mm)
FUNCTIONAL BLOCK DIAGRAM - UTOPIA LEVEL 2 MODE
TxREF
TxCLK
TxDATA[15:0]
+
-
Driver
Tx 0
Rx 0
TxPARITY
TxSOC
5B/4B
Encoding/
Decoding
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
P/S and S/P
NRZI
Clock/Data
Recovery
+
-
TxEN
TxCLAV
TxADDR[4:0]
PHY-ATM
Interface
MODE[1:0]
(UTOPIA or DPI)
RxADDR[4:0]
RxCLK
RxDATA[15:0]
RxPARITY
RxSOC
+
-
Driver
Tx 1
Rx 1
5B/4B
Encoding/
Decoding
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
P/S and S/P
NRZI
Clock/Data
Recovery
+
-
RxEN
RxCLAV
INT
RST
+
-
RD
Driver
Microprocessor
(Utility Bus)
Interface
Tx 2
Rx 2
5B/4B
Encoding/
Decoding
WR
CS
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
P/S and S/P
NRZI
Clock/Data
Recovery
+
-
AD[7:0]
ALE
3
3
OSC
RxREF
RxLED[2:0] TxLED[2:0]
4781 drw 01
DECEMBER 2004
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc.
1
2004 Integrated Device Technology, Inc. All rights reserved. Product specification subject to change without notice.
DSC-4781/2
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
PINCONFIGURATION:
VDD
GND
TX0-
TX0+
VDD
MM
MODE1
MODE0
RXREF
TXREF
GND
DNC
TXLED2
TXLED1
TXLED0
VDD
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXDATA8
TXDATA9
TXDATA10
TXDATA11
TXDATA12
TXDATA13
TXDATA14
TXDATA15
TXPARITY
TXEN
1
108
107
106
105
104
103
102
101
100
99
VDD
2
GND
DNC
DNC
VDD
DA
3
4
5
6
7
SE
8
AD7
AD6
AD5
AD4
GND
AD3
AD2
AD1
AD0
VDD
ALE
CS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
96
95
94
77V1253
144-PQFP
PU-144
93
92
91
90
89
88
87
RD
WR
RST
GND
INT
VDD
GND
DNC
RXLED2
RXLED1
RXLED0
VDD
86
85
84
83
82
81
80
79
78
77
GND
76
RXDATA0
RXDATA1
RXDATA2
RXDATA3
75
TXSOC
TXADDR4
74
73
4781 drw 02
Figure 1. Pin Assignments
2
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 1 — SIGNAL DESCRIPTIONS
LINE SIDE SIGNALS
SIGNAL NAME
RX0+,-
PIN NUMBER
139, 138
133, 132
121, 120
4, 3
I/O
In
SIGNAL DESCRIPTION
Port 0 positive and negative receive differential input pair.
Port 1 positive and negative receive differential input pair.
Port 2 positive and negative receive differential input pair.
Port 0 positive and negative transmit differential output pair.
Port 1 positive and negative transmit differential output pair.
Port 2 positive and negative transmit differential output pair.
RX1+,-
In
RX2+,-
In
TX0+,-
Out
Out
Out
TX1+,-
144, 143
110, 109
TX2+,-
UTILITY BUS SIGNALS
I/O
SIGNAL NAME
PIN NUMBER
SIGNAL DESCRIPTION
AD[7:0]
101, 100, 99, 98,
96, 95, 94, 93
In/Out
Utility bus address/data bus. The address input is sampled on the falling
edge of ALE. Data is output on this bus when a read is performed. Input
data is sampled at the completion of a write operation.
ALE
91
In
Utility bus address latch enable. Asynchronous input. An address on the
AD bus is sampled on the falling edge of ALE. ALE may be either high
low when the AD bus is being used for data.
90
89
In
In
Utility bus asynchronous chip select. CS must be asserted to read or
CS
RD
write an internal register. It may remain asserted at all times if desired.
Utility bus read enable. Active low asynchronous input. After latching
an address, a read is performed by deasserting WR and asserting
RD and CS.
88
In
Utility bus write enable. Active low asynchronous input. After latching
an address, a write is performed by deasserting RD, placing data
on the AD bus, and asserting WR and CS. Data is sampled.
WR
MISCELLANEOUS SIGNALS
I/O
SIGNAL NAME
PIN NUMBER
103
SIGNAL DESCRIPTION
DA
In
Reserved signal. This input must be connected to logic low.
DNC
12, 82, 105, 106
Out
Do Not Connect. Do not connect these pins to anything external to the
chip. They must remain open.
85
Out
Interrupt. INT is an open-drain output, driven low to indicate an interrupt.
Once low, INT remains low until the interrupt status in the appropriate
interrupt Status Register is read. Interrupt sources are programmable
via the interrupt Mask Registers.
INT
MA
MB
114
115
6
In
In
In
In
Reserved signal. This input must be connected to logic low.
Reserved signal. This input must be connected to logic low.
Reserved signal. This input must be connected to logic high.
MM
MODE[1:0]
7, 8
Mode Selects. They determine the configuration of the PHY/ATM
interface. 00 = UTOPIA Level 2. 01 = UTOPIA Level 1. 10 = DPI.
11 is reserved.
OSC
126
87
In
In
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz
for 25.6 Mbps; 64 MHz for 51.2 Mbps.
Reset. Active low asynchronous input resets all control logic, counters
and FIFOs. A reset must be performed after power up prior to normal
operation of the part.
RST
Receive LED drivers. Driven low for 223 RCLK or DPICLK cycles,
beginning with RXSOC when that port receives a good (non-null and
non-errored) cell. Drives 8 mA both high and low. One per port.
RXLED[2:0]
81, 80, 79
Out
4781 tbl 01
3
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 1 — SIGNAL DESCRIPTIONS (CONTINUED):
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
9
Out
Receive Reference. Active low, synchronous to OSC. RXREF pulses
RXREF
low for a programmable number of clock cycles when an x_8 command
byte is received. Register 0x40 is programmed to indicate which port
is referenced.
SE
102
In
Reserved signal. This input must be connected to logic low.
Ports 2 thru 0 Transmit LED driver. Goes low for 223 TCLK or DPICLK
cycles, beginning with TXSOC when this port receives a cell for
transmission. 8 mA drive current both high and low. One per port.
TXLED[2:0]
13, 14, 15
Out
10
In
Transmit Reference. Synchronous to OSC. On the falling edge of TXREF,
an X_8 command byte is inserted into the transmit data stream. Logic
for this signal is programmed in register 0x40. Typical application is
WAN timing.
TXREF
POWER SUPPLY SIGNALS
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
____
AGND
112, 117, 118, 123,
124, 127, 129, 130,
135, 136, 141
Analog ground. AGND supply a ground reference to the analog
portion of the ship, which sources a more constant current than the
digital portion.
____
____
____
AVDD
113, 116, 119, 122,
125, 128, 131, 134,
137, 140
Analog power supply 3.3 + 0.3V AVDD supply power to the analog
portion of the chip, which draws a more constant current than the
digital portion.
2, 11, 44, 50, 56,
67, 77, 83, 86, 97,
107, 111, 142
Digital Ground.
GND
VDD
1, 5, 16, 38, 45,
57, 68, 78, 84, 92,
104, 108
Digital power supply. 3.3 + 0.3V.
16-BIT UTOPIA 2 SIGNALS (MODE[1:0] = 00)
I/O
SIGNAL NAME
PIN NUMBER
SIGNAL DESCRIPTION
RXADDR[4:0]
53, 52, 51, 49, 48
In
Utopia 2 Receive Address Bus. This bus is used in polling and selecting
the receive port. The port addresses are defined in bits [4:0] of the
Enhanced Control Registers.
RXCLAV
54
Out
Utopia 2 Receive Cell Available. Indicates the cell available status of the
addressed port. It is asserted when a full cell is available for retrieval
from the receive FIFO. When non of the three ports is addressed.
RXCLAV is high impedance.
RXCLK
46
In
Utopia 2 Receive Clock. This is a free running clock input.
RXDATA[15:0]
59, 60, 61, 62, 63, 64,
65, 66, 69, 70, 71, 72,
73, 74, 75, 76
Out
Utopia 2 Receive Data. When one of the three ports is selected, the
77V1253 transfers received cells to an ATM device across this bus.
Also see RXPARITY.
47
In
Utopia 2 Receive Enable. Driven by an ATM device to indicate its ability
to receive data across the RXDATA bus.
RXEN
RXPARITY
RXSOC
58
55
Out
Out
Utopia 2 Receive Data Parity. Odd parity over RXDATA[15:0].
Utopia 2 Receive Start of Cell. Asserted coincident with the first word of
data for each cell on RXDATA.
TXADDR[4:0]
TXCLAV
36, 37, 39, 40, 41
42
In
Utopia 2 Transmit Address Bus. This bus is used in polling and selecting
the transmit port. The port addresses are defined in bits [4:0] of the
Enhanced Control Registers.
Out
Utopia 2 Transmit Cell Available. Indicates the availability of room in the
transmit FIFO of the addressed port for a full cell. When none of the
three ports is addressed, TXCLAV is high impedance.
4781tbl 02
4
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 1 — SIGNAL DESCRIPTIONS (CONTINUED):
SIGNAL NAME
TXCLK
PIN NUMBER
I/O
In
SIGNAL DESCRIPTION
43
Utopia Transmit Clock. This is a free running clock input.
TXDATA[15:0]
32, 31, 30, 29, 28,
27, 26, 25, 24, 23, 22,
21, 20, 19, 18, 17
In
Utopia 2 Transmit Data. An ATM device transfers cells across this bus to
the 77V1253 for transmission. Also see TXPARITY.
34
Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is
transmitting data across the TXDATA bus.
TXEN
In
In
TXPARITY
33
Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0]. Parity is
checked and errors are indicated in the Interrupt Status Registers, as
enabled in the Master Control Registers. No other action is taken in the
event of an error. Tie high or low if unused.
TXSOC
35
In
Utopia 2 Transmit Start of Cell. Asserted coincident with the first word of
data for each cell on TXDATA.
8-BIT UTOPIA LEVEL 1 SIGNALS (MODE[1:0] = 01)
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
RXCLAV[2:0]
65, 66, 54
Out
Utopia 1 Receive Cell Available. Indicates the cell available status of the
respective port. It is asserted when a full cell is available for retrieval
from the receive FIFO.
RXCLK
46
In
Utopia 1 Receive Clock. This is a free running clock input.
Utopia 1 Receive Data. When one of the three ports is selected, the
77V1253 transfers received cells to an ATM device across this bus. Bit 5
in the Diagnostic Control Registers determines whether RXDATA tri-states
when RXEN[2:0] are high. Also see RXPARITY.
RXDATA[7:0]
69, 70, 71, 72,
73, 74, 75, 76
Out
49, 48, 47
In
Utopia 1 Receive Enable. Driven by an ATM device to indicate its ability
to receive data across the RXDATA bus. One for each port.
RXEN[2:0]
RXPARITY
RXSOC
58
55
Out
Out
Utopia 1 Receive Data Parity. Odd parity over RXDATA[7:0].
Utopia 1 Receive Start of Cell. Asserted coincident with the first word of
data for each cell on RXDATA. Tri-statable as determined by bit 5 in the
Diagnostic Control Registers.
TXCLAV[2:0]
40, 41, 42
43
Out
Utopia 1 Transmit cell Available. Indicates the availability of room in the
transmit FIFO of the respective port for a full cell.
TXCLK
In
In
Utopia 1 Transmit Clock. This is a free running clock input.
TXDATA[7:0]
24, 23, 22, 21,
20, 19, 18, 17
Utopia 1 Transmit Data. An ATM device transfers cells across the bus to
the 77V1253 for transmission. Also see TXPARITY.
26, 25, 34
In
In
Utopia 1 Transmit Enable. Driven by an ATM device to indicate it is
transmitting data across the TXDATA bus. One for each port.
TXEN[2:0]
TXPARITY
33
Utopia 1 Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is
checked and errors are indicated in the Interrupt Status Registers, as
enabled in the Master Control Registers. No other action is taken in the
event of an error. Tie high or low if unused.
TXSOC
35
In
Utopia 1 Transmit Start of Cell. Asserted coincident with the first word of
data for each cell on TXDATA.
DPI MODE SIGNALS (MODE[1:0] = 10)
I/O
SIGNAL NAME
PIN NUMBER
SIGNAL DESCRIPTION
DPICLK
43
In
DPI Source Clock for Transmit. This is the free-running clock used as the
source to geenrate Pn_TCLK.
Pn_RCLK
51, 49, 48
In
DPI Port 'n' Receive Clock. Pn_RCLK is cycled to indicate that the
interfacing device is ready to receive a nibble of data on Pn_RD[3:0] of
port 'n'.
Pn_RD[3:0]
63, 64, 65, 66,
69, 70, 71, 72,
73, 74, 75, 76
Out
DPI Port 'n' Receive Data. Cells received on port 'n' are passed to the
interfacing device across this bus. Each port has its own dedicated bus.
4781 tbl 03
5
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 1 — SIGNAL DESCRIPTIONS (CONTINUED):
SIGNAL NAME
PIN NUMBER
I/O
SIGNAL DESCRIPTION
Pn_PFRM
58, 54, 55
Out
DPI Port 'n' Receive Frame. Pn_RFRM is asserted for one cycle
immediately preceding the transfer of each cell on Pn_RD[3:0].
Pn_TCLK
Pn_TD[3:0]
Pn_TFRM
39, 40, 41
Out
In
DPI Port 'n' Transmit Clock. Pn_TCLK is derrived from DPICLK and is
cycled when the respective port is ready to accept another 4 bits of data
on Pn_TD[3:0].
28, 27, 26, 25,
24, 23, 22, 21,
20, 19, 18, 17
DPI Port 'n' Transmit Data. Cells are passed across this bus to the PHY
for transmission on port 'n'. Each port has its own dedicated bus.
36, 33, 34, 35
In
DPI Port 'n' Transmit Frame. Start of cell signal which is asserted for one
cycle immediately preceding the first 4 bits of each cell on Pn_TD[3:0].
4781 tbl 04
TABLE 2 — SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE
MODE:
SIGNAL NAME
PIN NUMBER
16-BIT UTOPIA 2
MODE[1,0] = 00
8-BIT UTOPIA 1
MODE[1,0] = 01
DPI
MODE[1,0] = 10
VDD
GND
1
2
TX0-
3
TX0+
4
VDD
5
MM
6
MODE1
MODE0
RXREF
TXREF
GND
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
DNC
TXLED2
TXLED1
TXLED0
VDD
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXDATA8
TXDATA9
TXDATA10
TXDATA11
TXDATA12
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXDATA8
TXDATA9
TXDATA10
TXDATA11
TXDATA12
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXEN[1]
P0_TD[0]
P0_TD[1]
P0_TD[2]
P0_TD[3]
P1_TD[0]
P1_TD[1]
P1_TD[2]
P1_TD[3]
P2_TD[0]
P2_TD[1]
P2_TD[2]
P2_TD[3]
see note 2
TXEN[2]
see note 2
see note 2
see note 2
4781 tbl 05
6
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 2 — SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE
MODE(CONTINUED):
SIGNAL NAME
TXDATA13
TXDATA14
TXDATA15
TXPARITY
TXEN
PIN NUMBER
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
16-BIT UTOPIA 2
TXDATA13
TXDATA14
TXDATA15
TXPARITY
TXEN
8-BIT UTOPIA 1
see note 2
see note 2
see note 2
TXPARITY
TXEN[0]
DPI
see note 2
see note 2
see note 2
P2_TFRM
P1_TFRM
P0_TFRM
see note 2
see note 2
TXSOC
TXSOC
TXSOC
TXADDR4
TXADDR3
VDD
TXADDR4
TXADDR3
see note 2
see note 2
TXADDR2
TXADDR1
TXADDR0
TXCLAV
TXCLK
TXADDR2
TXADDR1
TXADDR0
TXCLAV
TXCLK
see note 1
TXCLAV[2]
TXCLAV[1]
TXCLAV[0]
TXCLK
P2_TCLK
P1_TCLK
P0_TCLK
see note 1
DPICLK
GND
VDD
RXCLK
RXCLK
RXEN
RXCLK
RXEN[0]
RXEN[1]
RXEN[2]
see note 2
see note 2
P0_RCLK
P1_RCLK
RXEN
RXADDR0
RXADDR1
GND
RXADDR0
RXADDR1
RXADDR2
RXADDR3
RXADDR4
RXCLAV
RXSOC
RXADDR2
RXADDR3
RXADDR4
RXCLAV
RXSOC
see note 2
see note 2
see note 2
RXCLAV[0]
RXSOC
P2_RCLK
see note 2
see note 2
P1_RFRM
P0_FRM
GND
VDD
RXPARITY
RXDATA15
RXDATA14
RXDATA13
RXDATA12
RXDATA11
RXDATA10
RXDATA9
RXDATA8
GND
RXPARITY
RXDATA15
RXDATA14
RXDATA13
RXDATA12
RXDATA11
RXDATA10
RXDATA9
RXDATA8
RXPARITY
see note 1
see note 1
see note 1
see note 1
see note 1
RXCLAV[3]
RXCLAV[2]
RXCLAV[1]
P2_RFRM
see note 1
see note 1
see note 1
see note 1
P2_RD[3]
P2_RD[2]
P2_RD[1]
P2_RD[0]
VDD
RXDATA7
RXDATA6
RXDATA5
RXDATA4
RXDATA3
RXDATA2
RXDATA1
RXDATA7
RXDATA6
RXDATA5
RXDATA4
RXDATA3
RXDATA2
RXDATA1
RXDATA7
RXDATA6
RXDATA5
RXDATA4
RXDATA3
RXDATA2
RXDATA1
P1_RD[3]
P1_RD[2]
P1_RD[1]
P1_RD[0]
P0_RD[3]
P0_RD[2]
P0_RD[1]
4781 tbl 06
7
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 2 — SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE
MODE(CONTINUED):
SIGNAL NAME
RXDATA0
GND
VDD
RXLED0
RXLED1
RXLED2
DNC
PIN NUMBER
76
16-BIT UTOPIA 2
8-BIT UTOPIA 1
DPI
RXDATA0
RXDATA0
P0_RD[0]
77
78
79
80
81
82
GND
VDD
INT
83
84
85
GND
RST
86
87
88
WR
89
RD
90
CS
ALE
91
VDD
AD0
92
93
AD0
94
AD0
95
AD0
96
GND
AD0
97
98
AD0
99
AD0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
AD0
SE
DA
VDD
DNC
DNC
GND
VDD
TX2-
TX2+
GND
AGND
AVDD
MA
MB
AVDD
AGND
AGND
AVDD
RX2-
RX2+
4781 tbl 07
8
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TABLE 2 — SIGNAL ASSIGNMENT AS A FUNCTION OF PHY/ATM INTERFACE
MODE(CONTINUED):
SIGNAL NAME
AVDD
AGND
AGND
AVDD
OSC
PIN NUMBER
122
16-BIT UTOPIA 2
8-BIT UTOPIA 1
DPI
123
124
125
126
AGND
AVDD
AGND
AGND
AVDD
RX1-
127
128
129
130
131
132
RX1+
133
AVDD
AGND
AGND
AVDD
RX0-
134
135
136
137
138
RX0+
139
AVDD
AGND
GND
140
141
142
TX1-
143
TX1+
144
4781 tbl 08
NOTES:
1. This output signal is unused in this mode. It must be left unconnected.
2. This input signal is unused in this mode. It must be connected to either logic high or logic low.
9
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
The 77V1253 is based on the 77105, and maintains significant register
compatibilitywithit.The77V1253,however,hasadditionalregisterfeatures,
andalsoduplicatesmostofitsregisterstoprovidesignificantindependence
betweenthethreeports.
Accesstothesestatusandcontrolregistersisthroughtheutilitybus. This
is an 8-bit muxed address and data bus, controlled by a conventional
asynchronousread/writehandshake.
77V1253OVERVIEW:
The77V1253isathree-portimplementationofthephysicallayerstandard
for 25.6Mbps ATM network communications as defined by ATM Forum
document af-phy-040.000 and ITU-T I.432.5. The physical layer is divided
intoaPhysicalMediaDependentsublayer(PMD)andTransmissionConver-
gence (TC) sub layer. The PMD sub layer includes the functions for the
transmitter, receiverandclockrecoveryforoperationacross 100meters of
category3unshieldedtwistedpair(UTP)cable.ThisisreferredtoastheLine
Side Interface. The TC sub layer defines the line coding, scrambling, data
framingandsynchronization.
Additionalpinspermitinsertionandextractionofan8kHztimingmarker,and
provideLEDindicationofreceiveandtransmitstatus.
OPERATIONAT51.2Mbps
Inadditiontooperationatthestandardrateof25.6Mbps,the77V1253is
alsospecifiedtooperateat51.2Mbps. Exceptforthedoubledbitrate,allother
aspects of operation are identical to the 25.6 Mbps mode. The data rate is
determinedbythefrequencyoftheclockappliedtotheOSCinput. OSCis32
MHz for the 25.6 Mbps line rate, and 64 MHz for the 51.2 Mbps line rate. All
portsoperateatthesamefrequency.
Onthe otherside, the 77V1253interfaces toanATMlayerdevice (such
asaswitchcoreorSAR). Thiscelllevelinterfaceisconfigurableaseither8-
bit Utopia Level 1 Multi-PHY, 16-bit Utopia Level 2, or as three 4-bit DPI
interfaces,asdeterminedbytwoMODEpins. ThisisreferredtoasthePHY-
ATM Interface. The pinout and front page block diagram are based on the
Utopia2configuration.Table2showsthecorrespondingpinfunctionsforthe
othertwomodes, andFigures 2and3showfunctionalblockdiagrams.
See page 30 for recommended line magnetics. Magnetics for 51.2 Mbps
operationhaveahigherbandwidththanmagneticsoptimizedfor25.6Mbps.
TxREF
TxCLK
+
-
Driver
Tx Port 0
Rx Port 0
TxDATA[7:0]
5B/4B
Encoding/
Decoding
TxParity
TxSOC
TxEN[2:0]
TxCLAV[2:0]
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
P/S and S/P
NRZI
Clock/Data
Recovery
+
-
UTOPIA
Multi-PHY
Interface
Mode[1:0]
RxCLK
RxDATA[7:0]
RxParity
+
-
Driver
Tx Port 1
Rx Port 1
5B/4B
Encoding/
Decoding
RxSOC
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
P/S and S/P
NRZI
RxEN[2:0]
Clock/Data
Recovery
+
-
RxCLAV[2:0]
INT
RST
RD
WR
+
-
Microprocessor
(Utility Bus)
Interface
Tx Port 2
Rx Port 2
Driver
5B/4B
Encoding/
Decoding
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
P/S and S/P
NRZI
CS
+
-
Clock/Data
Recovery
AD[7:0]
ALE
3
3
OSC
RxREF
4781 drw 03
RxLED[2:0] TxLED[2:0]
Figure 2. Block Diagram for Utopia Level 1 configuration (MODE[1:0] = 01)
10
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TxREF
DPICLK
Mode[1:0]
P0_TCLK
P0_TFRM
P0_TD[3:0]
+
-
Tx Port 0
Rx Port 0
Driver
5B/4B
Encoding/
Decoding
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
P/S and S/P
NRZI
Clock/Data
Recovery
+
-
P0_RCLK
P0_RFRM
P0_RD[3:0]
P1_TCLK
P1_TFRM
P1_TD[3:0]
+
-
Tx Port 1
Rx Port 1
Driver
5B/4B
Encoding/
Decoding
DPI
Multi-PHY
Interface
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
P/S and S/P
NRZI
Clock/Data
Recovery
+
-
P1_RCLK
P1_RFRM
P1_RD[3:0]
P2_TCLK
P2_TFRM
P2_TD[3:0]
+
-
Tx Port 2
Rx Port 2
Driver
5B/4B
Encoding/
Decoding
Tx/Rx ATM
Cell FIFO
Scrambler/
Descrambler
P/S and S/P
NRZI
+
-
P2_RCLK
P2_RFRM
P2_RD[3:0]
Clock/Data
Recovery
3
3
INT
RST
RD
WR
CS
Microprocessor
(Utility Bus)
Interface
AD[7:0]
ALE
OSC
RxREF
4781 drw 04
RxLED[2:0]
TxLED[2:0]
Figure 3. Block Diagram for DPI configuration (MODE[1:0] = 10)
11
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
2. X_4('escape'followedby'4'):Start-of-cellwithoutscrambler/
FUNCTIONALDESCRIPTION
descramblerreset.
3. X_8 ('escape' followed by '8'): 8kHz timing marker. This command byte
is generated when the 8kHz sync pulse is detected, and has priority over
alllineactivity(dataorcommandbytes). Itistransmittedimmediately
whenthe syncpulse is detected. Whenthis occurs duringa cell
transmission,thedatatransferistemporarilyinterruptedonanoctet
boundary,andtheX_8commandbyteis inserted.This conditionis the
onlyallowedinterruptinanotherwisecontiguoustransfer.
Belowisanillustrationofthecellstructureandcommandbyteusage:
TRANSMISSION CONVERGENCE (TC) SUB LAYER
Introduction
The TC sub layer defines the line coding, scrambling, data framing and
synchronization. Under control of a switch interface or Segmentation and
Reassembly(SAR)unit,the25.6MbpsATMPHYacceptsa53-byteATMcell,
scramblesthedata,appendsacommandbytetothebeginningofthecell,and
encodestheentire53bytesbeforetransmission.Thesedatatransformations
ensurethatthesignalisevenlydistributedacrossthefrequencyspectrum. In
addition,theserializedbitstreamisNRZIcoded.An8kHztimingsyncpulsemay
beusedforisochronouscommunications.
{X_X} {53-byte ATM cell} {X_4} {53-byte ATM {X_8} cell} ...
Intheaboveexample,thefirstATMcellisprecededbytheX_Xstart-of-cell
command byte which resets both the transmitter-scrambler and receiver-
descramblerpseudo-randomnibblegenerators(PRNG)totheirinitialstates.
The followingcellillustrates the insertionofa start-of-cellcommandwithout
scrambler/descramblerreset.Duringthiscell'stransmission,an8kHztiming
syncpulsetriggersinsertionoftheX_88kHztimingmarkercommandbyte.
Data Structure and Framing
Each 53-byte ATM cell is preceded with a command byte. This byte is
distinguishedbyanescapesymbolfollowedbyoneof17encodedsymbols.
Together,thisbyteformsoneofseventeenpossiblecommandbytes. Three
commandbytesaredefined:
1. X_X (read:'escape'symbolfollowedbyanother'escape'): Start-of-cell
withscrambler/descramblerreset.
FUNCTIONALBLOCKDIAGRAM(CONTINUED):
Start of Cell
TxRef (8kHz)
3 Cells
4
4
Command
Byte
Scrambler
Insertion
PHY-ATM
Interface
Reset
UTOPIA
or
DPI Interface
Control,
HEC Gen. &
Insertion
4
4
Scramble
Nibble
Next
PRNG
4b/5b
Encoding
1
OSC
Clock Input
NRZI
Encoding
Tx +
Tx -
4781 drw 05
Figure 4. TC Transmit Block Diagram
12
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
Transmission Description
RefertoFigure4onthepreviouspage.Celltransmissionbeginswiththe
PHY-ATMInterface. AnATMlayerdevice transfers a cellintothe 77V1253
acrosstheUtopiaorDPItransmitbus. Thiscellentersa3-celldeeptransmit
FIFO. OnceacompletecellisintheFIFO,transmissionbeginsbypassingthe
cell,fourbits(MSBfirst)atatimetothe'Scrambler'.
Data
0000
0100
1000
1100
Symbol
10101
00111
10010
10111
Data
0001
0101
1001
1101
Symbol
01001
01101
11001
11101
The'Scrambler'takeseachnibbleofdataandexclusive-ORsthemagainst
the4highorderbits(X(t),X(t-1),X(t-2),X(t-3))ofa10bitpseudo-randomnibble
generator (PRNG). Its function is to provide the appropriate frequency
distributionforthesignalacrosstheline.
The PRNG is clocked every time a nibble is processed, regardless of
whethertheprocessednibbleispartofadataorcommandbyte.Notehowever
thatonlydatanibblesarescrambled. Theentirecommandbyte(X_C)isNOT
scrambledbeforeit'sencoded(seediagramforillustration).ThePRNGisbased
uponthefollowingpolynomial:
Data
0010
0110
1010
1110
Symbol
01010
01110
11010
11110
Data
0011
0111
1011
1111
Symbol
01011
01111
11011
11111
4781 drw 05a
ESC(X) = 00010
10
7
X + X + 1
This encode/decodeimplementationhas severalverydesirableproper-
ties.Amongthemisthefactthattheoutputdatabitscanberepresentedbya
setofrelativelysimplesymbols;
With this polynomial, the four output data bits (D3, D2, D1, D0) will be
generatedfromthefollowingequations:
•Runlengthis limitedto<=5;
• Disparity never exceeds +/- 1.
D3 = d3 xor X(t-3)
D2 = d2 xor X(t-2)
D1 = d1 xor X(t-1)
D0 = d0 xor X(t)
On the receiver, the decoder determines from the received symbols
whetheratimingmarkercommand(X_8)orastart-of-cellcommandwassent
(X_XorX_4). Ifastart-of-cellcommandisdetected,thenext53bytesreceived
are decoded and forwarded to the descrambler. (See TC Receive Block
Diagram, Figure 4).
ThefollowingnibbleisscrambledwithX(t+4),X(t+3),X(t+2),andX(t+1).
Ascramblerlockbetweenthetransmitterandreceiveroccurseachtimean
X_Xcommandissent. AnX_Xcommandisinitiatedonlyatthebeginningofa
celltransferafterthePRNGhascycledthroughallofitsstates(210 -1=1023
states). The first valid ATM data cell transmitted after power on will also be
accompaniedwithanX_Xcommandbyte.EachtimeanX_Xcommandbyteis
sent,thefirstnibbleafterthelastescape(X)nibbleisXOR'dwith1111b(PRNG
= 3FFx).
Because a timing marker command (X_8) may occur at any time, the
possibilityofaresetPRNGstart-of-cellcommandandatimingmarkercommand
occurringconsecutivelydoesexist(e.g.X_X_X_8). Inthiscase,thedetection
ofthelasttwoconsecutiveescape(X)nibbleswillcausethePRNGtoresetto
itsinitial3FFxstate.Therefore,thePRNGisclockedonlyafterthefirstnibble
ofthesecondconsecutiveescapepair.
OncethedatanibbleshavebeenscrambledusingthePRNG,thenibbles
arefurtherencodedusinga4b/5bprocess.The4b/5bschemeensures that
anappropriatenumberofsignaltransitionsoccurontheline.Atotalofseventeen
5-bitsymbolsareusedtorepresentthesixteen4-bitdatanibblesandtheone
escape(X)nibble.Thetablebelowliststhe4-bitdatawiththeircorresponding
5-bitsymbols:
Theoutputofthe4b/5bencoderprovidesserialdatatotheNRZIencoder.
The NRZI code transitions the wire voltage each time a '1' bit is sent. This,
togetherwiththepreviousencodingschemesguaranteesthatlongrunlengths
ofeither'0'or'1'sareprevented.Eachsymbolisshiftedoutwithitsmostsignificant
bitsentfirst.
Whennocellsareavailabletotransmit,the77V1253keepsthelineactive
bycontinuingtotransmitvalidsymbols.Butitdoesnottransmitanotherstart-
of-cellcommanduntilithasanothercellfortransmission. The77V1253never
generatesidlecells.
Transmit HEC Byte Calculation/Insertion
Byte #5 of each ATM cell, the HEC (Header Error Control) is calculated
automaticallyacross thefirst4bytes ofthecellheader,dependinguponthe
settingofbit5ofregisters0x03,0x13and0x23.Thisbyteistheneitherinserted
asareplacementofthefifthbytetransferredtothePHYbytheexternalsystem,
or the cell is transmitted as received. A third operating mode provides for
insertionof"Bad"HECcodes whichmayaidincommunicationdiagnostics.
These modes are controlled by the LED Driver and HEC Status/Control
Registers.
13
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
Receiver Description
Uponresetorthe re-connect, eachport's receiveris typicallynotsymbol-
synchronized. When not symbol-synchronized, the receiver will indicate a
significantnumberofbadsymbols, andwilldeassertthe GoodSignalBitas
describedbelow.Synchronizationisestablishedimmediatelyoncethatport
receivesanEscapesymbol,usuallyaspartofthestart-of-cellcommandbyte
precedingthefirstreceivedcell.
ThereceiversideoftheTCsublayeroperateslikethetransmitter,but
inreverse.ThedataisNRZIdecodedbeforeeachsymbolisreassembled.
Thesymbolsarethensenttothe5b/4bdecoder,followedbytheCommand
ByteInterpreter,De-Scrambler,andfinallythroughaFIFOtotheUTOPIA
or DPI interface to an ATM Layer device.
TheIDT77V1253monitorslineconditionsandcanprovideaninterruptifthe
lineisdeemed'bad'. TheInterruptStatusRegisters(registers0x01,0x11and
0x21)containaGoodSignalBit(bit6,setto0=Badsignalinitially)whichshows
thestatusofthelineperthefollowingalgorithm:
NotethatalthoughtheIDT77V1253candetectsymbolandHECerrors,
itdoesnotattempttocorrectthem.
ATMCELLFORMAT
Bit 7
Bit 0
To declare 'Good Signal' (from "Bad" to "Good"):
Header Byte 1
Header Byte 2
Header Byte 3
Header Byte 4
UDF
There is anup-downcounterthatcounts from7to0andis initiallysetto
7. Whenthe clockticks for1,024cycles (32MHzclock, 1,024cycles =
204.8 symbols) and no "bad symbol" has been received, the counter
decreases by one. However, if at least one "bad symbol" is detected
during these 1,024 clocks, the counter is increased by one, to a
maximumof7. The GoodSignalBitis setto1whenthis counterreaches
0. The Good Signal Bit could be set to 1 as quickly as 1,433 symbols
(204.8 x 7) if no bad symbols have been received.
Payload Byte 1
•
•
•
Payload Byte 48
4781 drw 52
UDF = User Defined Field (or HEC)
FUNCTIONALBLOCKDIAGRAM(CONTINUED):
PRNG
Scramble
Nibble
RxRef
Reset
4
Next
Command
Byte
5b/4b
Decoding
NRZI
Decoding
De-
Scrambler
Detection,
Removal,
& Decode
Rx +
Rx
5
4
4
Start of Cell
4
3 Cells
32.0MHz
Clock
Synthesizer
& PLL
UTOPIA
or
DPI Interface
PHY-ATM
Interface
Control -
RECV
4781 drw 06
OSC
Figure 5. TC Receive Block Diagram
14
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
To declare 'Bad Signal' (from "Good" to "Bad"):
8kHzTimingMarker
The same up-down counter counts from 0 to 7 (being at 0 to provide a
"Good"status). Whentheclockticksfor1,024cycles(32MHzclock,
1,024 cycles = 204.8 symbols) and there is at least one "bad symbol",
the counterincreases byone. Ifitdetects all"goodsymbols"andno
"badsymbols"inthe nexttime period, the counterdecreases byone.
The "Bad Signal" is declared when the counter reaches 7. The Good
Signal Bit could be set to 0 as quickly as 1,433 symbols (204.8 x 7) if at
leastone"badsymbol"is detectedineachofsevenconsecutivegroups
of204.8symbols.
The8kHztimingmarker,describedearlier,isacompletelyoptionalfeature
whichisessentialforsomeapplicationsrequiringsynchronizationforvoiceor
video, and unnecessary for other applications. Figure 6 shows the options
availableforgeneratingandreceivingthe8kHztimingmarker.
The source of the marker is programmable in the RXREF and TXREF
ControlRegister(0x40). Eachportisindividuallyprogrammabletoeitheralocal
source or a looped remote source. The local source is TXREF, which is an
8kHzclockofvirtuallyanydutycycle. Whenunused, TXREFshouldbe tied
high. Also note that it is not limited to 8kHz, should a different frequency be
desired. When looped, a received X_8 command byte causes one to be
generatedonthetransmitside.
A received X_8 command byte causes the 77V1253 to issue a negative
pulse on RXREF. The source channel of the marker is programmable.
TxREF
Input
( Reg 40, Bit 0)
LTSel#0
LTSel#1
RxRef#0
(X_8 received)
Mux
Mux
TxRef#0
(X_8 generator)
( Reg 40, Bit 1)
RxRef#1
(X_8 received)
TxRef#1
(X_8 generator)
( Reg 40, Bit 2)
LTSel#2
RxRef#2
(X_8 received)
Mux
TxRef#2
(X_8 generator)
RxRef
RxRefSel[1:0]
Select
Decoder
IDT77V1253
RxREF
Output
4781 drw 07
Figure 6. RXREF and TXREF Block Diagram
15
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
The ATM device starts by polling the PHY ports on the Utopia 2 bus to
determineifanyofthemhasroomtoacceptacellfortransmission(TXCLAV),
or has a receive cell available to pass on to the ATM device (RXCLAV). To
poll,theATMdevicedrivesanaddress(TXADDRorRXADDR)thenobserves
TXCLAVorRXCLAVonthenextcycleofTXCLKorRXCLK. Aportmusttri-
state TXCLAVandRXCLAVexceptwhenitis addressed.
IfTXCLAVorRXCLAVis asserted,theATMdevicemayselectthatport,
thentransferacelltoorfromit. Selectionofaportisperformedbydrivingthe
address ofthe desiredportwhile TXEN or RXENis high, thendriving TXEN
orRXENlow. When TXENis drivenlow, TXSOC(startofcell)is drivenhigh
toindicatethatthefirst16bitsofthecellarebeingdrivenonTXDATA. TheATM
devicemaychosetotemporarilysuspendtransferofthecellbydeasserting
TXEN. Otherwise,TXENremainsassertedasthenext16bitsaredrivenonto
TXDATA with each cycle of TXCLK.
Inthereceivedirection,theATMdeviceselectsaportifitwishedtoreceive
thecellthattheportisholding. ItdoesthisbyassertingRXEN. ThePHYthen
transfersthedata16bits eachclockcycle,asdeterminedbyRXEN. Asinthe
transmitdirection,theATMdevicemaysuspendtransferbydeassertingRXEN
atanytime. NotethatthePHYassertsRXSOCcoincidentwiththefirst16bits
ofeachcell.
PHY-ATMInterface
The77V1253PHYoffersthreechoicesininterfacingtoATMlayerdevices
suchassegmentationandreassembly(SAR) andswitchingchips. MODE[1:0]
areusedtoselecttheconfigurationofthisinterface,asshowninthetablebelow.
MODE[1:0] PHY-ATM Interface Configuration
00
01
10
one 16-bit UTOPIA Level 2 port
one 8-bit UTOPIA Level 1 (Multi-PHY) port
three 4-bit Data Path Interface (DPI) ports
4781 tbl 09
UTOPIAis a PhysicalLayertoATMLayerinterface standardizedbythe
ATM Forum. It has separate transmit and receive channels and specific
handshakingprotocols. UTOPIALevel2has dedicatedaddress signals for
boththetransmitandreceivedirectionsthatallowtheATMlayerdevicetospecify
withwhichofthefourPHYchannelsitiscommunicating. UTOPIALevel1does
nothaveaddresssignals. Instead,keyhandshakingsignalsareduplicatedso
thateachchannelhasitsownsignals. InbothversionsofUTOPIA,allchannels
shareasingletransmitdatabusandasinglereceivedatabusfordatatransfer.
DPI is a low-pin count Physical Layer to ATM Layer interface. The low-
pincountcharacteristicallowsthe77V1253toincorporatethreeseparateDPI
4-bitports,oneforeachofthethreeserialports. AswiththeUTOPIAinterfaces,
thetransmitandreceivedirectionshavetheirowndatapathsandhandshaking.
TXPARITYandRXPARITYareparitybitsforthecorresponding16-bitdata
fields. Oddparityis used.
Figures 8 through 13 may be referenced for Utopia 2 bus examples.
Becausethisinterfacetransfersanevennumberofbytes,ratherthanthe
ATMstandardof53bytes,afillerbyteisinsertedbetweenthe5-byteheader
and the 48-byte payload. This is shown in Figure 7.
UTOPIA LEVEL 2 INTERFACE OPTION
The 16-bit Utopia Level 2 interface operates as defined in ATM Forum
document af-phy-0039. This PHY-ATM interface is selected by setting the
MODE[1:0]pinsbothlow.
This modeis configuredas asingle16-bitdatabus inthetransmit(ATM-
to-PHY)direction, anda single 16-bitdata bus inthe receive (PHY-to-ATM)
direction. Inadditiontothedatabus,eachdirectionalsoincludesasingleoptional
parity bit, an address bus, and several handshaking signals. The UTOPIA
addressofeachchannelisdeterminedbybits4to0intheEnhancedControl
Registers. Please note that the transmit bus and the receive bus operate
completelyindependently. TheUtopia2signalsaresummarizedbelow:
Bit 15
Bit 0
Header byte 2
First Header byte 1
Header byte 3
Header byte 5
Payload byte 1
Payload byte 3
Payload byte 5
Header byte 4
stuff byte
TXDATA[15:0]
TXPARITY
TXSOC
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
Payload byte 2
Payload byte 4
Payload byte 6
TXADDR[4:0]
TXEN
TXCLAV
TXCLK
RXDATA[15:0]
RXPARITY
RXSOC
RXADDR[4:0]
RXEN
RXCLAV
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
Payload byte 45 Payload byte 46
Last Payload byte 47 Payload byte 48
4781 drw 08
RXCLK
Figure 7. Utopia Level 2 Data Format and Sequence
16
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
selection
polling
polling
polling:
TxCLK
TxADDR[4:0]
1F
N+3
1F
N+2
1F
N+3
1F
N
1F
High-Z
TxCLAV
N+1
N+3
N+2
N+3
N
TxEN
TxData[15:0],
TxPARITY
H5, undefined
P39, 40
P41, 42
P43, 44
P45, 46
P47, 48
H1, 2
H3, 4
P1, 2
TxSOC
PHY N+3
PHY N
cell transmission to:
4781 drw 09
Figure 8. Utopia 2 Transmit Handshake - Back to Back Cells
selection
polling
polling
polling:
TxCLK
TxADDR[4:0]
1F
N+3
1F
N+2
1F
N+3
1F
N
1F
High-Z
TxCLAV
N+1
N+3
N+2
N+3
N
TxEN
TxData[15:0],
TxPARITY
H5, undefined
P43, 44
P45, 46
P47, 48
H1, 2
H3, 4
P1, 2
TxSOC
PHY N+3
PHY N
cell transmission to:
4781 drw 10
Figure 9. Utopia 2 Transmit Handshake - Delay Between Cells
17
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
selection
polling
polling
polling:
TxCLK
TxADDR[4:0]
1F
N+3
1F
N+2
1F
M
1F
N
1F
High-Z
TxCLAV
N+1
N+3
N+2
M
N
TxEN
High-Z
High-Z
TxData[15:0],
TxPARITY
P25, 26
P27, 28
P29, 30
P31, 32
P33, 34
P35, 36
TxSOC
PHY M
PHY M
cell transmission to:
4781 drw 11
Figure 10. Utopia 2 Transmit Handshake - Transmission Suspended
selection
polling
polling
polling:
RxCLK
RxADDR[4:0]
N+3
1F
N+2
1F
N+3
1F
N
1F
N+1
1F
High-Z
RxCLAV
N+3
N+2
N+3
N
RxEN
High-Z
High-Z
RxData[15:0],
RxPARITY
H5, undefined
P39, 40
P41, 42
P43, 44
P45, 46
P47, 48
H1, 2
H3, 4
P1, 2
RxSOC
PHY N+3
PHY N
cell transmission to:
4781 drw 12
Figure 11. Utopia 2 Receive Handshake - Back to Back Cells
18
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
selection
polling
polling
polling:
RxCLK
RxADDR[4:0]
N+3
1F
N+2
1F
N+1
1F
N+1
1F
N
1F
High-Z
RxCLAV
N+3
N+2
N+1
N+1
RxEN
High-Z
High-Z
RxData[15:0],
RxPARITY
P45, 46
P47, 48
H1, 2
H3, 4
undefined
RxSOC
PHY N+1
PHY N+3
cell transmission to:
4781 drw 13
Figure 12. Utopia 2 Receive Handshake - Delay Between Cells
re-selection
polling
polling
polling:
RxCLK
RxADDR[4:0]
N+3
1F
N+2
1F
M
1F
N+1
1F
N+2
High-Z
RxCLAV
N+3
N+2
M
N+1
RxEN
High-Z
High-Z
RxData[15:0],
RxPARITY
P25, 26
P27, 28
P29, 30
P31, 32
P33, 34
P35, 36
RxSOC
PHY M
PHY M
cell transmission from:
4781 drw 14
Figure 13. Utopia 2 Receive Handshake - Suspended Transfer of Data
19
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
UTOPIA LEVEL 1 MULTI-PHY INTERFACE OPTION
The UTOPIALevel1MULTI-PHYinterface operates as definedinATM
Forumdocumentaf-phy-0017andclarifiedinaf-phy-0039. UtopiaLevel1is
essentiallythesameasUtopiaLevel2,butwithouttheaddressing,pollingand
selectionfeatures. Insteadofaddressing,itutilizesseparateTxCLAV,TxEN,
RxCLAVandRxENsignalsforeachchannelofthe77V1254. Therearejust
oneeachoftheTxSOCandRxSOCsignals,whicharesharedacrossallthree
channels.
InadditiontoUtopiaLevel2'scellmodetransferprotocol,UtopiaLevel1
also offers the option of a byte mode protocol. Bit 1 of the Master Control
RegistersisusedtoprogramwhethertheUTOPIALevel1busisincellmode
orbytemode. Inbytemode,thePHYisallowedtocontroldatatransferona
byte-by-byte basis via the TXCLAV and RXCLAV signals. In cell mode,
TXCLAVandRXCLAVareignoredoncethetransferofacellhasbegun. In
every other way the two modes are identical. Cell mode is the default
configurationandistheonedescribedlater.
Bit 7
Bit 0
First Header byte 1
Header byte 2
Header byte 3
Header byte 4
Header byte 5
Payload byte 1
Payload byte 2
Payload byte 3
Payload byte 46
Payload byte 47
TheUtopia1signals aresummarizedbelow:
TXDATA[7:0]
TXPARITY
TXSOC
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
Last Payload byte 48
4781 drw 15
TXEN[2:0]
TXCLAV[2:0]
TXCLK
Figure 14. Utopia 1 Data Format and Sequence
RXDATA[7:0]
RXPARITY
RXSOC
RXEN[2:0]
RXCLAV[2:0]
RXCLK
PHY to ATM
PHY to ATM
PHY to ATM
ATM to PHY
PHY to ATM
ATM to PHY
ofthecelltransfer,buttheATMdevicemaydeassertTXENatanytimeoncethe
celltransferhas begun, butdata is transferredonlywhenTXEN is asserted.
Inthereceivedirection,RXENindicateswhentheATMdeviceisprepared
toreceivedata. Aswithtransmit,itmaybeassertedordeassertedatanytime.
ThePHYassertsRXCLAVtoindicatethatithasanentirecelltotransfer.
Inbothtransmitandreceive,TXSOCandRXSOC(startofcell)isasserted
foroneclock,coincidentwiththefirstbyteofeachcell. Oddparityisutilizedacross
each8-bitdatafield.
Transmitandreceivebothutilizefreerunningclocks,whichareinputsto
the77V1253. AllUtopiasignalsaretimedtotheseclocks.
In the transmit direction, the PHY first asserts TXCLAV (transmit cell
available)toindicatethatithasroominitstransmitFIFOtoacceptatleastone
53-byteATMcell. WhentheATMlayerdeviceisreadytobeginpassingthe
cell,itassertsTXEN(transmitenable)andTXSOC(startofcell),coincidentwith
thefirstbyteofthecellonTXDATA. TXENremainsassertedfortheduration
Figure 14shows the data sequence foranATMcelloverUtopia Level1,
and Figures 15 to 21 are examples of the Utopia Level 1 handshake.
TxCLK
TxCLAV[2:0]
TxEN[2:0]
TxDATA[7:0],
TxPARITY
X
H1
H2
P44
P45
P46
P47
P48
X
TxSOC
4781 drw 16
Figure 15. Utopia 1 Transmit Handshake - Single Cell
20
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
TxCLK
TxCLAV[2:0]
TxEN[2:0]
TxDATA[7:0],
TxPARITY
P46
P47
P48
H1
H2
H3
H4
X
H5
TxSOC
4781 drw 17
Figure 16. Utopia 1 Transmit Handshake - Back-to-Back Cells, and TXEN Suspended Transmission
TxCLK
TxCLAV[2:0]
TxEN[2:0]
TxDATA[7:0],
TxPARITY
P42
P43
P44
P45
P46
X
X
X
P47
P48
H1
TxSOC
4781 drw 18
Figure 17. Utopia 1 Transmit Handshake - TXEN Suspended Transmission and Back-to-Back Cells
(Byte Mode Only)
RxCLK
RxCLAV[2:0]
RxEN[2:0]
High-Z
RxDATA[7:0],
RxPARITY
P47
P48
H1
H2
H3
High-Z
RxSOC
4781 drw 19
Figure 18. Utopia 1 Receive Handshake - Delay Between Cells
21
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
RxCLK
RxCLAV[2:0]
RxEN[2:0]
High-Z
RxDATA[7:0],
RxPARITY
P47
P48
H1
P47
P48
X
X
H1
H2
High-Z
RxSOC
4781 drw 20
Figure 19. Utopia 1 Receive Handshake - RXEN and RXCLAV Control
RxCLK
RxCLAV[2:0]
Early RxCLAV option (bit 6=1, registers 0x02, 0x12, 0x22)
RxEN[2:0]
High-Z
High-Z
High-Z
High-Z
RxDATA[7:0],
RxPARITY
P42
P43
P44
P45
P46
P47
P48
X
X
RxSOC
4781 drw 21
Figure 20. Utopia 1 Receive Handshake - RXCLAV Deassertion
RxCLK
RxCLAV[2:0]
RxEN[2:0]
High-Z
RxDATA[7:0],
RxPARITY
H1
H2
X
H3
H4
H5
P1
High-Z
RxSOC
4781 drw 22
Figure 21. Utopia 1 Receive Handshake - RXCLAV Suspended Transfer (Byte Mode Only)
22
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
The DPIprotocolis exactlysymmetricalinthe receive direction, withthe
77V1253drivingthedataandstart-of-cellsignalswhilereceivingPn_RCLK
as aninput.
The DPI data interface is four bits, so the 53 bytes of an ATM cell are
transferredin106cycles. Figure22showsthesequenceofthatdatatransfer.
Figures 23 through 30 show how the handshake operates.
DPI INTERFACE OPTION
TheDPIinterfaceisrelativelynewandworthadditionaldescription. The
biggestdifferencebetweentheDPIconfigurationsandtheUTOPIAconfigurations
isthateachchannelhasitsownDPIinterface. Eachinterfacehasa4-bitdata
path,aclockandastart-of-cellsignal,forboththetransmitdirectionandthe
receivedirection. Therefore,eachsignalispoint-to-point,andnoneofthese
signalshashigh-Zcapability. Additionally,thereisonemasterDPIclockinput
(DPICLK)intothe77V1253whichisusedasasourcefortheDPItransmitclock
outputs. DPI is a cell-based transfer scheme like Utopia Level 2, whereas
UTOPIA Level 1 transfers can be either byte- or cell-based.
AnotheruniqueaspectofDPIisthatitisasymmetricalinterface. Itisaseasy
toconnecttwoPHYsback-to-backasitistoconnectaPHYtoaswitchfabric
chip. Incontrast,Utopiaisasymmetrical. Notethatforthe77V1253,weare
usingthe"transmit"and"receive"nomenclatureinthenamingoftheDPIsignals,
whereasotherdevicesmayusemoregeneric"in"and"out"nomenclaturefor
theirDPIsignals.
Bit 3
Bit 0
First
Header byte 1, (8:5)
Header byte 1, (4:1)
Header byte 2, (8:5)
Header byte 2, (4:1)
Header byte 3, (8:5)
Header byte 3, (4:1)
Header byte 4, (8:5)
Header byte 4, (4:1)
Header byte 5, (8:5)
Header byte 5, (4:1)
Payload byte 1, (8:5)
Payload byte 1, (4:1)
TheDPIsignalsaresummarizedbelow,where"Pn_"referstothesignalsfor
channelnumber"n":
DPICLK
inputtoPHY
PHY to ATM
ATM to PHY
ATM to PHY
Pn_TCLK
Pn_TD[3:0]
Pn_TFRM
Pn_RCLK
Pn_RD[3:0]
Pn_RFRM
ATM to PHY
PHY to ATM
PHY to ATM
Payload byte 47, (8:5)
Payload byte 47, (4:1)
Payload byte 48, (8:5)
Payload byte 48, (4:1)
Inthetransmitdirection(ATMtoPHY),theATMlayerdeviceassertsstart-
of-cellsignal(Pn_TFRM)foroneclockcycle,oneclockpriortodrivingthefirst
nibbleofthecellonPn_TD[3:0]. OncetheATMsidehasbegunsendingacell,
itispreparedtosendtheentirecellwithoutinterruption. The77V1253drives
thetransmitDPIclocks(Pn_TCLK)backtotheATMdevice,andcanmodulate
(gap)ittocontroltheflowofdata. Specifically,ifitcannotacceptanothernibble,
the77V1253disablesPn_TCLKanddoesnotgenerateanotherrisingedge
untilithas roomforthe nibble. Pn_TCLKare derivedfromthe DPICLKfree
runningclocksource.
Last
4781 drw 23
Figure 22. DPI Data Format and Sequence
23
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
P_RCLK (in)
P_RFRM (out)
Cell 1
Nibble 104
Cell 1
Nibble 105
Cell 1
Nibble 0
P_RD(3:0) (out)
X
X
X
X
4781 drw 24
Figure 23. DPI Receive Handshake - One Cell Received
P_RCLK (in)
P_RFRM (out)
Cell 1
Nibble 104
Cell 1
Nibble 0
Cell 1
Nibble 1
Cell 1
Nibble 105
Cell 2
Nibble 0
Cell 2
Nibble 1
P_RD(3:0) (out)
X
X
Cell 1
4781 drw 25
Figure 24. DPI Receive Handshake - Back-to-Back Cells
P_RCLK (in)
P_RFRM (out)
Cell 2
Nibble 1
Cell 1
Nibble 104
Cell 1
Nibble 105
Cell 2
Nibble 0
Cell 2
Nibble 2
Cell 2
Nibble 3
Cell 2
Nibble 4
P_RD(3:0) (out)
4781 drw 26
Figure 25. DPI Receive Handshake - ATM Layer Device Suspends Transfer
24
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
ATM Layer Device Not Ready
77V1253 Not Ready
P_RCLK (in)
P_RFRM (out)
Cell 1
Nibble 104
Cell 1
Nibble 105
Cell 2
Nibble 0
Cell 2
Nibble 1
Cell 2
Nibble 2
P_RD(3:0) (out)
X
X
X
X
4781 drw 27
Figure 26. DPI Receive Handshake - Neither Device Ready
P_TCLK (out)
P_TFRM (in)
Cell 1
Nibble 0
Cell 1
Nibble 1
Cell 1
Nibble 104
Cell 1
Nibble 105
P_TD(3:0) (in)
X
X
X
X
4781 drw 28
Figure 27. DPI Transmit Handshake - One Cell for Transmission
P_TCLK (out)
P_TFRM (in)
Cell 1
Nibble 104
Cell 1
Nibble 0
Cell 1
Nibble 1
Cell 1
Nibble 105
Cell 2
Nibble 0
Cell 2
Nibble 1
P_TD(3:0) (in)
X
X
Cell 1
4781 drw 29
Figure 28. DPI Transmit Handshake - Back-to-Back Cells for Transmission
25
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
P_TCLK (out)
P_TFRM (in)
Cell 2
Nibble 1
Cell 1
Nibble 104
Cell 1
Nibble 105
Cell 2
Nibble 0
Cell 2
Nibble 2
Cell 2
Nibble 3
Cell 2
Nibble 4
P_TD(3:0) (in)
4781 drw 30
Figure 29. DPI Transmit Handshake - 77V1254 Transmit FIFO Full
77V1253 Not Ready
ATM Layer Device Not Ready
P_TCLK (out)
P_TFRM (in)
Cell 1
Nibble 104
Cell 1
Nibble 105
Cell 2
Nibble 0
Cell 2
Nibble 1
Cell 2
Nibble 2
P_TD(3:0) (in)
X
X
X
X
4781 drw 31
Figure 30. DPI Transmit Handshake - Neither Device Ready
26
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
differentinterruptsources. Additionalinterruptsignalcontrolisprovidedbybit
5oftheMasterControlRegisters.Whenthisbitisset(=1),receivecellerrors
will be flagged via interrupt signalling and all other interrupt conditions are
masked.Theseerrorsinclude:
CONTROLANDSTATUSINTERFACE
UTILITY BUS
TheUtilityBusisabyte-wideinterfacethatprovidesaccesstotheregisters
withintheIDT77V1253.Theseregistersareusedtoselectdesiredoperating
characteristicsandfunctions,andtocommunicatestatustoexternalsystems.
TheUtilityBusisimplementedusingamultiplexedaddressanddatabus
(AD[7:0])wheretheregisteraddressislatchedviathe AddressLatchEnable
(ALE)signal.
- Bad receive HEC
- Short (fewer than 53 bytes) cells
- Received cell symbol error
Normalinterruptoperationsareperformedbysettingbit0andclearingbit
5intheMasterControlRegisters. INT(pin85)willgotoalowstatewhenan
interruptconditionisdetected.Theexternalsystemshouldtheninterrogatethe
77V1253todeterminewhichone(ormore)conditionscausedthisflag,andreset
the interrupt for further occurrences. This is accomplished by reading the
InterruptStatusRegisters.Decodingthebitsinthesebyteswilltellwhicherror
conditioncausedtheinterrupt.Readingtheseregistersalso:
TheUtilityBusinterfaceiscomprisedofthefollowingpins:
AD[7:0], ALE, CS, RD, WR
Read Operation
RefertotheUtilityBustimingwaveformsinFigures42-43.Aregisterread
isperformedasfollows:
1. Initialcondition:
-clearsthe(sticky)interruptstatusbitsintheregistersthatareread
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
- resets INT
2. Set up register address:
Thisleavestheinterruptsystemreadytosignalanalarmforfurtherproblems.
- place desired register address on AD[7:0]
- set ALE to logic 1;
-latchthis address bysettingALEtologic0.
3. Read register data:
LED CONTROL AND SIGNALLING
TheLEDoutputsprovidebi-directionalLEDdrivecapabilityof8mA. Asan
example,theRxLEDoutputsaredescribedinthetruthtable:
-Remove registeraddress data fromAD[7:0]
-assertCSbysettingtologic0;
- assert RD by setting to logic 0
-waitminimumpulsewidthtime(seeACspeci-
fications)
STATE
PIN VOLTAGE
Low
Cells being received
Cells not being received
High
4781 tbl 10
Write Operation
Asillustratedinthefollowingdrawing(Figure31),thiscouldbeconnected
toprovideforatwo-LEDconditionindicator. Thesecouldalsobedifferentcolors
toprovidesimplestatusindicationataglance.(TheminimumvalueforRshould
be 330Ω, but a value closer to 1 kΩ is recommended).
Aregisterwriteis performedas describedbelow:
1. Initialcondition:
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
2. Set up register address:
TxLED Truth Table
- place desired register address on AD[7:0]
- set ALE to logic 1;
-latchthis address bysettingALEtologic0.
3. Writedata:
STATE
PIN VOLTAGE
Low
Cells being transmitted
Cells not being transmitted
High
- place data on AD[7:0]
4781 tbl 11
-assertCSbysettingtologic0;
-assertWR(logic0)forminimumtime
3.3V
(accordingtotimingspecification);resetWR
to logic 1 to
completeregisterwritecycle.
R
(Indicates: Cells
being received
or transmitted)
INTERRUPTOPERATIONS
RxLED(2:0)
TxLED(2:0)
TheIDT77V1253providesavarietyofselectableinterruptandsignalling
conditionswhichareusefulbothduring‘normal’operation,andasdiagnostic
aids.RefertotheStatusandControlRegisterListsection.
Overallinterruptcontrolisprovidedviabit0oftheMasterControlRegisters.
When this bit is cleared (set to 0), interrupt signalling is prevented on the
respective port. The Interrupt Mask Registers allow individual masking of
(Indicates: Cells are
not being received or
transmitted)
R
4781 drw 32
Figure 31.
27
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
DIAGNOSTIC FUNCTIONS
PHY Loopback
AsFigure33 illustratesbelow,thisloopbackmodeprovidesaconnection
withinthePHYfromthetransmitPHY-ATMinterfacetothePHY-ATMreceive
interface. Note that while this mode is operating, no data is forwarded to or
receivedfromthelineinterface.
1. LOOPBACK
Therearetwoloopbackmodessupportedbythe77V1253. Theloopback
modeiscontrolledviabits1and0oftheDiagnosticControlRegisters:
Line Loopback
Bit 1
Bit 0
MODE
Normal operating mode
PHY Loopback
Figure 34 might also be called “remote loopback” since it provides for a
meanstotesttheoverallsystem,includingtheline.Sincethismodewillprobably
beenteredunderdirectionfromanothersystem(ataremotelocation),receive
dataisalsodecodedandtransferredtotheupstreamsystemtoallowittolisten
forcommands.Acommonexamplewouldbeacommandaskingtheupstream
system to direct the TC to leave this loopback state, and resume normal
operations.
0
1
1
0
0
1
Line Loopback
4781 tbl 12
Normal Mode
This mode,Figure32,supports normaloperatingconditions:datatobe
transmitted is transferred to the TC, where it is queued and formatted for
transmissionbythePMD.ReceivedatafromthePMDisdecodedalongwith
itsclockfortransfertothereceiving"upstreamsystem".
ATM Layer
Device
Utopia/DPI
Interface
Line
TC sublayer
PMD sublayer
Interface
4781 drw 33
Figure 32. Normal Mode
Line
Interface
ATM Layer Utopia/DPI
Device Interface
PMD sublayer
TC sublayer
4781 drw 34
Figure 33. PHY Loopback
28
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
ATM Layer
Device
Utopia/DPI
Interface
PMD
sublayer
Line
Interface
TC sublayer
4781 drw 35
Figure 34. Line Loopback
2. COUNTERS
VPI/VCISwapping
Severalconditioncountersareprovidedtoassistexternalsystems(e.g.
softwaredrivers)inevaluatingcommunicationsconditions. Itisanticipatedthat
these counters willbe polledfromtime totime (userselectable)toevaluate
performance. AseparatesetofregistersexistsforeachchannelofthePHY.
ForcompatibilitywithIDT'sSwitchStarproducts(77V400and77V500),the
77V1253hastheabilitytoswappartsoftheVPI/VCIaddressspaceintheheader
ofreceivecells. ThisfunctioniscontrolledbytheVPI/VCISwapbits,whichare
bit5oftheEnhancedControlRegisters(0x08,0x18and0x28). Theportions
ofthe VPI/VCIthatare swappedare shownbelow. Bits X(7:0)are swapped
with Y(7:0) when the VPI/VCI Swap bit is set and the chip is in DPI mode.
• Symbol Error Counters
- 8 bits
-counts allinvalid5-bitsymbols received
•TransmitCellCounters
- 16 bits
-countsalltransmittedcells
• Receive Cell Counters
7
0
- 16 bits
VPI
VCI
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
GFC/VPI
VPI
- counts all received cells, excluding idle cells and HEC errored
cells
• Receive HEC Error Counters
- 5 bits
VCI
VCI
PTI
CLP
0
- counts all HEC errors received
HEC
TheTxCellandRxCellcountersaresized(16bits)toprovideafullcellcount
(withoutrollover)ifthecounterisreadonce/second.TheSymbolErrorcounter
andHECErrorcounterweregivensufficientsizetoindicateexactcountsfor
low error-rate conditions. If these counters overflow, a gross condition is
occurring, where additional counter resolution does not provide additional
diagnosticbenefit.
7
X7 X6 X5 X4 X3 X2 X1 X0 Byte 0
Y7 Y6 Y5 Y4 Byte 1
Y3 Y2 Y1 Y0
Byte 2
Byte 3
Byte 4
4781 drw 51
Reading Counters
1. Decide which counter value is desired. Write to the Counter Select
Register(s)(0x06,0x16and0x26)tothebitlocationcorrespondingtothe
desiredcounter.ThisloadstheHighandLowByteCounterRegisterswith
theselectedcounter’svalue,andresetsthiscountertozero.
NOTE: Only one counter may be enabled at any time in each of the Counter Select
Registers.
2. ReadtheCounterRegisters(0x04,0x14or0x24(lowbyte))and(0x05,
0x15 or 0x25 (high byte)) to get the value.
Further reads may be accomplished in the same manner by writing to the
CounterSelectRegisters.
29
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
Also, the receive circuitry biases the positive and negative RX inputs to
slightlydifferentvoltages. Thisisdonesothatthereceiverdoesnotreceivefalse
signals in the absence of a real signal. This can be important because the
77V1253doesnotdisableerrordetectionorinterruptswhenaninputsignalis
notpresent.
LINE SIDE (SERIAL) INTERFACE
Eachofthefourportshastwopinsfordifferentialserialtransmission,
andtwopinsfordifferentialserialreceiving.
PHY TO MAGNETICS INTERFACE
WhenconnectingtoUTPat51.2Mbps,itisnecessarytousemagneticswith
sufficientbandwidth. Suchadevicecanalsooperatesatisfactorilyat25.6Mbps.
A standard connection to 100ý and 120ý unshielded twisted pair
cablingisshowninFigure35. Notethatthetransmitsignalissomewhat
attenuatedinordertomeetthelaunchamplitudespecifiedbythestandards.
Thereceivecircuitryisdesignedtoattenuatelowfrequenciesinorderto
compensateforthehighfrequencyattenuationofthecable.
IDT77V1253
TxD+
AGND
R1
R2
4
3
5
1
2
1
2
3
4
5
6
7
8
7
8
R3
TxD-
AVDD
Magnetics
R5
C1
R8
RxD+
16
15
R7
R4
10
9
R9
C2
L1
RxD-
14
13
12
R6
AGND
4781 drw 36
AGND
Figure 35. Recommended Connection to Magnetics
TABLE 3 — ANALOG COMPONENT
VALUES
Component
Value
47Ω
Tolerance
+5%
R1
R2
R3
R4
R5
R6
R7
R8
R9
C1
C2
L1
Magnetics Modules for 25.6 Mbps
47Ω
+5%
Pulse PE-67583 or R4005
TDK TLA-6M103
Valor SF1153
(619) 674-8100
(847) 803-6100
(800) 318-2567
620Ω
110Ω
2700Ω
2700Ω
82Ω
+5%
+5%
+5%
+5%
+5%
33Ω
+5%
Magnetics Modules for 51.2 Mbps
33Ω
+5%
Pulse R4005
(619) 674-8100
470pF
470pF
3.3µH
+20%
+20%
+20%
4781 tbl 13
30
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
STATUS AND CONTROL REGISTER LIST
The77V1253has28registersthatareaccessiblethroughtheutilitybus. Eachofthethreeportshas9registersdedicatedtothatport. Thereisonlyoneregister(0x40)which
isnotportspecific.
ForthoseregisterbitswhichcontroloperationoftheUtopiainterface,theoperationoftheUtopiainterfaceisdeterminedbytheregisterscorrespondingtotheportwhichis
selectedatthatparticulartime. Forconsistentoperation,theUtopiacontrolbitsshouldbeprogrammedthesameforallthreeports,exceptfortheUtopia2portaddressesinthe
EnhancedControlRegisters.
Register Address
Register Name
Port 0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Port 1
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
Port 2
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
All Ports
Master Control Registers
Interrupt Status Registers
Diagnostic Control Registers
LED Driver and HEC Status/control
Low Byte Counter Register [7:0]
High Byte Counter Register [15:8]
Counter Registers Read Select
Interrupt Mask Registers
Enhanced Control Registers
RxREF and TxREF Control Register
0x40
4781 tbl 14
Nomenclature
"Reserved" register bits, if written, should always be written "0"
R/W = register may be read and written via the utility bus
R-only or W-only = register is read-only or write-only
sticky = register bit is cleared after the register containing it is read; all sticky bits are read-only
“0” = ‘cleared’ or ‘not set’
“1” = ‘set’
MASTERCONTROLREGISTERS
Addresses: 0x00, 0x10, 0x20
Bit
7
Type
R
Initial State
Function
0
Reserved
6
R/W
1 = discard
Discard Receive Error Cells
errored cells
On receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive HEC error
(if enabled)), this cell will be discarded and will not enter the receive FIFO.
5
R/W
0 = all interrupts Enable Cell Error Interrupts Only
If Bit 0 in this register is set (Interrupts Enabled), setting of this bit enables only "Received Cell Error"
(as defined in bit 6) to trigger interrupt line.
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
0 = disabled
Transmit Data Parity Check
Directs TC to check parity of TxDATA against parity bit located in TXPARITY.
1 = discard
idle cells
Discard Received Idle Cells
Directs TC to discard received idle (GFC & VPI/VCI = 0) cells from PMD without signalling external systems.
0 = not halted Halt Tx
Halts transmission of data from TC to PMD and forces both TxD signals low.
0 = cell mode UTOPIA Level 1 mode select:
0 = cell mode, 1 = byte mode. Not applicable for Utopia 2 for DPI modes.
1 = enable
interrupts
Enable Interrupt Pin (Interrupt Mask Bit)
Enables interrupt output pin (pin 85). If cleared, pin is always high and interrupt is masked. If set, an
interrupt will be signaled by setting the interrupt pin to "0".
4781 tbl 15
31
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
INTERRUPTSTATUSREGISTERS
Addresses: 0x01, 0x11, 0x21
Bit
7
Type
R
Initial State
Function
0
Reserved
6
R
0 = Bad Signal Good Signal Bit
1 - Good Signal
See definitions on pages 14 and 15
0 - Bad Signal
5
4
sticky
sticky
0
0
HEC error cell received
"Short Cell" Received
Set when a HECerror is detected on received cell.
Interrupt signal which flags received cells with fewer than 53 bytes. This condition is detected when receiving
Start-of-Cell command bytes with fewer than 53 bytes between them.
3
2
sticky
sticky
0
0
Transmit Parity Error
If Bit 4 of Register 0x00 / 0x10 / 0x20 is set (Transmit Data Parity Check), this interrupt flags a transmit data
parity error condition. Odd parity is used.
Receive Signal Condition change
This interrupt is set when the received 'signal'
changes either from 'bad to good' or from 'good to bad'.
1
0
sticky
sticky
0
0
Received Symbol Error
Set when an undefined 5-bit symbol is received.
Receive FIFO Overflow
Interrupt which indicates when the receive FIFO has filled and cannot
accept additional data.
4781 tbl 16
DIAGNOSTICCONTROLREGISTERS
Addresses: 0x02, 0x12, 0x22
Bit
Type
Initial State
Function
7
R/W
0 = normal
Force TxCLAV deassert (applicable only in Utopia 1 and 2 modes)
Used during line loopback mode to prevent upstream system from continuing to send data to the
77V1253. Not applicable in DPI mode.
6
R/W
0 = UTOPIA
RxCLAV Operation Select (for Utopia 1 mode)
The UTOPIA standard dictates that during cell mode operation, if the receive FIFO no longer has a complete
cell available for transfer from PHY, RxCLAV is deasserted following transfer of the last byte out of the PHY
to the upstream system. With this bit set, early deassertion of this signal will occur coincident with the end of
Payload byte 44 (as in octet mode for TxCLAV). This provides early indication to the upstream system of this
impending condition.
0 = "Standard UTOPIA RxCLAV'
1 = "Cell mode = Byte mode"
5
4
3
R/W
R/W
R/W
1 = tri-state
0 = normal
0 = normal
Single/Multi-PHY configuration select (applicable and writable only in Utopia 1 mode)
0 = single:
Never tri-state RxDATA, RxPARITY and RxSOC
1 = Multi-PHY mode: Tri-state RxDATA, RxPARITY and RxSOC when RxEN = 1
RFLUSH = Clear Receive FIFO
This signal is used to tell the TC to flush (clear) all data in the receive FIFO. The TC signals this completion
by clearing this bit.
Insert Transmit Payload Error
Tells TC to insert cell payload errors in transmitted cells. This can be used to test error detection and
recovery systems at destination station, or, under loopback control, at the local receiving station. This
payload error is accomplished by flipping bit 0 of the last cell payload byte.
2
R/W
R/W
0 = normal
Insert Transmit HEC Error
Tells TC to insert HEC error in Byte 5 of cell. This can be used to test error detection and recovery
systems in downstream switches, or, under loopback control, the local receiving station. The HEC error is
accomplished by flipping bit 0 of the HEC byte.
1,0
00 = normal
Loopback Control
bit #
1
0
1
1
0
0
0
1
Normal mode (receive from network)
PHY Loopback
Line Loopback
4781 tbl 17
32
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
LEDDRIVERANDHECSTATUS/CONTROLREGISTERS
Addresses: 0x03, 0x13, 0x23
Bit
7
Type
Initial State
Function
0
Reserved
6
R/W
0 = enable
checking
Disable Receive HEC Checking (HEC Enable)
When not set, the HEC is calculated on first 4 bytes of received cell, and compared against the 5th byte.
When set (= 1), the HEC byte is not checked.
5
R/W
R/W
0 = enable
calculate &
replace
Disable Xmit HEC Calculate & Replace
When set, the 5th header byte of cells queued for transmit is not replaced with the HEC calculated across
the first four bytes of that cell.
RxREF Pulse Width Select
4,3
00 = 1 cycle
bit #
4
3 .
0
0 RxREF active for 1 OSC cycle
1 RxREF active for 2 OSC cycles
0 RxREF active for 4 OSC cycles
1 RxREF active for 8 OSC cycles
0
1
1
2
1
0
R
R
R
1 = empty
FIFO Status
TxLED Status
RxLED Status
1 = TxFIFO empty
0 = Cell Transmitted
0 = Cell Received
0 = TxFIFO not empty
1
1
1 = Cell not Transmitted
1 = Cell not Received
4781 tbl 18
LOW BYTE COUNTER REGISTERS [7:0]
Addresses: 0x04, 0x14, 0x24
Bit
Type
Initial State
Function
[7:0]
R
0x00
Provides low-byte of counter value selected via registers 0x06, 0x16 and 0x26.
4781 tbl 19
HIGH BYTE COUNTER REGISTERS [15:8]
Addresses: 0x05, 0x15, 0x25
Bit
Type
Initial State
Function
[7:0]
R
0x00
Provides high-byte of counter value selected via registers 0x06, 0x16 and 0x26.
4781 tbl 20
COUNTERSELECTREGISTERS
Addresses: 0x06, 0x16, 0x26
Bit
7
Type
Initial State
Function
____
0
0
0
0
0
0
0
0
Reserved.
____
____
____
6
Reserved.
5
Reserved.
4
Reserved.
3
W
W
W
W
Symbol Error Counter.
TxCell Counter.
RxCell Counter.
Receive HEC Error Counter.
2
1
0
4781 tbl 21
NOTE: Only one bit may set at any time for proper operation
33
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
INTERRUPTMASKREGISTERS
Addresses: 0x07, 0x17, 0x27
Bit
7
Type
Initial State
Function
0
0
Reserved.
Reserved.
6
5
R/W
R/W
R/W
R/W
R/W
R/W
0 = interrupt enabled HEC Error Cell.
4
0 = interrupt enabled Short Cell Error.
3
0 = interrupt enabled Transmit Parity Error.
0 = interrupt enabled Receive Signal Condition Change.
0 = interrupt enabled Received Cell Symbol Error.
0 = interrupt enabled Receive FIFO Overflow.
2
1
0
4781 tbl 22
NOTE: When set to "1", these bits mask the corresponding interrupts going to the interrupt pin (INT). When set to "0", the interrupts are unmasked. These
interruptscorrespondtotheinterruptstatusbitsintheInterruptStatusRegisters.
ENHANCEDCONTROLREGISTERS
Addresses: 0x08, 0x18, 0x28
Bit
Type
Initial State
Function
7
W
0 = not reset
Individual Port Software Reset
1 = Reset. This bit is self clearing; It is not necessary to write "0" to exit reset.
6
5
R/W
R/W
R/W
0 = OSC
Transmit Line Clock (or Loop Timing Mode)
When set to 0, the OSC input is used as the transmit line clock. When set to 1, the recovered
receive clock is used as the transmit line clock.
0 = no swap
VPI/VCI Swap
DPI mode only. Receive direction only. See description on page 29.
4-0
Port 0 (Reg 0x08): 00000 Utopia 2 Port Address
Port 1 (Reg 0x18): 00001 When operating in Utopia 2 Mode, these register bits determine the Utopia 2 port address. These
Port 2 (Reg 0x28): 00010 bits are not affected by an Individual Port Software Reset.
4781 tbl 23
RXREF ANDTXREF CONTROLREGISTER
Addresses: 0x40
Bit
Type
Initial State
Function
7,6
R/W
00 = RxREF0 (Port 0) RxREF Source Select
Selects which of the three ports (0 to 2) is the source of RxREF.
5
W
0 = not reset
Master Software Reset
1 - Reset. This bit is self clearing; it is not necessary write "0" to exit reset.
4-3
2-0
R/W
R/W
00
Reserved.
RxREF to TxREF Loop Select
0000 = not looped
When set to 0, TxREF is used to generate X_8 timing marker commands.
When set to 1, TxREF input is ignored, and received X_8 timing commands
are looped back and added to the transmit stream of that same port. See Figure 6.
bit 2: port 2
bit 1: port 1
bit 0: port 0
4781 tbl 24
34
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
ABSOLUTEMAXIMUMRATINGS(1)
IDT77V1253
RECOMMENDEDDCOPERATIONS
CONDITIONS
Symbol
Rating
Value
-0.5 to +5.5
-55 to +125
-55 to +120
50
Unit
V
Symbol
Parameter
Min.
3.0
0
Typ. Max. Unit
V
TERM
Terminal Voltage
with Respect to GND
VDD Digital Supply Voltage
GND Digital Ground Voltage
3.3
3.6
0
V
V
V
V
V
V
0
Temperature
Under Bias
oC
T
BIAS
____
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
-0.3
3.0
0
5.25
0.8
3.6
0
Storage
oC
____
T
STG
Temperature
AVDD Analog Supply Voltage
AGND Analog Ground Voltage
3.3
0
I
OUT
DC Output Current
mA
4781 tbl 25
NOTE:
VDIF
VDD - AVDD
-0.5
0
0.5
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
4781 tbl 26
CAPACITANCE(TA = +25°C, f = 1MHz)
RECOMMENDEDOPERATING
TEMPERATUREANDSUPPLY
VOLTAGE
Symbol
Parameter
Input Capacitance
I/O Capacitance
Conditions
IN = 0V
OUT = 0V
Max. Unit
(1)
C
IN
V
10
10
pF
Ambient
(1)
IO
C
V
pF
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
GND, AGND
VDD, AVDD
4781 tbl 28
0V
0V
3.3V
3.3V
+
+
0.3V
0.3V
NOTES:
1. Characterized values, not currently tested.
4781 tbl 27
DC ELECTRICAL CHARACTERISTICS (ALL PINS EXCEPT TX+/- AND RX+/-)
Symbol
Parameter
Input Leakage Current
Test Conditions
Min.
-5
Max.
Unit
µA
µA
V
ILI
Gnd ≤ VIN ≤ VDD
Gnd ≤ VIN ≤ VDD
5
ILO
I/O (as input) Leakage Current
Output Logic "1" Voltage
-10
2.4
10
(1)
OH1
___
V
I
OH = -2mA, VDD = min.
OH = -8mA, VDD = min.
OL = 8mA, VDD = min.
(2)
OH2
___
V
Output Logic "1" Voltage
I
2.4
V
(3)
OL
___
V
Output Logic "0" Voltage
I
0.4
140
140
V
(4,5)
DD1
___
___
I
Digital Power Supply Current - VDD
Analog Power Supply Current - AVDD
OSC = 32 MHz, all outputs unloaded
OSC = 32 MHz, all outputs unloaded
mA
(5)
DD2
I
mA
4781 tbl 29
NOTES:
1. For AD[7:0] pins only.
2. For all output pins except AD[7:0], INT and TX+/-.
3. For all output pins except TX+/-.
4. Add 15mA for each TX+/- pair that is driving a load
5. Total supply current is the sum of IDD1 and IDD2.
DC ELECTRICAL CHARACTERISTICS (TX+/- OUTPUT PINS ONLY)
Symbol
Parameter
Output High Voltage
Output Low Voltage
Test Conditions
Min.
Max.
Unit
____
VOH
I
OH = -20mA
VDD - 0.5V
V
____
VOL
IOL = 20mA
0.5
V
4781 tbl 30
35
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
UTOPIA LEVEL 2 BUS TIMING PARAMETERS
Symbol
Parameter
Min.
0.2
40
7
Max.
Unit
MHz
%
t1
TxCLK Frequency
50
t2
TxCLK Duty Cycle (% of t1)
60
____
t3
TxDATA[15:0], TxPARITY Setup Time to TxCLK
TxDATA[15:0], TxPARITY Hold Time to TxCLK
TxADDR[4:0], Setup Time to TxCLK
TxADDR[4:0}, Hold Time to TxCLK
TxSOC, TxEN Setup Time to TxCLK
TxSOC, TxEN Hold Time to TxCLK
TxCLK to TxCLAV High-Z
ns
____
____
____
____
____
t4
2
ns
t5
7
ns
t6
2
ns
t7
7
ns
t8
2
ns
t9
2
10
14
50
ns
t10
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
TxCLK to TxCLAV Low-Z (min) and Valid (max)
RxCLK Frequency
2
ns
0.2
40
7
MHz
%
RxCLK Duty Cycle (% of t12)
60
____
ns
RxEN Setup Time to RxCLK
____
____
____
2
ns
RxEN Hold Time to RxCLK
RxADDR[4:0] Setup Time to RxCLK
RxADDR[4:0] Hold Time to RxCLK
RxCLK to RxCLAV High-Z
7
ns
2
ns
2
10
14
10
14
10
14
ns
RxCLK to RxCLAV Low-Z (min) and Valid (max)
RxCLK to RxSOC High-Z
2
ns
2
ns
RxCLK to RxSOC Low-Z (min) and Valid (max)
RxCLK to RxDATA, RxPARITY High-Z
RxCLK to RxDATA, RxPARITY Low-Z (min) and Valid (max)
2
ns
2
ns
2
ns
4781 tbl 31
t3
t4
t2
t1
TxCLK
TxDATA[15:0],
TxPARITY
Octets 1 &
2
Octet 3 & 4
t5
t6
TxADDR[4:0]
t7
t8
t10
t9
t10
TxSOC
TxEN
High-Z
High-Z
TxCLAV
4781 drw 37
Figure 36. UTOPIA Level 2 Transmit
36
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
t12
t13
RxCLK
t
14
16
t15
RxEN
t
t17
RxADDR[4:0]
t18
t19
t19
High-Z
High-Z
High-Z
RxCLAV
RxSOC
t
21
t
21
t
20
High-Z
High-Z
t
23
t
23
t
22
High-Z
RxDATA[15:0],
RxPARITY
4781 drw 38
Figure 37. UTOPIA Level 2 Receive
UTOPIA LEVEL 1 BUS TIMING PARAMETERS
Symbol
Parameter
Min.
Max.
Unit
MHz
%
t31
t32
t33
t34
t35
t36
t37
t39
t40
t41
t42
t43
t44
t45
t46
t47
TxCLK Frequency
0.2
40
7
50
TxCLK Duty Cycle (% of t31)
60
____
TxDATA[7:0], TxPARITY Setup Time to TxCLK
TxDATA[7:0], TxPARITY Hold Time to TxCLK
TxSOC, TxEN[2:0] Setup Time to TxCLK
TxSOC, TxEN[2:0] Hold Time to TxCLK
TxCLK to TxCLAV[2:0] Invalid (min) and Valid (max)
RxCLK Frequency
ns
____
____
____
2
ns
7
ns
2
ns
2
14
50
ns
0.2
40
7
MHz
%
RxCLK Duty Cycle (% of t39)
60
____
ns
RxEN[2:0] Setup Time to RxCLK
____
2
ns
RxEN[2:0] Hold Time to RxCLK
RxCLK to RxCLAV[2:0] Invalid (min) and Valid (max)
RxCLK to RxSOC High-Z
2
14
10
14
10
14
ns
2
ns
RxCLK to RxSOC Low-Z (min) and Valid (max)
RxCLK to RxDATA, RxPARITY High-Z
RxCLK to RxDATA, RxPARITY Low-Z (min) and Valid (max)
2
ns
2
ns
2
ns
4781 tbl 32
37
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
t31
t32
t33
t34
TxCLK
TxDATA[7:0],
TxPARITY
Octet 1
36
Octet 2
t35
t
t37
TxSOC
TxEN[2:0]
TxCLAV[2:0]
4781 drw 39
Figure 38. UTOPIA Level 1 Transmit
t39
t
40
43
RxCLK
t41
t42
RxEN[2:0]
t
RxCLAV[2:0]
RxSOC
t
45
t
45
t
44
High-Z
High-Z
High-Z
High-Z
t
47
t47
t
46
RxDATA[7:0],
RxPARITY
4781 drw 40
Figure 39. UTOPIA Level 1 Receive
38
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
DPI BUS TIMING PARAMETERS
Symbol
Parameter
Min.
0.2
40
2
Max.
50
Unit
MHz
%
t51
t52
t53
t54
t55
t56
t57
t61
t62
t63
t64
t65
DPICLK Frequency
DPICLK Duty Cycle (% of t31)
DPICLK to Pn_TCLK Propagation Delay
Pn_TFRM Setup Time to Pn_TCLK
Pn_TFRM Hold Time to Pn_TCLK
Pn_TD[3:0] Setup Time to Pn_TCLK
Pn_TD[3:0] Hold Time to Pn_TCLK
Pn_RCLK Period
60
14
ns
____
11
1
ns
____
____
____
____
____
____
ns
11
1
ns
ns
25
10
10
2
ns
Pn_RCLK High Time
ns
Pn_RCLK Low Time
ns
Pn_RCLK to Pn_RFRM Invalid (min) and Valid (max)
Pn_RCLK to Pn_RD Invalid (min) and Valid (max)
12
12
ns
2
ns
4781 tbl 33
t51
t52
DPICLK
t53
Pn_TCLK
Pn_TFRM
Pn_TD[3:0]
t54
t55
t56
t57
4781 drw 41
Figure 40. DPI Transmit
t61
t62
t63
Pn_RCLK
Pn_RFRM
Pn_RD[3:0]
t64
t65
4781 drw 42
Figure 41. DPI Receive
39
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
UTILITY BUS READ CYCLE
UTILITY BUS WRITE CYCLE
Name
Tap w
Tas
Min
10
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Name
Tas
Min
10
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Address setup to ALE
Chip select to read enable
Address hold to ALE
____
____
ALE min pulse width
Address set up to ALE
Address hold time to ALE
CS Assert to WR
____
____
____
____
____
____
____
____
____
____
____
Tcsrd
Tah
Tah
5
Tac swr
Twrp w
Tdws
Tdwh
Tc h
0
Tap w
Ttria
Trdpw
Tdh
10
ALE min pulse width
____
20
20
10
0
Min. WR pulse width
Write Data set up
0
Address tri-state to RD assert
Min. RD pulse width
____
20
0
____
____
Write Data hold time
WR deassert to CS deassert
ALE low to end of write
Data Valid hold time
Tc h
0
RD deassert to CS deassert
RD deassert to data tri-state
Read Data access
____
Taw
20
Ttrid
Trd
10
4781 tbl 35
5
5
0
18
____
Tar
ALE low to start of read
Start of read to Data low-Z
____
Trdd
4781 tbl 34
Tah
Tas
AD[7:0]
(input)
Address
Tapw
ALE
Tch
Tcsrd
CS
RD
Tar
Trdpw
Ttrid
Tdh
Trd
Trdd
AD[7:0]
(output)
Data
4781 drw 43
Figure 42. Utility Bus Read Cycle
Tas
Tah
Tdws
Data (input)
Tdwh
AD[7:0]
ALE
CS
Address
Tapw
Tch
Taw
Tcswr
Twrpw
WR
4781 drw 44
Figure 43. Utility Bus Write Cycle
40
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
OSC, RXREF, TXREF AND RESETTIMING
Symbol
Parameter
Min.
Typ.
Max.
Unit
Tcyc
OSC cycle period (25.6 Mbps)
(51.2 Mbps)
30
15
31.25
15.625
33
16.5
ns
ns
____
____
____
____
____
____
____
Tch
Tcl
OSC high time
OSC lo w time
40
60
60
1
%
%
%
ns
ns
40
____
Tcc
OSC cycle to cycle period variation
OSC to RXREF Propagation Delay
TXREF High Time
Trrpd(1)
Ttrh
1
30
____
35
35
____
____
Ttrl
ns
TXREF Low Time
____
Trspw
Minimum RST Pulse Width
two OSC cycles
4781 tbl 36
NOTES:
1. The width of the RXREF pulse is programmable in the LED Driver and HEC Status/Control Registers.
2. The minimum RESET Pulse Width is either two RxCLK cycles, two TxCLK cycles, two DPICLK cycles or two OSC cycles, whichever is greater (and applicable).
Tch
Tcl
Tcyc
OSC
Trrpd
Trrpd
RxREF
Ttrl
Ttrh
TxREF
RST
Trspw
4781 drw 45
Figure 44. OSC, RXREF, TXREF and Reset Timing
1.5V
50Ω
ACTESTCONDITIONS
Input Pulse Levels
Z = 50Ω
D.U.T.
o
GND to 3.0V
.
Input Rise/Fall Times
3ns
4781 drw 46
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
See Figure 45
Figure 45. Output Load
4781 tbl 37
* Includes jigandscopecapacitances.
41
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
AnoteaboutFigures 46and47: TheATMForumandITU-Tstandards for25Mbps ATMdefine"Network"and"User"interfaces. Theyareidenticalexcept
thattransmitandreceive are switchedbetweenthe two. ANetworkdevice canbe connecteddirectlytoa Userdevice witha straight-throughcable. User-
to-UserorNetwork-to-Networkconnections require a cable with1-to-7and2-to-8crossovers.
Note 3
109
110
111
112
TX2+ TX2-
Note 1
Note 2
AGND
Rx
Filter
1
120 RX2-
121 RX2+
Rx
2
8 7 6 5 4 3 2 1
RJ45
Magnetics
Connector
7
8
9 10 11 12 13 14 15 16
Tx
Filter
Tx
IDT
77V1253
AGND
RJ45
RJ45
Magnetics
Magnetics
141
142
4781 drw 47
Figure 46. PC Board Layout for ATM Network
NOTES:
1. No power or ground plane inside this area.
2. Analog power plane inside this area.
3. Digital power plane inside this area.
4. A single ground plane should extend over the area covered by the analog and digital power planes, without breaks.
5. All analog signal traces should avoid 90° corners.
109
110
Note 3
Note 2
111
112
TX2+ TX2-
Note 1
AGND
Tx
Filter
1
Tx
2
8 7 6 5 4 3 2
1
RJ45
Connector
Magnetics
7
8
120 RX2-
121 RX2+
9 10 11 12 13 14 15 16
Rx
Filter
Rx
IDT
77V1253
AGND
RJ45
RJ45
Magnetics
Magnetics
141
142
4781 drw 48
Figure 47. PC Board Layout for ATM User
NOTES:
1. No power or ground plane inside this area.
2. Analog power plane inside this area.
3. Digital power plane inside this area.
4. A single ground plane should extend over the area covered by the analog and digital power planes, without breaks.
5. All analog signal traces should avoid 90° corners.
42
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6
AND 51.2 MBPS ATM NETWORKS
IDT77V1253
PackageDimensions
144
109
A2
1
A1
108
e
144-Lead
PQFP
PU-144
E
E1
73
36
A
37
72
D1
D
L
b
SYMBOL
MIN.
NOM.
MAX.
A
A1
A2
D
-
3.70
0.33
3.37
31.20
28.00
31.20
28.00
0.88
0.65
-
4.07
0.25
-
3.20
3.60
-
-
D1
E
-
-
-
-
-
-
E1
L
0.73
-
1.03
-
e
b
0.22
0.38
Dimensions are in millimeters
4781 drw 49
PSC-4053 is a more comprehensive package outline drawing which is available from the packaging section of the IDT
web site.
43
OrderingInformation
IDT
NNNNN
A
NNN
A
A
Process/
Temp. Range
Device Type
Speed
Package
Power
Industrial (-40°C to +85°C)
144-Pin PQFP (PU-144)
I
PG
25
L
Speed in Mb/s
Triple 25Mb/s ATM PHY
Transmission Convergence (TC)
and PMD Sublayers
77V1253
4781 drw 50
PreliminaryDatasheet:Definition
"PRELIMINARY'datasheetscontaindescriptionsforproductssoontobe,orrecentlyreleasedtoproduction,includingfeatures,pinoutsandblockdiagrams.
Timingdataarebasedonsimulationorinitialcharacterizationandaresubjecttochangeuponfullcharacterization.
DatasheetDocumentHistory
11/30/98:
PRELIMINARY.Numerousminoredits.CorrectionstoFigures25and29.EliminationofLineRateSelectionbitinthe
MasterControlRegisters.IDD1andIDD2valuesupdated.AdditionofVPI/VCISwapfeature.ImprovementstoUtopiabus
timingparameters.
3/25/99:
Updatetonewformat
12/08/2004
RemovedPreliminaryfromdatasheetandalsoremovedCommercialTemperaturerangethroughoutDatasheetandinOrderingInformation
drawing(pg44)and updateddatasheettocurrenttemplate.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8694
for Tech Support:
408-330-1552
email:TELECOMhelp@idt.com
44
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