IDT79R3051E-25J [IDT]
RISControllers; RISControllers
| 型号： | IDT79R3051E-25J |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | RISControllers |
| 文件： | 总23页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT79R3051 , 79R3051E
IDT79R3052 , 79R3052E
IDT79R3051/79R3052
RISControllers
Integrated Device Technology, Inc.
— On-chip DMA arbiter
FEATURES:
— Bus Interface minimizes design complexity
• Single clock input with 40%-60% duty cycle
• 35 MIPS, over 64,000 Dhrystones at 40MHz
• Low-cost 84-pin PLCC packaging that's pin-/package-
compatible with thermally enhanced 84-pin MQUAD.
• Flexible bus interface allows simple, low-cost designs
• 20, 25, 33, and 40MHz operation
• Complete software support
— Optimizing compilers
— Real-time operating systems
— Monitors/debuggers
• Instruction set compatible with IDT79R3000A and
IDT79R3001 MIPS RISC CPUs
• High level of integration minimizes system cost, power
consumption
— IDT79R3000A /IDT79R3001 RISC Integer CPU
— R3051 features 4KB of Instruction Cache
— R3052 features 8KB of Instruction Cache
— All devices feature 2kB of Data Cache
— “E” Versions (Extended Architecture) feature full
function Memory Management Unit, including 64-
entry Translation Lookaside Buffer (TLB)
— 4-deep write buffer eliminates memory write stalls
— 4-deep read buffer supports burst refill from slow
memory devices
— Floating Point Software
— Page Description Languages
BrCond(3:0)
Clk2xIn
Clock
Generator
Unit
Master Pipeline Control
System Control
Coprocessor
Integer
CPU Core
Exception/Control
Registers
General Registers
(32 x 32)
Memory Management
Registers
ALU
Shifter
Mult/Div Unit
Address Adder
PC Control
Int(5:0)
Translation
Lookaside Buffer
(64 entries)
Virtual Address
32
Physical Address Bus
32
Instruction
Cache
(8kB/4kB)
Data
Cache
(2kB)
Data Bus
Bus Interface Unit
4-deep
Write
Buffer
4-deep
DMA
BIU
Control
Read
Arbiter
Buffer
Address/
Data
DMA Rd/Wr SysClk
Ctrl Ctrl
2874 drw 01
Figure 1. R3051 Family Block Diagram
The IDT logo is a registered trademark, and RISChipset, RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400 and R4600 are trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
SEPTEMBER 1995
1995 Integrated Device Technology, Inc.
5.3
DSC-3000/5
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IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
The execution engine of the IDT79R3051 family uses a
five-stage pipeline to achieve close-to single cycle execution.
A new instruction can be started in every clock cycle; the
execution engine actually processes five instructions con-
currently (in various pipeline stages). Figure 2 shows the
concurrency achieved by the IDT79R3051 family pipeline.
INTRODUCTION
The IDT IDT79R3051 family is a series of high-perfor-
mance 32-bit microprocessors featuring a high level of inte-
gration which are targeted to high-performance, but cost-
sensitiveembeddedprocessingapplications.TheIDT79R3051
family is designed to bring the high-performance inherent in
the MIPS RISC architecture into low-cost, simplified, power-
sensitive applications.
FunctionalunitswereintegratedontotheCPUcoreinorder
toreducethetotalsystemcost,withoutsignificantlydegrading
system performance. Thus, the IDT79R3051 family is able to
offer35MIPSofintegerperformanceat40MHzwithoutrequir-
ing external SRAM or caches.
I#1
IF
RD ALU MEM WB
I#2
IF
RD ALU MEM WB
Furthermore,theIDT79R3051familybringsdramaticpower
reductiontotheseembeddedapplications, allowingtheuseof
low-costpackagingfordevicesupto25MHz. TheIDT79R3051
family allows customer applications to bring maximum per-
formance at minimum cost.
I#3
IF
RD ALU MEM WB
I#4
IF
RD ALU MEM WB
Figure 1 shows a block-level representation of the func-
tional units within the IDT79R3051 family. The IDT79R3051
family could be viewed as the embodiment of a discrete
solution built around the IDT79R3000A or IDT79R3001.
However, by integrating this functionality on a single chip,
dramatic cost and power reductions are achieved.
I#5
IF
RD ALU MEM WB
Current
CPU
Cycle
2874 drw 02
Currently, there are four members of the IDT79R3051
family. All devices are pin- and software-compatible: the
differences lie in the amount of instruction cache, and in the
memory management capabilities of the processor:
• TheIDT79R3052"E”incorporates8kBofInstructionCache,
and features a full-function Memory Management Unit
(MMU), including a 64-entry fully-associative Translation
LookasideBuffer(TLB).ThisisthesameMMUincorporated
into the IDT79R3000A and IDT79R3001.
Figure 2. R3051 Family 5-Stage Pipeline
System Control Co-Processor
The R3051 family also integrates on-chip the System
Control Co-processor, CP0. CP0 manages both the excep-
tion handling capability of the IDT79R3051 family, as well as
the virtual to physical mapping of the IDT79R3051 family.
There are two versions of the IDT79R3051 family architec-
ture: the Extended Architecture Versions (the IDT79R3051E
and IDT79R3052E) contain a fully associative 64-entry TLB
which maps 4KB virtual pages into the physical address
space. The virtual to physical mapping thus includes kernel
segments which are hard mapped to physical addresses, and
kernel and user segments which are mapped on a page basis
by the TLB into anywhere within the 4GB physical address
space. In this TLB, 8-page translations can be “locked” by the
kernel to insure deterministic response in real-time applica-
tions. These versions thus use the same MMU structure as
that found in the IDT79R3000A and IDT79R3001. Figure 3
shows the virtual-to-physical address mapping found in the
Extended Architecture versions of the processor family.
The Extended Architecture devices allow the system
designertoimplementkernelsoftwaretodynamicallymanage
User task utilization of memory resources, and also allow the
Kernel to effectively “protect” certain resources from user
tasks. These capabilities are important in a number of
embeddedapplications,fromprocesscontrol(whereresource
protection may be extremely important) to X-Window display
systems (where virtual memory management is extremely
important),andcanalsobeusedtosimplifysystemdebugging.
• TheIDT79R3052alsoincorporates8kBofInstructionCache.
However, the MMU is a much simpler subset of the capabili-
ties of the enhanced versions of the architecture, and in fact
does not use a TLB.
• TheIDT79R3051"E”incorporates4KBofInstructionCache.
Additionally, this device features the same full-function
MMU (including TLB file) as the IDT79R3052"E”, and
IDT79R3000A.
• The IDT79R3051 incorporates 4KB of Instruction Cache,
and uses the simpler memory management model of the
IDT79R3052.
An overview of the functional blocks incorporated in these
devices follows.
CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close-to single cycle execution
rate. The CPU core contains a five stage pipeline and 32
orthogonal 32-bit registers. The IDT79R3051 family imple-
ments the MIPS ISA. In fact, the execution engine of the
IDT79R3051familyisthesameastheexecutionengineofthe
IDT79R3000A (and IDT79R3001). Thus the IDT79R3051
family is binary-compatible with those CPU engines.
5.3
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IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
VIRTUAL
PHYSICAL
0xffffffff
Kernel Mapped
(kseg2)
Any
0xc0000000
0xa0000000
0x80000000
Kernel Uncached
(kseg1)
Physical
Memory
3548MB
Kernel Cached
(kseg0)
User Mapped
Cacheable
(kuseg)
Any
Memory
512MB
0x00000000
2874 drw 03
Figure 3. Virtual-to-Physical Mapping of Extended Architecture Versions
The base versions of the architecture (the IDT79R3051
When using the base versions of the architecture, the
and IDT79R3052) remove the TLB and institute a fixed system designer can implement a distinction between the
address mapping for the various segments of the virtual user tasks and the kernel tasks, without having to execute
address space. The base processors support distinct kernel page management software. This distinction can take the
andusermodeoperationwithoutrequiringpagemanagement form of physical memory protection, accomplished by ad-
software, leading to a simpler software model. The memory dress decoding, or in other forms. In systems which do not
mapping used by these devices is illustrated in Figure 4. Note wish to implement memory protection, and wish to have the
that the reserved address spaces shown are for compatibility kernel and user tasks operate out of a single unified memory
with future family members; in the current family members, space, upper address lines can be ignored by the address
references to these addresses are translated in the same decoder, and thus all references will be seen in the lower
fashion as their respective segments, with no traps or excep- gigabyte of the physical address space.
tions taken.
VIRTUAL
PHYSICAL
0xffffffff
1MB Kernel Rsvd
Kernel Cacheable
Tasks
1024MB
2048MB
Kernel Cached
(kseg2)
0xc0000000
0xa0000000
0x80000000
Kernel Uncached
(kseg1)
Kernel/User
Cacheable
Tasks
Kernel Cached
(kseg0)
1MB User Rsvd
User
Cached
(kuseg)
Inaccessible
512MB
512MB
Kernel Boot
and I/O
0x00000000
2874 drw 04
Figure 4. Virtual-to-Physical Mapping of Base Architecture Versions
5.3
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IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Clock Generation Unit
of the memory system. The write buffers capture and FIFO
processor address and data information in store operations,
and presents it to the bus interface as write transactions at the
rate the memory system can accommodate.
The IDT79R3051 family is driven from a single input clock,
capable of operating in a range of 40%-60% duty cycle. On
chip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
clock generator unit replaces the external delay line required
in IDT79R3000A and IDT79R3001 based applications.
The IDT79R3051/52 read interface performs both single
wordreadsandquadwordreads. Singlewordreadsworkwith
a simple handshake, and quad word reads can either utilize
the simple handshake (in lower performance, simple sys-
tems)orutilizeatightertimingmodewhenthememorysystem
can burst data at the processor clock rate. Thus, the system
designer can choose to utilize page or nibble mode DRAMs
(and possibly use interleaving), if desired, in high-perfor-
mance systems, or use simpler techniques to reduce com-
plexity.
In order to accommodate slower quad-word reads, the
IDT79R3051 family incorporates a 4-deep read buffer FIFO,
so that the external interface can queue up data within the
processor before releasing it to perform a burst fill of the
internal caches. Depending on the cost vs. performance
tradeoffsappropriatetoagivenapplication,thesystemdesign
engineer could include true burst support from the DRAM to
provide for high-performance cache miss processing, or uti-
lize the read buffer to process quad word reads from slower
memory systems.
Instruction Cache
The current family includes two different instruction cache
sizes: the IDT79R3051 family (the IDT79R3051 and
IDT79R3051E) feature 4KB of instruction cache, and the
IDT79R3052 and IDT79R3052E each incorporate 8KB of
Instruction Cache. For all four devices, the instruction cache
is organized as a line size of 16 bytes (four words). This
relatively large cache achieves a hit rate well in excess of 95%
in most applications, and substantially contributes to the
performance inherent in the IDT79R3051 family. The cache is
implemented as a direct mapped cache, and is capable of
caching instructions from anywhere within the 4GB physical
address space. The cache is implemented using physical
addresses (rather than virtual addresses), and thus does not
require flushing on context switch.
Data Cache
SYSTEM USAGE
All four devices incorporate an on-chip data cache of 2KB,
organized as a line size of 4 bytes (one word). This relatively
large data cache achieves hit rates well in excess of 90% in
most applications, and contributes substantially to the perfor-
manceinherentintheIDT79R3051family. Aswiththeinstruc-
tion cache, the data cache is implemented as a direct mapped
physicaladdresscache. Thecacheiscapableofmappingany
word within the 4GB physical address space.
The IDT79R3051 family has been specifically designed to
easily connect to low-cost memory systems. Typical low-cost
memory systems utilize slow EPROMs, DRAMs, and applica-
tion-specific peripherals. These systems may also typically
contain large, slow Static RAMs, although the IDT79R3051
family has been designed to not specifically require the use of
external SRAMs.
Figure 5 shows a typical system block diagram. Transpar-
ent latches are used to de-multiplex the IDT79R3051/52
address and data busses from the A/D bus. The data paths
between the memory system elements and the R3051 family
A/D bus is managed by simple octal devices. A small set of
simple PALs can be used to control the various data path
elements, and to control the handshake between the memory
devices and the CPU.
The data cache is implemented as a write through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4-
deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance.
Bus Interface Unit
DEVELOPMENT SUPPORT
The IDT79R3051 family is supported by a rich set of
development tools, ranging from system simulation tools
through prom monitor support, logic analysis tools, and sub-
system modules.
The IDT79R3051 family uses its large internal caches to
provide the majority of the bandwidth requirements of the
execution engine, and thus can utilize a simple bus interface
connected to slow memory devices.
Figure7isanoverviewofthesystemdevelopmentprocess
typically used when developing IDT79R3051 family-based
applications. The IDT79R3051 family is supported by power-
ful tools through all phases of project development. These
tools allow timely, parallel development of hardware and
software for IDT79R3051/52 based applications, and include
tools such as:
• A program, Cache-3051, which allows the performance of
an IDT79R3051 family based system to be modeled and
understood without requiring actual hardware.
The IDT79R3051 family bus interface utilizes a 32-bit
address and data bus multiplexed onto a single set of pins.
The bus interface unit also provides an ALE signal to de-
multiplex the A/D bus, and simple handshake signals to
process processor read and write requests. In addition to the
read and write interface, the IDT79R3051 family incorporates
a DMA arbiter, to allow an external master to control the
external bus.
The IDT79R3051 family incorporates a 4-deep write buffer
to decouple the speed of the execution engine from the speed
5.3
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IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
• Sable, an instruction set simulator.
• The IDT Laser Printer System board, which directly drives
a low-cost print engine, and runs Microsoft TrueImage
Page Description Language on top of PeerlessPage Ad-
vanced Printer Controller BIOS.
• Optimizing compilers from MIPS, the acknowledged leader
in optimizing compiler technology.
• IDT Cross development tools, available in a variety of
development environments.
• Adobe PostScript Page Description Language, ported to
the R3000 instruction set, runs on the IDT79R3051 family.
• The high-performance IDT floating point library software,
which has been integrated into the compiler toolchain to
allow software floating point to replace hardware floating
point without modifying the original source code.
• The IDT Prom Monitor, which implements a full prom
monitor (diagnostics, remote debug support, peek/poke,
etc.).
• An In-Circuit Emulator, developed and sold by Embedded
Performance, Inc.
• The IDT Evaluation Board, which includes RAM, EPROM,
I/O, and the IDT Prom Monitor.
Reset
Clk2xIn
Int(5:0)
IDT R3051 Family
RISController
BrCond(3:0)
BusReq
Burst/
RdCEn WrNear
BusGnt
Wr
AD(31:0)
ALE Addr(3:2) SysClk Rd
Ack
DataEn BErr
Memory and Interface
Control PALs
FCT373T
Address
Decode
PAL
DRAM Control
PALs
I/O Devices/
Peripherals
EPROM
System I/O
DRAM
FCT245T
2874 drw 05
Figure 5. Typical R3051 Family Based System
5.3
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IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Clk2xIn
IDT79R3051 Family
RISController
Address/
Data
Control
R3051 Family
Local Bus
DRAM
Controller
I/O Controller
PROM
I/O
I/O
DRAM
DRAM
IDT73720
Bus Exchanger
(2)
2874 drw 06
Figure 6. R3051 Family Chip Set Based System
5.3
6
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
System
Architecture
Evaluation
System
Development
Phase
System
Integration
and Verification
Software
SABLE Simulator
DBG Debugger
PIXIE Profiler
MIPS Compiler Suite
Stand-Alone Libraries
Floating Point Library
Cross Development Tools
Adobe PostScript PDL
MicroSoft TrueImage PDL
Ada
Logic Analysis
Diagnostics
Cache-R305x
Benchmarks
Evaluation Board
Laser Printer System
IDT PROM Monitor
Remote Debug
Real-Time OS
In-Circuit Emulator
Hardware
Cache-R305x
Hardware Models
General CAD Tools
RISC Sub-systems
Evaluation Board
Laser Printer System
2874 drw 07
Figure 7. R3051 Family Development Toolchain
5.3
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IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
PERFORMANCE OVERVIEW
THERMAL CONSIDERATIONS
The IDT79R3051 family achieves a very high level of
performance. This performance is based on:
The IDT79R3051 family utilizes special packaging tech-
niques to improve the thermal properties of high-speed pro-
• An efficient execution engine. The CPU performs ALU cessors. Thus, all versions of the IDT79R3051 family are
operations and store operations at a single cycle rate, and packaged in cavity-down packaging.
has an effective load time of 1.3 cycles, and a branch
The lowest cost members of the family use a standard
execution rate of 1.5 cycles (based on the ability of the cavity-down, injection molded PLCC package (the "J" pack-
compilers to avoid software interlocks). Thus, the execution age). This package, coupled with the power reduction tech-
engineachievesover35MIPSperformancewhenoperating niques employed in the design of the IDT79R3051 family,
out of cache.
allows operation at speeds to 25MHz. However, at higher
speeds, additional thermal care must be taken.
• Large on-chip caches. The IDT79R3051 family contains
caches which are substantially larger than those on the
majorityoftoday’sembeddedmicroprocessors.Theselarge
caches minimize the number of bus transactions required,
and allow the R3051 family to achieve actual sustained
performance, very close to its peak execution rate.
For this reason, the IDT79R3051 family is also available in
the MQUAD package (the "MJ" package), which is an all-
aluminum package with the die attached to a normal copper
lead-frame, mounted to the aluminum casing. The MQUAD
allows for more efficient thermal transfer between the die and
the case of the part due to the heat-spreading effect of the
aluminum. The aluminum offers less internal resistance from
one end of the package to the other, which reduces the
temperature gradient across the package, and, therefore,
presents a greater area for convection and conduction to the
PCB for a given temperature. Even nominal amounts of
airflowwilldramaticallyreducethejunctiontemperatureofthe
die, resulting in cooler operation. The MQUAD package is
available at all frequencies, and is pin- and form-compatible
withthePLCCpackage. Thus, designerscanchoosetoutilize
this package without changing their PCB.
• Autonomous multiply and divide operations. The
IDT79R3051 family features an on-chip integer multiplier/
divideunitwhichisseparatefromtheotherALU. Thisallows
the IDT79R3051 family to perform multiply or divide opera-
tions in parallel with other integer operations, using a single
multiply or divide instruction rather than “step” operations.
• Integrated write buffer. The IDT79R3051 family features a
four-deep write buffer, which captures store target ad-
dressesanddataattheprocessorexecutionrateandretires
it to main memory at the slower main memory access rate.
Use of on-chip write buffers eliminates the need for the
processor to stall when performing store operations.
The members of the IDT79R3051 family are guaranteed in
a case temperature range of 0°C to +85°C. The type of
• Burst read support. The IDT79R3051 family enables the package, speed (power) of the device, and airflow conditions
system designer to utilize page mode or nibble mode RAMs affect the equivalent ambient conditions which meet this
when performing read operations to minimize the main specification.
memory read penalty and increase the effective cache hit
rates.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(ØCA) of the given package. The following equation relates
ambient and case temperature:
Thesetechniquescombinetoallowtheprocessortoachieve
35MIPS integer performance, and over 64,000 dhrystones at
40MHz without the use of external caches or zero wait-state
memory devices.
TA = TC - P * ØCA
where P is the maximum power consumption at hot tempera-
ture, calculated by using the maximum ICC specification for
the device.
SELECTABLE FEATURES
The IDT79R3051 family allows the system designer to
configure some aspects of operation. These aspects are
established when the device is reset and include:
• Big Endian vs. Little Endian operation: The part can be
configured to operate with either byte ordering convention,
and in fact may also be dynamically switched between the
two conventions. This facilitates the porting of applications
from other processor architectures, and also permits inter-
communications between various types of processors and
databases.
Typical values for ØCA at various airflows are shown in
Table 1 for the various packages.
Airflow (ft/min)
ØCA
0
200
400
600
800
1000
"J" Package
29
26
21
18
16
15
"MJ" Package*
22
14
12
11
9
8
2874 tbl 01
• Data cache refill of one or four words: The memory
system must be capable of performing 4-word transfers to
satisfy cache misses. This option allows the system de-
signer to choose between one- and four-word refill on data
cache misses, depending on the performance each option
brings to his application.
Table 1. Thermal Resistance (ØCA) at Various Airflows
(*estimated: final values tbd)
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IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
PIN NAME
I/O
DESCRIPTION
A/D(31:0)
I/O
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
Address(31:4):
(3:0):
The high-order address for the transfer is presented on A/D(31:4).
These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are represented on A/D(3:0).
BE
During write cycles, the bus contains the data to be stored and is driven from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in either a single data transaction
or in a burst of four words, and places it into the on-chip read buffer.
Addr(3:2)
Diag(1)
O
O
Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor.
Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes
or single datum reads) or functions as a two bit counter starting at ‘00’ for burst read operations.
Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an on-
chip cache miss, and also presents part of the miss address. The value output on this pin is time
multiplexed:
Cached:
DuringthephaseinwhichtheA/Dbuspresentsaddressinformation, this
pin is an active high output which indicates whether the current read is
a result of a cache miss. The value of this pin at this time in other than
read cycles is undefined.
Miss Address (3):
During the remainder of the read operation, this output presents address
bit(3)oftheaddresstheprocessorwasattemptingtoreferencewhenthe
cache miss occurred. Regardless of whether a cache miss is being
processed, this pin reports the transfer address during this time.
Diag(0)
O
Diagnostic Pin 0. This output distinguishes cache misses due to instruction references from those due
to data references, and presents the remaining bit of the miss address. The value output on this pin is
also time multiplexed:
I/ :
D
If the “Cached” Pin indicates a cache miss, then a high on this pin at this
time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an uncached
reference, then this pin is undefined during this phase.
Miss Address (2):
During the remainder of the read operation, this output presents address
bit(2)oftheaddresstheprocessorwasattemptingtoreferencewhenthe
cache miss occurred. Regardless of whether a cache miss is being
processed, this pin reports the transfer address during this time.
ALE
O
O
Address Latch Enable: Used to indicate that the A/D bus contains valid address information for the bus
transaction. This signal is used by external logic to capture the address for the transfer, typically using
transparent latches.
DataEn
External Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor
during read cycles, and thus the external memory system may enable the drivers of the memory system
onto this bus without having a bus conflict occur. During write cycles, or when no bus transaction is
occurring, this signal is negated, thus disabling the external memory drivers.
2874 tbl 02
5.3
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IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (Continued):
PIN NAME
I/O
DESCRIPTION
Burst/
WrNear
O
Burst Transfer/Write Near: On read transactions, the Burst signal indicates that the current bus read
is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles
due to cache misses; it is asserted for all I-Cache miss read cycles, and for D-Cache miss read cycles
if selected at device reset time.
On write transactions, the WrNear output tells the external memory system that the bus interface unit
is performing back-to-back write transactions to an address within the same 256 word page as the prior
write transaction. This signal is useful in memory systems which employ page mode or static column
DRAMs, and allows near writes to be retired quickly.
Rd
O
O
I
Read: An output which indicates that the current bus transaction is a read.
Write: An output which indicates that the current bus transaction is a write.
Wr
Ack
Acknowledge: An input which indicates to the device that the memory system has sufficiently
processedthebustransaction, andthattheCPUmayeitherterminatethewritecycleorprocesstheread
data from this read transfer.
RdCEn
SysClk
I
Read Buffer Clock Enable: An input which indicates to the device that the memory system has placed
valid data on the A/D bus, and that the processor may move the data into the on-chip Read Buffer.
O
System Reference Clock: An output from the CPU which reflects the timing of the internal processor
"Sys" clock. This clock is used to control state transitions in the read buffer, write buffer, memory
controller, and bus interface unit.
BusReq
BusGnt
I
DMAArbiterBusRequest: AninputtothedevicewhichrequeststhattheCPUtri-stateitsbusinterface
signals so that they may be driven by an external master.
O
I
DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been
detected, and that the bus is relinquished to the external master.
SBrCond(3:2)
BrCond(1:0)
Branch Condition Port: These external signals are internally connected to the CPU signals
CpCond(3:0). These signals can be used by the branch on co-processor condition instructions as input
ports. There are two types of Branch Condition inputs: the SBrCond inputs have special internal logic
tosynchronizetheinputs, andthusmaybedrivenbyasynchronousagents. ThedirectBranchCondition
inputs must be driven synchronously.
BErr
I
I
Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error.
This signal is only sampled during read and write operations. If the bus transaction is a read operation,
then the CPU will take a bus error exception.
Int(5:3)
SInt(2:0)
Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0)
signals of the R3000. During processor reset, these signals perform mode initialization of the CPU, but
in a different (simpler) fashion than the interrupt signals of the R3000.
There are two types of interrupt inputs: the SInt inputs are internally synchronized by the processor, and
may be driven by an asynchronous external agent. The direct interrupt inputs are not internally
synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have
one cycle lower latency than the synchronized interrupts.
Clk2xIn
Reset
I
I
Master Clock Input: This is a double frequency input used to control the timing of the CPU.
Master Processor Reset: This signal initializes the CPU. Mode selection is performed during the last
cycle of Reset.
Rsvd(4:0)
I/O
Reserved: These five signal pins are reserved for testing and for future revisions of this device. Users
must not connect these pins.
2874 tbl 03
5.3
10
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1, 3)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to +7.0
V
Grade
Commercial
Temperature
0°C to +85°C
(Case)
GND
0V
VCC
5.0 ±5%
2874 tbl 06
TC
Operating Case
Temperature
0 to +85
°C
°C
°C
TBIAS
TSTG
Temperature
Under Bias
–55 to +125
–55 to +125
–0.5 to +7.0
Storage
Temperature
OUTPUT LOADING FOR AC TESTING
+4mA
VIN
Input Voltage
V
NOTES:
2874 tbl 04
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
abovethoseindicatedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
VREF
–
To Device
Under Test
+
+1.5V
2. VIN minimum = –3.0V for pulse width less than 15ns.
VIN should not exceed VCC +0.5V.
25pF
3. Notmorethanoneoutputshouldbeshortedatatime. Durationoftheshort
should not exceed 30 seconds.
–4mA
2874 drw 08
AC TEST CONDITIONS
Symbol
Parameter
Min.
3.0
—
Max.
—
0
Unit
V
VIH
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input LOW Voltage
VIL
V
VIHS
VILS
3.5
—
—
0
V
V
2874 tbl 05
DC ELECTRICAL CHARACTERISTICS (TC = 0°C to +85°C, VCC = +5.0V ±5%)
20MHz
25MHz
33.33MHz
40MHz
Symbol Parameter
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
VOL
VIH
VIL
Output HIGH Voltage
Output LOW Voltage
VCC = Min., IOH = –4mA
3.5
—
—
0.4
—
3.5
—
—
0.4
—
3.5
—
—
0.4
—
3.5
—
—
0.4
—
V
V
VCC = Min., IOL = 4mA
(3)
Input HIGH Voltage
—
2.0
—
2.0
—
2.0
—
2.0
—
V
(1)
Input LOW Voltage
Input HIGH Voltage
—
0.8
—
0.8
—
0.8
—
0.8
—
V
(2,3)
VIHS
VILS
CIN
COUT
ICC
—
3.0
—
3.0
—
3.0
—
3.0
—
V
(1,2)
Input LOW Voltage
—
—
0.4
10
0.4
10
0.4
10
0.4
10
10
V
(4)
Input Capacitance
—
—
—
—
pF
pF
(4)
Output Capacitance
Operating Current
—
—
10
—
10
—
10
—
VCC = 5V, TC = 25°C
VIH = VCC
—
350
100
—
—
400
100
—
—
450
100
—
—
500 mA
IIH
Input HIGH Leakage
Input LOW Leakage
Output Tri-state Leakage
—
—
—
—
100
—
µA
µA
IIL
VIL = GND
–100
–100
–100
–100
–100
IOZ
VOH = 2.4V, VOL = 0.5V
100 –100
100 –100
100 –100 100
µA
2874 tbl 07
NOTES:
1. VIL Min. = –3.0V for pulse width less than 15ns. VIL should not fall below –0.5V for larger periods.
2. VIHS and VILS apply to CIk2xIn and Reset.
3. VIH should not be held above VCC + 0.5V.
4. Guaranteed by design.
5.3
11
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
(1, 2, 3)
AC ELECTRICAL CHARACTERISTICS
(TC = 0°C to +85°C, VCC = +5.0V ±5%)
20MHz
25MHz
33.33MHz
40MHz
Min. Max. Unit
Symbol
Signals
Description
Min.
Max.
Min.
Max.
Min. Max.
t1
BusReq, Ack, BusError,
RdCEn,
Set-up to SysClk rising
6
—
5
—
4
—
3
—
ns
t1a
t2
A/D
Set-up to SysClk falling
Hold from SysClk rising
7
4
—
—
6
4
—
—
5
3
—
—
4.5
3
—
—
ns
ns
BusReq, Ack, BusError,
RdCEn,
t2a
t3
A/D
Hold from SysClk falling
2
—
2
—
1
—
1
—
A/D, Addr, Diag, ALE, Wr
Burst/WrNear, Rd, DataEn
Tri-state from SysClk rising
—
10
—
10
—
10
—
10
ns
ns
t4
A/D, Addr, Diag, ALE, Wr
Burst/WrNear, Rd, DataEn
Driven from SysClk falling
—
10
—
10
—
10
—
10
t5
BusGnt
Asserted from SysClk rising
Negated from SysClk falling
Valid from SysClk rising
—
—
—
—
—
2
8
8
—
—
—
—
—
2
7
7
—
—
—
—
—
1.5
—
0
6
6
—
—
—
—
—
1.5
—
0
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tsys
ns
ns
ns
ns
ns
ns
ns
t6
BusGnt
t7
Wr, Rd, Burst/WrNear, A/D
5
5
4
3.5
3
t8
ALE
Asserted from SysClk rising
Negated from SysClk falling
Hold from ALE negated
4
4
3
t9
ALE
4
4
3
3
t10
t11
t12
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
tsys
t32
t33
tderate
A/D
—
15
—
—
7
—
15
—
—
6
—
13
—
—
5
—
12
—
—
4
DataEn
DataEn
A/D
Asserted from SysClk falling
Asserted from A/D tri-state(4)
Driven from SysClk rising(4)
—
0
—
0
0
0
0
0
Wr, Rd, DataEn, Burst/WrNear Negated from SysClk falling
—
—
—
—
—
10
10
25
200
32
6
—
—
—
—
—
8
—
—
—
—
—
6.5
6.5
15
200
32
4
—
—
—
—
—
5.6
5.6
12.5
200
32
3
Addr(3:2)
Diag
Valid from SysClk
6
6
5
4.5
9
Valid from SysClk
12
10
12
—
—
250
—
—
—
—
—
—
—
—
—
11
10
11
—
—
250
—
—
—
—
—
—
—
—
—
10
9
A/D
Tri-state from SysClk falling
SysClk falling to data out
Pulse Width HIGH
8
A/D
10
—
—
250
—
—
—
—
—
—
—
—
—
9
Clk2xIn
Clk2xIn
Clk2xIn
Reset
—
—
250
—
—
—
—
—
—
—
—
—
Pulse Width LOW
8
Clock Period
20
200
32
5
Pulse Width from Vcc valid
Minimum Pulse Width
Set-up to SysClk falling
Mode set-up to Reset rising
Mode hold from Reset rising
Set-up to SysClk falling
Hold from SysClk falling
Set-up to SysClk falling
Hold from SysClk falling
Pulse Width
Reset
Reset
Int
6
5
4
3
Int
2.5
6
2.5
5
2.5
4
2.5
3
SInt, SBrCond
SInt, SBrCond
Int, BrCond
Int, BrCond
SysClk
SysClk
SysClk
All outputs
3
3
2
2
6
5
4
3
3
3
2
2
2*t22
2*t22 2*t22
2*t22 2*t22
2*t22 2*t22 2*t22
Clock HIGH Time
t22 – 2 t22 + 2 t22 – 2 t22 + 2 t22 – 1 t22 + 1 t22 – 1 t22 + 1 ns
t22 – 2 t22 + 2 t22 – 2 t22 + 2 t22 – 1 t22 + 1 t22 – 1 t22 + 1 ns
Clock LOW Time
Timing deration for loading
over 25pf(4, 5)
—
0.5
—
0.5
—
0.5
—
0.5
ns/
25pF
NOTES:
2874 tbl 08
1. All timings referenced to 1.5V, with a rise and fall time of less than 2.5ns.
2. All outputs tested with 25pF loading.
3. The AC values listed here reference timing diagrams contained in the R3051 Family Hardware User's Manual.
4. Guaranteed by design.
5. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified
test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.
5.3
12
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
1
84
75
VSS
VCC
12
VSS
VCC
Clk2xIn
Rsvd(4)
Rsvd(3)
Rsvd(2)
Rsvd(1)
Rsvd(0)
Int(5)
A/D(14)
A/D(13)
A/D(12)
A/D(11)
A/D(10)
A/D(9)
VCC
VSS
VSS
VCC
A/D(8)
A/D(7)
A/D(6)
A/D(5)
A/D(4)
A/D(3)
VSS
Int(4)
Int(3)
SInt(2)
SInt(1)
SInt(0)
SBrCond(3)
SBrCond(2)
BrCond(1)
VSS
VCC
A/D(2)
A/D(1)
VCC
54
A/D(0)
33
2874 drw 09
84-Pin PLCC/MQUAD
Top View
NOTE:
Reserved Pins must not be connected.
5.3
13
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
t22
t
21
Clk2xIn
SysClk
t20
t
32
t33
2874 drw 11
t
sys
Figure 8. R3051 Family Clocking
VCC
ClkIn
Reset
t23
2874 drw 12
Figure 9. Power-On Reset Sequence
SysClk
Reset
t24
2874 drw 13
Figure 10. Warm Reset Sequence
SysClk
Reset
t25
SInt(n),
Int(n)
t26
2874 drw 14
t27
Figure 11. Mode Selection and Negation of Reset
5.3
14
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Run/
Fixup/
Stall
Stall
Stall
Stall
Stall
Stall
Fixup
PhiClk
SysClk
Rd
t7
t15
t14
t18
t14
t1a
Addr
BE
Data Input
t2a
A/D(31:0)
Addr(3:2)
t16 t10
Word Address
t8
ALE
t9
t12
t15
DataEn
Burst
t11
t7
t1
RdCEn
t2
ACK
t17
Cached?
t17
Miss Address(3)
Diag(1)
I/D
Miss Address(2)
Diag(0)
Start
Read
Turn
Bus
ACK/
RdCen
Sample
Data
End
Read
ACK?
ACK?
2874 drw 15
Figure 12. Single Datum Read in R3051 Family
5.3
15
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Run/
Fixup/
Stall
Stall
Stall
Stall
Word 0
Word 1
Word 2
Word 3
PhiClk
SysClk
Rd
t
7
t
15
t14
t14
t18
t
1a
Word 0
2a
t
1a
Word 1
2a
t
1a
Word 2
2a
t
1a
Word 3
2a
Addr
BE
A/D(31:0)
Addr(3:2)
ALE
t
t
t
t
t16
t10
'00'
'01'
'10'
'11'
t
16
t16
t16
t9
t8
t
12
t15
DataEn
Burst
t11
t7
t1
t
1
t1
t1
RdCEn
ACK
t2
t2
t2
t2
t17
t17
Cached?
Miss Address(3)
Miss Address(2)
Diag(1)
Diag(0)
I/D
Start
Read
Turn
Bus
ACK/ Sample RdCEn Sample RdCEn Sample RdCEn Sample
New
RdCen Data Data Data Data Transaction
2874 drw 16
Figure 13. R3051 Family Burst Read
5.3
16
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Stall
Stall
Stall
Stall
PhiClk
SysClk
Rd
t1a
t1a
Word 0
Word 1
A/D(31:0)
Addr(3:2)
ALE
t2a
t2a
'00'
'01'
'10'
t16
t16
DataEn
Burst
t1
t1
t1
RdCEn
ACK
t2
t2
t2
Sample
Data
Sample
Data
Sample
Data
RdCEn
RdCEn
RdCEn
2874 drw 17
Figure 14 (a). Start of Throttled Quad Read
5.3
17
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Refill/
Stream/
Fixup
Stall
Word 0
Word 1
Word 2
Word 3
PhiClk
SysClk
Rd
t15
t14
t1a
Word 2
t1a
Word 3
A/D(31:0)
Addr(3:2)
ALE
t2a
t2a
'01'
'11'
t16
t15
DataEn
Burst
t1
t1
t1
RdCEn
t2
t2
t2
t1
ACK
t2
ACK
RdCEn
Sample
Data
RdCEn Sample
Data
New
Transaction
2874 drw 18
Figure 14 (b). End of Throttled Quad Read
5.3
18
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
SysClk
t7
t
15
Wr
A/D(31:0)
Addr(3:2)
ALE
t14
t19
t
14
Addr
BE
Data
Out
t
10
t
16
Word Address
t
8
t
9
t7
t
15
WrNear
ACK
t2
t
1
Start
Write
Data
Out
ACK
Negate
Wr
New
Transfer
ACK
ACK
2874 drw 19
Figure 15. R3051 Family Write Cycle
SysClk
BusReq
BusGnt
A/D(31:0)
Addr(3:2)
Diag(1:0)
Rd
t2
t1
t5
t3
Wr
ALE
Burst/
WrNear
2874 drw 20
Figure 16. Request and Relinquish of R3051 Family Bus to External Master
5.3
19
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
SysClk
t2
BusReq
t1
t6
BusGnt
t4
A/D(31:0)
Addr(3:2)
Diag(1:0)
Rd
Wr
ALE
Burst/
WrNear
2874 drw 21
Figure 17. R3051 Family Regaining Bus Mastership
5.3
20
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
Run Cycle
Exception Vector
Phi
SysClk
SInt(n)
t 28 t 29
2874 drw 22
Figure 18. Synchronized Interrupt Input Timing
Run Cycle
Exception Vector
Phi
SysClk
Int(n)
2874 drw 23
t30
t31
Figure 19. Direct Interrupt Input Timing
Run Cycle
Capture BrCond
BCzT/F Instruction
Phi
SysClk
SBrCond(n)
t
28
t29
2874 drw 24
Figure 20. Synchronized Branch Condition Input Timing
Run Cycle
Capture BrCond
BCzT/F Instruction
Phi
SysClk
BrCond(n)
2874 drw 25
t30
t31
Figure 21. Direct Branch Condition Input Timing
5.3
21
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
84 LEAD PLCC/MQUAD(7) (SQUARE)
A
D
D1
A1
PIN 1
C
45° x .045
D3/E3
E1
E
D2/E2
b1
B
e
C1
SEATING PLANE
2874 drw 27
NOTES:
1. All dimensions are in inches, unless otherwise noted.
2. BSC—Basic lead Spacing between Centers.
3. D & E do not include mold flash or protutions.
4. Formed leads shall be planar with respect to one another and within .004” at the seating plane.
5. ND & NE represent the number of leads in the D & E directions respectively.
6. D1 & E1 should be measured from the bottom of the package.
7. MQUAD is pin & form compatible with PLCC.
DWG #
J84-1
84
MJ84-1
84
# of Leads
Symbol
Min.
165
Max.
.180
Min.
165
Max.
A
A1
.180
.114
.095
.026
.013
.020
.008
1.185
1.150
1.090
.115
.094
.026
.013
.020
.008
1.185
1.140
1.090
B
.032
.032
b1
.021
.021
C
.040
.040
C1
.012
.012
D
1.195
1.156
1.130
1.195
1.150
1.130
D1
D2/E2
D3/E3
E
1.000 REF
1.000 REF
1.185
1.150
1.195
1.156
1.185
1.140
1.195
1.150
E1
e
.050 BSC
21
.050 BSC
21
ND/NE
5.3
22
IDT79R3051/79R3052 INTEGRATED RISControllers
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXXXX
-
XX
X
X
IDT
Device Type
Speed Package Process/
Temp. Range
Blank
Commercial Temperature Range
'J'
'MJ'
84-Pin PLCC
84-Pin MQUAD
'20'
'25'
'33'
'40'
20.0 MHz
25.0 MHz
33.33 MHz
40.0 MHz
79R3051
79R3051E
79R3052
79R3052E
4kB Instruction Cache, No TLB
4kB Instruction Cache, With TLB
8kB Instruction Cache, No TLB
8kB Instruction Cache, With TLB
2874 drw 28
VALID COMBINATIONS
IDT 79R3051 - 20, 25
79R3051E - 20, 25
79R3052 - 20, 25
J Packages Only
J Packages Only
J Packages Only
J Packages Only
79R3052E - 20, 25
79R3051 - 33, 40
79R3051E - 33, 40
79R3052 - 33, 40
79R3052E - 33, 40
MJ Packages Only
MJ Packages Only
MJ Packages Only
MJ Packages Only
5.3
23
相关型号：
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