IDT79RC64T575200DPG_技术文档

79RC64574^™

79RC64575^™

Advanced 64-bit

Microprocessors

Product Family

◆

Big- or Little-endian capability

RC5000 compatible memory management

Features

◆

High-performance 64-bit embedded Microprocessor

–

On-chip 48-entry, 96-page TLB, for advanced operating

system support

–

250MHz operating frequency

>330 Dhrystone MIPS performance

300MFLOPS/s floating-point performance

Up to 125 million multiply accumulate per second (MAC/s)

MIPS-IV Instruction Set Architecture (ISA), with integer DSP

and 3-operand integer multiply extensions

–

Compatible with major operating systems:

Windows^®CE, VxWorks, and others

◆

Bus compatible with IDT 64-bit microprocessor families

–

Pipeline runs at 2 to 8 times the bus frequency

Bus speeds to 125MHz

32-bit bus option, for lower cost systems

Enhanced timing protocol for SyncDRAM systems (compatible

with IDT79RC64474/475)

–

Limited dual-issue microarchitecture

–

◆

Compatible with RC4640 and RC32364 DSP extensions

–

DSP Extensions, for consumer applications

2-cycle repeat rate, on atomic Multiply-add

Multiply-subtract (MSUB) support, for complex number

processing

◆

RC64574:

–

32-bit SysAd bus, for low-cost systems

Pin compatible with RC4640 and RC64474

128-pin QFP package

–

Count-leading-zero/one support, for string searches and

normalization

◆

High-performance on-chip cache subsystem

RC64575:

–

32kB, two-set associative instruction cache (I-cache)

32kB, two-set associative data cache (D-cache)

Write-through and write-back data cache operations

High-performance cache-ops, bandwidth management

–

64-bit SysAd bus interface

Pin compatible with RC4650 and RC64475

208-pin QFP package

–

◆

Industrial temperature range support

JTAG Boundary Scan Interface

◆

I-cache and D-cache locking capability (per line), provides

improved real-time support

2.5V operation with 3.3V tolerant I/O

Joint TLB on-chip, for virtual-to-physical address mapping

Block Diagram

PLL

64-bit

Integer

Execution Unit

666 MFIOPS

IEEE 1284

Floating-Point

Accelerator

DSP

Accelerator

RC5000

Compatible

System Control

Coprocessor

Dual-Issue Instruction Fetch Unit

Primary Cache Controller

48-entry

96-page

TLB

32kB

2 set-associative

Data

2 set-associative

Instruction

Cache

(Lockable)

64-bit/32-bit

RC64474/475 Compatible

System Interface

ClkIn

Figure 1 RC64574/RC64575 Block Diagram

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

1 of 28

December 14, 2001

DSC 5607

79RC64574™ 79RC64575™

Device Overview¹

IDT’s 79RC64574/575 processors serve a wide range of perfor-

mance-critical embedded applications that include high-end internet-

working systems, digital set-top boxes, web browsers, color printers,

and graphics terminals.

Instruction Issue Mechanism

The RC64574 and RC64575 are limited dual-issue super-scalar

machines that use a traditional 5-stage integer pipeline, as shown in the

pipeline diagram on Page 3. For multi-issue operations, these devices

recognize the following two general classes of instructions:

◆

Floating-point ALU

The RC64574/575 allow a socket compatible upgrade path for IDT’s

RC4640/50 and RC64474/475 processors. This unprecedented upgrad-

ability allows a 2:1 range of frequencies; 4:1 range of cache size; 15:1

range of floating-point; and 4:1 range of DSP performance in a single

socket.

◆

All others

Such a broad separation of instruction classes insure that there are

no data dependencies to restrict multi-issue performance. As they are

brought on-chip, these instruction classes are pre-decoded by the

RC64574/575, and the class information is then stored in the instruction

cache. Assuming there are no pending resource conflicts, the devices

can issue one instruction per class per pipeline clock cycle.

With special emphasis on system bandwidth, floating- point and DSP

operations, the RC64574/575 have been optimized for high-perfor-

mance applications through the integration of high-performance compu-

tational units and a high-performance memory hierarchy. The result is a

low-cost CPU that is capable of more than 330 Dhrystone MIPS.

Through the RC64574/64575 processors IDT offers:

However, longer latency resources—in either the floating-point ALU

(for example, division or square root instructions) or integer unit (such as

multiply)—can restrict the issue of instructions. Note that these proces-

sors do not perform out-of-order or speculative execution; instead, the

pipeline slips until the required resource becomes available.

◆

High-performance upgrade paths to existing embedded

customers in the internetworking, office automation and

visualization markets.

On dual-issue instruction pairs, there are no alignment restrictions,

and the RC64574/575 fetch two instructions from the cache per cycle.

Thus, for optimal performance, compilers should attempt to align branch

targets to allow dual-issue on the first target cycle, because the instruc-

tion cache only performs aligned fetches.

◆

Significant floating-point performance improvements over

currently available, moderately priced MIPS CPUs.

◆

Performance improvements through the use of the MIPS-IV ISA.

◆

High-performance DSP acceleration

1.

Detailed system operation information is provided in the RC64574/RC64575

user’s manual.

RISCore4000/RISCore5000 Family of Socket Compatible Processors

32-bit External Bus Processors 64-bit External Bus Processors

RC4640

RC64474

RC64574

RC4650

RC64475

RC64575

64-bit RISCore4000 w/ 64-bit RISCore4000

DSP extensions

64-bit RISCore5000 w/

DSP extensions

64-bit RISCore4000 w/ 64-bit RISCore4000

DSP extensions

64-bit RISCore5000 w/

DSP extensions

CPU

>350MIPS

>330MIPS

>350MIPS

>330MIPS

Performance

FPA

89 mflops, single preci- 125 mflops, single and

sion only

666 mflops, single and

double precision

89 mflops, single preci- 125 mflops, single and 666 mflops, single and

sion only

double precision

8kB/8kB, 2-way,

lockable by set

16kB/16kB, 2-way,

lockable by set

32kB/32kB, 2-way,

lockable by line

8kB/8kB, 2-way,

lockable by set

16kB/16kB, 2-way,

lockable by set

32kB/32kB, 2-way,

lockable by line

Caches

32-bit

32-bit, Superset pin

compatible w/RC4640

32-bit, Superset pin

compatible w/RC4640,

RC64474

32- or 64-bit

32-or 64-bit, Superset

pin compatible w/

RC4650

32-or 64-bit, Superset

pin compatible w/

RC4650, RC64475

External Bus

3.3V

2.5V

3.3V

2.5V

Voltage

100-267 MHz

128 PQFP

Base-Bounds

180-250 MHz

128 QFP

200-250 MHz

128 QFP

100-267 MHz

208 QFP

180-250 MHz

208 QFP

250 MHz

208 QFP

96 page TLB

Frequencies

Packages

MMU

96 page TLB

Base-Bounds

96 page TLB

Cache locking, on-chip Cache locking, JTAG,

Cache locking, JTAG,

Cache locking, on-chip Cache locking, JTAG,

Cache locking, JTAG,

syncDRAM mode, 32-

64- bit bus option

Key Features

MAC, 32-bit external

bus

syncDRAM mode, 32-bit syncDRAM mode, 32-bit MAC, 32-bit & 64 bit

external bus external bus bus option

syncDRAM mode, 32-

64- bit bus option

Table 1 RISCore4000/RISCore5000 Processor Family

2 of 28

December 14, 2001

79RC64574™ 79RC64575™

Load and branch latencies are minimized by the short pipeline of the

RC64574/575, and the caches contain special logic that will allow any

combination of loads and stores to execute in back-to-back cycles

without requiring pipeline slips or stalls, assuming the operation does

not miss in the cache.

Instruction Set Architecture

The RC64574/575 implement a superset of the MIPS-IV 64-bit ISA,

including CP1 and CP1X functional units and their instruction set. Both

32- and 64-bit data operations are performed by utilizing thirty-two

general purpose 64-bit registers (GPR) that are used for integer opera-

tions and address calculation. The complete on-chip floating-point co-

processor (CP1)—which includes a floating-point register file and execu-

tion units—forms a “seamless” interface, decoding and executing

instructions in parallel with the integer unit.

Computational Units

The RC64574/575 implement a full, single-cycle 64-bit arithmetic

logic unit (ALU), for Integer ALU functions other than multiply and

divide. Bypassing is used to support back-to-back ALU operations at the

full pipeline rate, without requiring stalls for data dependencies.

CP1’s floating-point execution units support both single and

double precision arithmetic—as specified in the IEEE Standard 754—

and are separated into a multiply unit and a combined add/convert/

divide/square root unit. Overlap of multiplies and add/subtract is

supported, and the multiplier is partially pipelined, allowing the initiation

of a new multiply instruction every fourth pipeline cycle. The floating-

point register file is made up of thirty-two 64-bit registers. The floating-

point unit can take advantage of the 64-bit wide data cache and issue a

co-processor load or store doubleword instruction in every cycle.

To allow the longer latency operations to run in parallel with other

operations, the Integer Multiply/Divide unit of the RC64574/ 575 is

separated from the primary ALU. The pipeline stalls only if an attempt to

access the HI or LO registers is made before an operation completes.

The Floating-point ALU unit is responsible for all of the CP1/CP1X

ALU operations—other than DIV/SQRT operations—and is pipelined to

allow a single-cycle repeat rate for single-precision operations.

The system control coprocessor (CP0) registers are also incorpo-

rated on-chip and provide the path through which the virtual memory

system’s page mapping is examined and changed, exceptions are

handled, and any operating mode selections are controlled. A secure

user processing environment is provided through the user, supervisor,

and kernel operating modes of virtual addressing to system software.

Bits in a status register determine which of these modes is used.

The Floating-point DIV/SQRT unit is separated from the floating-

point ALU, to ensure that these longer latency operations do not prevent

the issue of other floating-point operations. Separate logical units are

also provided on the RC64574/575 to implement load, store, and branch

operations.

Intended to enhance the performance of DSP algorithms such as fast

fused multiply-adds, multiply-subtracts and three operand multiply oper-

ations, new instructions have been added over and above the MIPS-IV

ISA.

Integer Pipeline

The integer instruction execution speed is tabulated—in number of

pipeline clocks—as follows:

System Interfaces

Operation

Latency

Repeat

The RC64575 supports a 64-bit system interface that is pin and

bus compatible with the RC4650 and RC64475 system interface. The

system interface consists of a 64-bit Address/Data bus with eight parity-

check bits and a 9-bit command bus.

Load

Store

2

4

6

1

3

5

MULT/MULTU

DMULT/DMULTU

DIV/DIVU

During 64-bit operation, RC64575 system address/data (SysAD)

transfers are protected with an 8-bit parity check bus, SysADC. When

initialized for 32-bit operation, the RC64575’s SysAD can be viewed as a

32-bit multiplexed bus that is protected by four parity-check bits.

36

68

3

36

68

2

DDIV/DDIVU

MAD/MADU

MSUB/MSUBU

Other Integer ALU

Branch

The RC64574 supports a 32-bit system interface that is pin and

bus compatible with the RC4640 and RC64474. During 32-bit operation,

SysAD transfers are performed on a 32-bit multiplexed bus (SysAD

31:0) that is protected by 4 parity check bits (SysADC 6:0).

4

3

1

2

Writes to external memory—whether they are cache miss write-

backs, stores to uncached or write-through addresses—use the on-chip

write buffer. The write buffer holds a maximum of four 64-bit addresses

and 64-bit data pairs. The entire buffer is used for a data cache write-

back and allows the processor to proceed in parallel with memory

updates.

Jump

2

Table 2 Integer Instruction Execution Speed

To insure that the maximum frequency of operation is not limited by

the speed of the multiplier unit, a “fast multiply” disable reset mode bit

(see Table 2) is featured. When this bit is asserted, each multiply opera-

tion shown in Table 1 has its latency and repeat rate increased by one

cycle.

Included in the system interface are six handshake signals:

RdRdy*, WrRdy*, ExtRqst*, Release*, ValidOut*, and ValidIn*; six inter-

rupt inputs, and a simple timing specification that is capable of trans-

3 of 28

December 14, 2001

79RC64574™ 79RC64575™

ferring data between the processor and memory at a peak rate of

1000MB/sec. A boot-time selectable option to run the system interface

as 32-bits wide—using basically the same protocols as the 64-bit

system—is also supported.

Serial

Bit

Description

Value & Mode Setting

Timer interrupt settings:

0: Enable Timer Interrupt on Int(5)

1: Disable Timer Interrupt on Int(5)

11

TimerIntEn

A boot-time mode control interface initializes fundamental

processor modes and is a serial interface that operates at a very low

frequency (SysClock divided by 256). This low-frequency operation

allows the initialization information to be kept in a low-cost EPROM;

alternatively, the twenty-or-so bits could be generated by the system

interface ASIC or a simple PAL. The boot-time serial stream is shown in

Table 3.

12

System Interface Interface bus width control settings:

Bus Width.

0: 64-bit system interface

1: 32-bit system interface

13:14

Drv_Out

Bit 14 is MSB

Slew rate control of the output drivers:

10: 100% strength (fastest)

11: 83% strength

00: 67% strength

01: 50% strength (slowest)

Serial

Description

Value & Mode Setting

Must be set to 0.

Bit

15:17

Write address to From 0 to 7 SysClk cycles:

write data delay. 0: AD...

1: AxD...

0

Reserved

1:4

Transmit-data- 64-bit bus width:

pattern.

Bit 4 is MSB

2: AxxD...

3: AxxxD...

4: AxxxxD...

5: AxxxxxD...

6: AxxxxxxD...

7: AxxxxxxxD...

0: DDDD

1: DDxDDx

2: DDxxDDxx

3: DxDxDxDx

4: DDxxxDDxxx

5: DDxxxxDDxxxx

6: DxxDxxDxxDxx

7: DDxxxxxxDDxxxxxx

8: DxxxDxxxDxxxDxxx

9-15: Reserved. Must not be selected.

18

19

Reserved

User must select ‘0’

Extend

Multiplication

Repeat Rate.

Initial setting of the “Fast Multiply” bit.

0: Enable Fast Multiply

1: Do not Enable Fast Multiply

32-bit bus width:

0: WWWWWWWW

1: WWxWWxWWxWWx

Note: For pipeline speeds >250MHz, this bit must

be set to ‘1’.

2: WWxxWWxxWWxxWWxx

3: WxWxWxWxWxWxWxWx

20:24

25:26

Reserved

User must select ‘0’

System

configuration

identifier.

Software visible in processorConfig[21:20]

0: Config[21:20] = Mode Bit [25:26]

Must be set to 0.

4: WWxxxWWxxxWWxxxWWxxx

5: WWxxxxWWxxxxWWxxxxWWxxxx

6: WxxWxxWxxWxxWxxWxxWxxWxx

7: WWxxxxxxWWxxxxxxWWxxxxxxWWxxxxxx

8: WxxxWxxxWxxxWxxxWxxxWxxxWxxxWxxx

9-15: Reserved. Must not be selected.

27:256 Reserved

User must select ‘0’

Table 3 Boot-time Mode Stream (Page 2 of 2)

The clocking interface allows the CPU to be easily mated with

external reference clocks. The CPU input clock is the bus reference

clock and can be between 33 and 125MHz. An on-chip phase-locked-

loop (PLL) generates the pipeline clock (PClock) through multiplication

of the system interface clock by values of 2,3,4,5,6,7 or 8, as defined at

system reset. This allows the pipeline clock to be implemented at a

significantly higher frequency than the system interface clock. The

RC64574/575 support both single data (one byte through full CPU bus

width) and 8-word block transfers on the SysAD bus.

5:7

PClock-to-

SysClk-Ratio.

Bit 7 is MSB

0: 2

1: 3

2: 4

3: 5

4: 6

5: 7

6: 8

7: Reserved

8

Endianness

0: Little endian

1: Big endian

The RC64574/575 implement additional write protocols that

double the effective write bandwidth. The write re-issue has a repeat

rate of 2 cycles per write. Pipelined writes have the same 2-cycle per

write repeat rate, but can issue an additional write after WrRdy* de-

asserts.

9:10

Non-block write 00: R4400 compatible

Mode. Bit 10 is 01: Reserved

MSB

10: Pipelined-Write-Mode

11: Write-Reissue-Mode

Table 3 Boot-time Mode Stream (Page 1 of 2)

4 of 28

December 14, 2001

79RC64574™ 79RC64575™

To lock critical sections of code and/or data into the caches for quick

access, a per line “cache locking” feature has been implemented.

Once enabled, a cache is said to be locked when a particular piece of

code or data is loaded into the cache and that cache location will not be

selected later for refill by other data.

Choosing a 32- or 64-bit wide system interface dictates whether a

cache line block transaction requires 4 double word data cycles or 8

single word cycles as well as whether a single data transfer—larger than

4 bytes—must be divided into two smaller transfers.

As shown in Table 3, the bus delay can be defined as 0 to 7

SysClock cycles and is activated and controlled through mode bit

(17:15) settings selected during the reset initialization sequence. The

‘000’ setting provides the same write operations timing protocol as the

RC4640, RC4650, and RC5000 processors.

Power Management

Executing the WAIT instruction enables the processor to enter

Standby mode. The internal clocks will shut down, thus freezing the

pipeline. The PLL, internal timer, and some of the input pins (Int[5:0]*,

NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. Once in

Standby Mode, any interrupt, including the internally generated timer

interrupt, will cause the CPU to exit Standby Mode.

To facilitate discrete interface to SyncDRAM, the RC64574/575 bus

interface is enhanced during write cycles with a programmable delay

that is inserted between the write address and the write data (for both

block and non-block writes).

Board-level testing during Run-Time mode is facilitated through the

full JTAG boundary scan facility. Five pins—TDI, TDO, TMS, TCK,

TRST*—have been incorporated to support the standard JTAG inter-

face.

Thermal Considerations

The RC64574 is packaged in a 128-pin QFP footprint package and

uses a 32-bit external bus, offering the ideal combination of 64-bit

processing power and 32-bit low-cost memory systems. The RC64575

is packaged in a 208-pin QFP footprint package and uses the full 64-bit

external bus. The RC64575 is ideal for applications requiring 64-bit

performance and 64-bit external bandwidth.

The RC64574/575 devices offer a direct migration path for designs

that are based on IDT’s RC4640/RC4650 and RC64474/RC64475

processors², through full pin and socket compatibility. Full 64-bit-family

software and bus protocol compatibility ensures the RC64574/575

processors access to an existing market and development infrastruc-

ture, allowing quicker time to market.

Both devices are guaranteed in a case temperature range of 0° to

+85° C for commercial temperature devices and -40° to +85° C for

Industrial temperature devices. Package type, speed (power) of the

device, and air flow conditions affect the equivalent ambient temperature

conditions that will meet these specifications.

Development Tools

An array of hardware and software tools is available to assist system

designers in the rapid development of RC64574/575 based systems.

This accessibility allows a wide variety of customers to take full advan-

tage of the device’s high-performance features while addressing today’s

aggressive time-to-market demands.

Using the thermal resistance from case to ambient (∅^CA) of the

given package, the equivalent allowable ambient temperature, TA, can

be calculated. The following equation relates ambient and case temper-

atures:

TA = TC - P * ∅CA

Cache Memory

where P is the maximum power consumption at hot temperature,

calculated by using the maximum ICC specification for the device.

Typical values for ∅^CAat various air flow are shown in Table 4. Note

that the RC64574/575 processor implements advanced power manage-

ment, which substantially reduces the typical power dissipation of the

device.

To keep the high-performance pipeline of the RC64574/575 full and

operating efficiently, on-chip instruction and data caches have been

incorporated. Each cache has its own data path and can be accessed in

the same single pipeline clock cycle.

The 32kB two-way set associative instruction cache is virtually

indexed, physically tagged, and word parity protected. Because this

cache is virtually indexed, the virtual-to-physical address translation

occurs in parallel with the cache access, further increasing performance

by allowing both operations to occur simultaneously. The instruction

cache provides a peak instruction bandwidth of 2GB/sec at 250MHz.

∅CA

Airflow (ft/min)

0

200 400 600 800 1000

128 QFP

208 QFP

16

20

10

13

9

7

9

6

8

5

7

10

The 32kB two-way set associative data cache is byte parity

protected and has a fixed 32-byte (eight words) line size. Its tag is

protected with a single parity bit. To allow simultaneous address transla-

tion and data cache access, the D-cache is virtually indexed and physi-

cally tagged. The data cache can provide 8 bytes each clock cycle, for a

peak bandwidth of 2GB/s.

Table 4 Thermal Resistance (∅CA) at Various Airflows

Revision History

July 22, 1999: Original data sheet.

2.

To ensure socket compatibility, refer to Table 8 and Table 9.

5 of 28

December 14, 2001

79RC64574™ 79RC64575™

September 9, 1999: Made several changes in JTAG Interface

section of Table 5. Added information on Pin 63 in Table 5.

October 14, 1999: Revised data in the Power Consumption tables

for RC64574 and RC64575.

November 16, 1999: Added Power Curve graphs, revised data in

System Interface Parameters table, added System Clock Jitter row to

Clock Parameter table.

December 20, 1999: Table 7 “RC64574 128-Pin Package” on page

12, Changed pin #75 function from Vcc to N.C.

March 7, 2000: In Table 1, added “with DSP extensions” in the CPU

row under RC64574 and RC64575 columns and changed “by set” to “by

line” in the Caches row for RC64574 and RC64575 columns. Added

rows in the Data Output and Data Output Hold rows in the System Inter-

face Parameters table. Removed references to 300 MHz, and changed

bandwidth speed to 2GB/second in Cache Memory section. Revised

Power Curves.

March 28, 2000: Replaced existing figure in Mode Configuration

Interface Reset Sequence section with 3 reset figures. Revised values

for 250MHz in System Interface Parameters table. Changed Data Sheet

from Preliminary to final.

April 3, 2000: Deleted signal t_DZfrom Figure 6.

April 25, 2001: In the Absolute Maximum Ratings table, changed

upper voltage limit from 3.8 to 4.0V and removed “Vin should not exceed

Vcc +0.5 volts” from footnote #1. In DC Electrical Characteristics table,

changed maximum value for Vih from 3.3 to 3.8V for all speeds.

May 1, 2001: In the Data Output Hold category of the System Inter-

face Parameters table, changed values in the Min column for all speeds

from 1.0 to 0. In the Electrical Characteristics table, values were added

to the System Clock Jitter row. Added Industrial temperature range of

-40° C to +85° C.

December 14, 2001: In Absolute Maximum Ratings Table, changed

the Industrial low-end temperature for symbol Tc to read -40 degrees

instead of 0 degrees.

6 of 28

December 14, 2001

79RC64574™ 79RC64575™

Pin Description Table

The following is a list of system interface pins available on the RC64574/575. Pin names ending with an asterisk (*) are active when low.

Pin Name

Type

Description

System Interface

ExtRqst*

I

External request

An external agent asserts ExtRqst* to request use of the System interface. The processor grants the request

by asserting Release*.

Release*

O

Release interface

In response to the assertion of ExtRqst* or a CPU read request, the processor asserts Release* and signals

to the requesting device that the system interface is available.

RdRdy*

WrRdy*

ValidIn*

I

Read Ready

The external agent asserts RdRdy* to indicate that it can accept a processor read request.

Write Ready

An external agent asserts WrRdy* when it can now accept a processor write request.

Valid Input

Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command

or data identifier on the SysCmd bus.

ValidOut*

O

Valid Output

Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or

data identifier on the SysCmd bus.

SysAD(63:0)

I/O

System address/data bus

A 64-bit address and data bus for communication between the processor and an external agent. In 64 bit

interface mode, during address phases only, SysAd(35:0) contains invalid address information. The remain-

ing SysAD(63:36) pins are not used. The whole 64-bit SysAD(63:0) may be used during the data transfer

phase. For all double-word accesses (read or write), the low-order 3 bits (SysAD[2:0]) will always be output as

zero during the address phase.

In 32-bit interface mode and in the RC64574, SysAD(63:32) is not used, regardless of Endianness. A 32-bit

address and data communication between processor and external agent is performed via SysAD(31:0).

SysADC(7:0)

I/O

System address/data check bus

An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.

In 32-bit mode and in the RC64574, SysADC(7:4) is not used. The SysADC(3:0) contains check bits for

SysAD(31:0).

SysCmd(8:0)

SysCmdP

I/O

System command/data identifier bus

A 9-bit bus for command and data identifier transmission between the processor and an external agent.

System Command Parity

A single, even-parity bit for the Syscmd bus. This signal is always driven low.

Clock/Control Interface

SysClock

I

SystemClock

The system clock input establishes the processor and bus operating frequency. It is multiplied internally by

2,3,4,5,6,7, or 8 to generate the pipeline clock (PClock).

V_CCP

V_SSP

I

Quiet VCC for PLL

Quiet VCC for the internal phase locked loop.

Quiet V_SSfor PLL

Quiet VSS for the internal phase locked loop.

Table 5 Pin Descriptions (Page 1 of 2)

7 of 28

December 14, 2001

79RC64574™ 79RC64575™

Pin Name

Type

Description

Interrupt Interface

Int*(5:0)

I

Interrupt

Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.

NMI*

Non-maskable interrupt

Non-maskable interrupt, ORed with bit 6 of the interrupt register.

Initialization Interface

V_CCOk

I

V_CCis OK

When asserted, this signal indicates to the processor that the power supply has been above the Vcc minimum

for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the initialization

sequence.

ColdReset*

Reset*

I

Cold reset

This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchro-

nously with SysClock.

Reset

This signal must be asserted for any reset sequence. It can be asserted synchronously or asynchronously for

a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with

SysClock.

ModeClock

ModeIn

O

I

Boot-mode clock

Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six.

Boot-mode data in

Serial boot-mode data input.

JTAG Interface

TDI

I

JTAG Data In

On the rising edge of TCK, serial input data are shifted into either the Instruction register or Data register,

depending on the TAP controller state. An external pull-up resistor is required.

TDO

TCK

O

I

JTAG Data Out

On the falling edge of TCK, the TDO is serial data shifted out from either the instruction or data register. When

no data is shifted out, the TDO is tri-stated (high impedance).

JTAG Clock Input

An input test clock used to shift into or out of the boundary-scan register cells. TCK is independent of the sys-

tem and processor clock with nominal 40-60% duty cycle.

TMS

TRST*

I

JTAG Command Select

The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is

sampled on the rising edge of TCK. An external pull-up resistor is required.

I

JTAG Reset

The TRST* pin is an active-low signal used for asynchronous reset of the debug unit, independent of the pro-

cessor logic. During normal CPU operation, the JTAG controller will be held in the reset mode, asserting this

active low pin.

When asserted low, this pin will also tristate the TDO pin. An external pull-down resistor is required.

JTAG32*

JR_V_cc

I

JTAG 32-bit scan

This pin is used to control length of the scan chain for SysAD (32-bit or 64-bit) for the JTAG mode. When set

to Vss, 32-bit bus mode is selected. In this mode, only SysAD(31:0) are part of the scan chain. When set to

Vcc, 64-bit bus mode is selected. In this mode, SysAD(63:0) are part of the scan chain. This pin has a built-in

pull-down device to guarantee 32-bit scan, if it is left un connected.

JTAG VCC

This pin has an internal pull-down to continuously reset the JTAG controller (if left unconnected) bypassing

the TRst* pin. When supplied with Vcc, the TRst* pin will be the primary control for the JTAG reset.

Table 5 Pin Descriptions (Page 2 of 2)

8 of 28

December 14, 2001

79RC64574™ 79RC64575™

Logic Diagram — RC64574/RC64575

Figure 1 illustrates the direction and functional groupings for the processor signals.

64

SysAD(63:0)

SysADC(7:0)

SysClock

8

9

V

_CCP

SysCmd(8:0)

SysCmdP

V_SSP

TDI

RC64574/

RC64575

Logic

VCCOK

TDO

TMS

TRST*

ColdReset*

Reset*

Symbol

ModeClock

ModeIn

TCK

JTag32*

JR_Vcc

RdRdy*

NMI*

WrRdy*

6

Int*(5:0)

ExtRqst*

Release*

ValidIn*

ValidOut*

Figure 1 Logic Symbol for RC64574/RC64575

9 of 28

December 14, 2001

79RC64574™ 79RC64575™

RC64575 208-pin QFP Package Pin-out

Pin names followed by an asterisk (*) are active when low. For maximum flexibility and compatibility with future designs, N.C. pins should be left

floating.

Function

N.C.

53

Function

JTAG32*

105

Function

N.C.

157

Function

N.C.

1

2

3

4

5

6

7

8

9

N.C.

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

N.C.

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

N.C.

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

N.C.

SysAD59

ColdReset*

SysAD28

V_cc

N.C.

SysCmd2

SysAD36

SysAD4

SysCmd1

V_ss

N.C.

V_ss

N.C.

SysAD60

Reset*

SysAD29

SysAD61

SysAD30

V_cc

N.C.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

SysAD11

V_ss

V_cc

SysAD52

ExtRqst*

V_cc

SysAD35

SysAD3

SysCmd0

SysAD34

V_ss

V_cc

SysCmd8

SysAD42

SysAD10

SysCmd7

V_ss

SysAD21

SysAD53

RdRdy*

Modein

SysAD22

SysAD54

V_cc

V_ss

SysAD62

SysAD31

SysAD63

V_cc

SysAD2

Int5*

V_cc

SysAD41

SysAD9

SysCmd6

SysAD40

V_ss

SysAD33

SysAD1

V_ss

V_ccOK

SysADC3

SysADC7

N.C.

V_ss

V_cc

Release*

SysAD23

SysAD55

NMI*

Int4*

V_cc

SysAD32

SysAD0

Int3*

TDI

SysAD8

SysCmd5

SysADC4

SysADC0

V_ss

TRst*

V_cc

TCK

V_ss

TMS

V_cc

SysADC2

SysADC6

SysAD24

V_cc

TDO

Int2*

V_ccP

V_cc

SysAD16

SysAD48

Int1*

V_ssP

SysCmd4

SysAD39

SysAD7

SysClock

V_cc

V_ss

SysAD56

V_ss

Table 6 RC64575 208-pin QFP Package Pin-Out (Page 1 of 2)

10 of 28

December 14, 2001

79RC64574™ 79RC64575™

34

Function

86

Function

V_cc

138

Function

SysAD25

190

Function

SysADC5

SysCmd3

V_ss

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

87

SysAD17

SysAD49

Int0*

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

SysAD57

V_cc

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

SysADC1

V_cc

88

SysAD38

SysAD6

ModeClock

WrRdy*

SysAD37

SysAD5

V_ss

89

V_ss

90

SysAD18

V_ss

N.C

SysAD47

SysAD15

SysAD46

V_cc

91

SysAD26

SysAD58

N.C.

92

V_cc

93

SysAD50

ValidIn*

SysAD19

SysAD51

V_ss

94

V_cc

V_ss

95

V_ss

SysAD14

SysAD45

SysAD13

SysAD44

V_ss

V_cc

96

SysAD27

N.C.

97

N.C.

98

V_cc

JR_V_cc

N.C.

99

ValidOut*

SysAD20

N.C.

100

101

102

103

104

N.C.

V_cc

N.C.

SysAD12

SysCmdP

SysAD43

N.C.

Table 6 RC64575 208-pin QFP Package Pin-Out (Page 2 of 2)

11 of 28

December 14, 2001

79RC64574™ 79RC64575™

RC64574 128-pin Package Pin-out

N.C. pins should be left floating for maximum flexibility as well as for compatibility with future designs. An asterisk (*) identifies a pin that is active

when low.

Function

JTAG32*

33

Function

97

Function

1

2

3

4

5

6

7

8

9

V_cc

V_ss

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

V_cc

V_ss

SysCmd2

V_cc

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

SysAD28

ColdReset*

SysAD27

V_ss

98

SysAD13

SysAD14

V_ss

99

SysAD19

ValidIn*

V_cc

V_ss

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

SysAD5

WrRdy*

ModeClock

SysAD6

V_cc

V_ss

SysAD15

V_ss

JR_V_cc

SysAD26

N.C.

SysAD18

Int0*

V_cc

SysAD17

V_cc

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

V_ss

SysADC1

V_ss

SysCmd3

SysAD7

SysCmd4

V_cc

N.C.

V_ss

V_cc

SysAD25

V_ss

Int1*

SysClock

V_ssP

SysAD16

Int2*

V_cc

V_ss

V_ccP

SysAD24

SysADC2

V_ss

V_cc

SysADC0

SysCmd5

SysAD8

V_cc

TDO

V_ss

TMS

Int3*

TCK

V_cc

SysAD0

Int4*

TRst*

TDI

NMI*

V_ss

SysAD23

Release*

V_ss

V_cc

SysCmd6

SysAD9

V_cc

V_ss

SysADC3

V_ccOK

V_ss

SysAD1

Int5*

V_cc

V_ss

SysAD22

Modein

RdRdy*

SysAD21

V_ss

SysAD2

V_cc

SysCmd7

SysAD10

SysCmd8

V_cc

Vcc

SysAD31

V_ss

SysCmd0

SysAD3

V_cc

V_ss

SysAD30

SysAD29

Reset*

V_ss

V_cc

SysAD11

SysCmdP

SysAD12

ExtRqst*

SysAD20

ValidOut*

V_ss

SysCmd1

SysAD4

Table 7 RC64574 128-Pin Package

12 of 28

December 14, 2001

79RC64574™ 79RC64575™

RC64574 Socket Compatibility to RC64474 & RC4640

The RC64574/575 is 100% pin compatible with the RC64474/475 with the supply voltage being the only difference. RC64474/475 requires a 3.3V

supply, while RC64574/575 requires a 2.5V supply.

To ensure socket compatibility between the RC64574/RC64474 and the RC4640 devices, several pin changes are required, as shown in the tables

below. Note: The RC64574/575 are 2.5V parts and as such all Vcc must be at the correct voltage for a given part.

RC64574/

RC64474

Compatible to

RV4640?

RC4640

N.C

Comments

1

JTAG32*

Yes

Pin has an internal pull-down, to enable 32-bit scan.

Can also be left a N.C.

48

V_ss

TDO

Yes

Can be driven with V_ss, if JTAG is not needed. Is tristated when

TRst* is low.

49

50

51

52

71

V_ss

N.C.

TMS

TCK

Yes

Can be driven with V_ssif JTAG is not needed.

TRst*

TDI

JR_V_cc

Can be left N.C. in RC64574, if JTAG is not need. If JTAG is

needed, it must be driven to V_cc.

Table 8 RC64574 Socket Compatibility to RC64474 and R4640

RC64575 Socket Compatibility to RC64475 & RC4650

RC64575

32-bit

RC64475

32-bit

RC64575

64-bit

RC64475

64-bit

RV4650

32-bit

RV4650

64-bit

Compatible to

RV4650?

Comments

53

N.C.

JTAG32*

No Connect

JTAG32*

Yes

In 32-bit, this pin can be left uncon-

nected because of internal pull-down.

In 64-bit, this assumes that JTAG will

not be used. If using JTAG, this pin

must be at V_cc.

150

N.C.

JR_V_cc

No Connect

JR_V_cc

Ye s

In RC64475, can be left a N.C, if

JTAG is not need. If JTAG is needed,

it must be driven to V_cc.

180

181

182

183

184

N.C.

TDI

No Connect

TDO

TRsT*

TCK

Yes