IDT79RV4650-150DPI8 [IDT]
RISC Microprocessor, 64-Bit, 150MHz, PQFP208, PLASTIC, QFP-208;
| 型号： | IDT79RV4650-150DPI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | RISC Microprocessor, 64-Bit, 150MHz, PQFP208, PLASTIC, QFP-208 时钟 外围集成电路 |
| 文件： | 总25页 (文件大小：568K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT79RC4650™
Low-Cost 64-bit
RISController
w/DSP Capability
◆
Large, efficient on-chip caches
ꢀꢁꢂꢃꢄꢅꢁꢆ
◆
– Separate 8kB Instruction and 8kB Data caches
– Over 3200MB/sec bandwidth from internal caches
– 2-set associative
– Write-back and write-through support
– Cache locking to facilitate deterministic response
High-performance embedded 64-bit microprocessor
– 64-bit integer operations
– 64-bit registers
– 100MHz, 133MHz, 150 MHz, 180MHz, 200MHz and 267MHz
operation frequencies
High-performance DSP capability
– 133.5 Million Integer Multiply-Accumulate Operations/sec @
267 MHz
High-performance microprocessor
– 133.5 M Mul-Add/second at 267MHz
– 89 MFL0P/s at 250MHz
◆
Bus compatible with RC4000 family
◆
◆
– System interface provides bandwidth up to 1000 MB/S
– Direct interface to 32-bit wide or 64-bit wide systems
– Synchronized to external reference clock for multi-master
operation
– Socket compatible with IDT RC64475 and RC64575
◆
◆
Improved real-time support
– Fast interrupt decode
Optional cache locking
– >640,000 dhrystone (2.1)/sec capability at 267MHz
(352 dhrystone MIPS)
High level of integration
◆
Note:“R” refers to 5V parts; “RV” refers to 3.3V parts; “RC”
refers to both
– 64-bit, 267 MHz integer CPU
– 8KB instruction cache; 8KB data cache
– Integer multiply unit with 133.5M Mul-Add/sec
◆
◆
Low-power operation
– Active power management powers-down inactive units
– Standby mode
Upwardly software compatible with IDT RISController
Family
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢈꢋ
352 M IPS 64-bit C PU
System C ontrol C oprocessor
89M FL O PS Single-Precision FPA
FP register file
Address Translation/
Cache Attribute Control
64-bit register file
64-bit adder
Load aligner
Store Aligner
Logic Unit
Pack/Unpack
Exception M anagem ent
Functions
FP Add/Sub/C vt/
Div/Sqrt
H igh-Perform ance
Integer M ultiply
FP M ultiply
Control Bus
Data Bus
Instruction Bus
Instruction Cache
Set A
(Lockable)
Data Cache
Set A
(Lockable)
Instruction Cache
Set B
32-/64-bit
Synchronized
System Interface
D ata C ache
Set
B
The IDT logo is a registered trademark and ORION, RC4600, RC4650, RV4650, RC4700, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
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DSC 3149/3
1999 Integrated Device Technology, Inc.
IDT79RC4650™
The RC4650 provides complete upward application-software
compatibility with the IDT79RC32300™ and IDT79RC64xxx™ families of
microprocessors. An array of development tools facilitates the rapid
development of RC4650-based systems, enabling a wide variety of
customers to take advantage of the high-performance capabilities of the
processor while maintaining short time to market goals.
ꢇꢁꢆꢈꢅꢉꢊꢃꢉꢋꢌ
The IDT79RC4650 is a low-cost member of the IDT Microprocessor
family, targeted to a variety of performance-hungry embedded applica-
tions. The RC4650 continues the IDT tradition of high-performance
through high-speed pipelines, high-bandwidth caches and bus interface,
64-bit architecture, and careful attention to efficient control. The RC4650
reduces the cost of this performance relative to the RC4700 by removing
functional units that are frequently unneeded for many embedded appli-
cations, such as double-precision floating point arithmetic and a TLB.
The 64-bit computing capability of the RC4650 enables a wide
variety of capabilities previously limited by the lower bandwidth and bit-
manipulation rates inherent in 32-bit architectures. For example, the
RC4650 can perform loads and stores from cached memory at the rate
of 8-bytes every clock cycle, doubling the bandwidth of an equivalent 32-
bit processor. This capability, coupled with the high clock rate for the
RC4650 pipeline, enables new levels of performance to be obtained
from embedded systems.
The RC4650 adds features relative to the RC4700, reflective of its
target applications. These features enable system cost reduction (e.g.,
optional 32-bit system interface) as well as higher performance for
certain types of systems (e.g., cache locking, improved real-time
support, integer DSP capability).
This data sheet provides an overview of the features and architecture
of the RC4650 CPU. A more detailed description of the processor is
available in the IDT79RC4650 Processor Hardware User’s Manual,
available from IDT. Further information on development support, appli-
cations notes, and complementary products are also available from your
local IDT sales representative.
The RC4650 supports a wide variety of embedded processor-based
applications, such as consumer game systems, multi-media functions,
internetworking equipment, switching equipment, and printing systems.
Upwardly software-compatible with the RC3000 family, and bus- and
upwardly software-compatible with the IDT RC4000/RC5000 family, the
RC4650 will serve in many of the same applications, but, in addition
supports other applications such as those requiring integer DSP func-
tions.
ꢍꢂꢅꢎꢏꢂꢅꢁꢐꢑꢒꢁꢅꢒꢉꢁꢏ
The RC4650 family brings a high-level of integration designed for
high-performance computing. The key elements of the RC4650 are
briefly described below. A more detailed description of each of these
subsystems is available in the User’s Manual.
The RC64475 and RC64575 processors offer a direct migration path
for designs based on IDT’s RC4650 processors, through full pin and
socket compatibility.
The RC4650 brings 64-bit performance levels to lower cost systems.
High performance is preserved by retaining large on-chip caches that
are two-way set associative, a streamlined high-speed pipeline, high-
bandwidth, 64-bit execution, and facilities such as early restart for data
cache misses. These techniques combine to allow the system designer
3.2GB/sec aggregate bandwidth, 1000 MB/sec bus bandwidth, 352
Dhrystone MIPS, 89 MFlops, and 133.5 M Multiply-add/second.
The RC4650 uses a 5-stage pipeline similar to the IDT79RC3000
and the IDT79RC4700. The simplicity of this pipeline allows the RC4650
to be lower cost and lower power than super-scalar or super-pipelined
processors. Unlike superscalar processors, applications that have large
data dependencies or that require a great deal of load/stores can still
achieve performance close to the peak performance of the processor.
General Purpose Registers
Multiply/Divide Registers
63
0
0
63
0
HI (Accumulate HI)
63
r1
r2
•
0
LO (Accumulate LO)
•
•
Program Counter
•
63
0
32 310
PC
r29
Figure 1 CPU Registers
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IDT79RC4650™
The RC4650 implements the MIPS-III Instruction Set Architecture
and is upwardly compatible with applications that run on the earlier
generation parts. The RC4650 includes the same additions to the
instruction set found in the RC4700 family of microprocessors, targeted
at improving performance and capability while maintaining binary
compatibility with earlier RC3000 processors.
MULT/U, MAD/U 16 bit
32 bit
3
4
3
4
6
2
3
2
3
5
0
0
1
2
0
MUL
16 bit
32 bit
any
The extensions result in better code density, greater multi-processing
support, improved performance for commonly used code sequences in
operating system kernels, and faster execution of floating-point intensive
applications. All resource dependencies are made transparent to the
programmer, insuring transportability among implementations of the
MIPS instruction set architecture. In addition, MIPS-III specifies new
instructions defined to take advantage of the 64-bit architecture of the
processor.
DMULT,
DMULTU
DIV, DIVU
any
any
36
68
36
68
0
0
DDIV, DDIVU
Table 1 RC4650 Integer Multiply Operation
The MIPS-III architecture defines that the results of a multiply or
divide operation are placed in the HI and LO registers. The values can
then be transferred to the general purpose register file using the MFHI/
MFLO instructions.
Finally, the RC4650 also implements additional instructions, which
are considered extensions to the MIPS-III architecture. These instruc-
tions improve the multiply and multiply-add throughput of the CPU,
making it well suited to a wide variety of imaging and DSP applications.
These extensions, which use opcodes allocated by MIPS Technologies
for this purpose, are supported by a wide variety of development tools.
The RC4650 adds a new multiply instruction, “MUL”, which can
specify that the multiply results bypass the “Lo” register and are placed
immediately in the primary register file. By avoiding the explicit “Move-
from-Lo” instruction required when using “Lo”, throughput of multiply-
intensive operations is increased.
The MIPS integer unit implements a load/store architecture with
single cycle ALU operations (logical, shift, add, sub) and autonomous
multiply/divide unit. The 64-bit register resources include: 32 general-
purpose orthogonal integer registers, the HI/LO result registers for the
integer multiply/divide unit, and the program counter. In addition, the on-
chip floating-point co-processor adds 32 floating-point registers, and a
floating-point control/status register.
An additional enhancement offered by the RC4650 is an atomic
“multiply-add” operation, MAD, used to perform multiply-accumulate
operations. This instruction multiplies two numbers and adds the product
to the current contents of the HI and LO registers. This operation is used
in numerous DSP algorithms, and allows the RC4650 to cost reduce
systems requiring a mix of DSP and control functions.
Finally, aggressive implementation techniques feature low latency for
these operations along with pipelining to allow new operations to be
issued before a previous one has fully completed. Table 1 also shows
the repeat rate (peak issue rate), latency, and number of processor stalls
required for the various operations. The RC4650 performs automatic
operand size detection to determine the size of the operand, and imple-
ments hardware interlocks to prevent overrun, allowing this high-perfor-
mance to be achieved with simple programming.
The RC4650 has thirty-two general-purpose 64-bit registers. These
registers are used for scalar integer operations and address calculation.
The register file consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline. Figure 1 illus-
trates the RC4650 Register File.
The RC4650 ALU consists of the integer adder and logic unit. The
adder performs address calculations in addition to arithmetic operations,
and the logic unit performs all logical and shift operations. Each of these
units is highly optimized and can perform an operation in a single pipe-
line cycle.
The RC4650 incorporates an entire single-precision floating-point co-
processor on chip, including a floating-point register file and execution
units. The floating-point co-processor forms a “seamless” interface with
the integer unit, decoding and executing instructions in parallel with the
integer unit.
The RC4650 uses a dedicated integer multiply/divide unit, optimized
for high-speed multiply and multiply-accumulate operation. Table 1
shows the performance, expressed in terms of pipeline clocks, achieved
by the RC4650 integer multiply unit.
The RC4650’s floating-point unit directly implements single-precision
floating-point operations. This enables the RC4650 to perform functions
such as graphics rendering, without requiring extensive die are or power
consumption.
The RC4650 does not directly implement the double-precision opera-
tions found in the RC64475. However, to maintain software compatibility,
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IDT79RC4650™
the RC4650 will signal a trap when a double-precision operation is initi-
ated, allowing the requested function to be emulated in software. Alter-
natively, the system architect could use a software library emulation of
double-precision functions, selected at compile time, to eliminate the
overhead associated with trap and emulation.
The floating-point register file is made up of thirty-two 32-bit regis-
ters. These registers are used as source or target registers for the
single-precision operations. References to these registers as 64-bit
registers (as supported in the RC64475) will cause a trap to be
signalled.
The floating-point control register space contains two registers; one
for determining configuration and revision information for the copro-
cessor and one for control and status information. These are primarily
involved with diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
The RC4650 floating-point execution units perform single precision
arithmetic, as specified in the IEEE Standard 754. The execution unit is
broken into a separate multiply unit and a combined add/convert/divide/
square root unit. Overlap of multiplies and add/subtract is supported.
The multiplier is partially pipelined, allowing a new multiply to begin
every 6 cycles.
As in the IDT79RC64475, the RC4650 maintains fully precise
floating-point exceptions while allowing both overlapped and pipelined
operations. Precise exceptions are extremely important in mission-crit-
ical environments, such as ADA, and highly desirable for debugging in
any environment.
The system control co-processor in the MIPS architecture is respon-
sible for the virtual to physical address translation and cache protocols,
the exception control system, and the diagnostics capability of the
processor. In the MIPS architecture, the system control co-processor
(and thus the kernel software) is implementation dependent.
The floating-point unit’s operation set includes floating-point add,
subtract, multiply, divide, square root, conversion between fixed-point
and floating-point format, conversion among floating-point formats, and
floating-point compare.These operations comply with IEEE Standard
754. Double precision operations are not directly supported; attempts to
execute double-precision floating point operations, or refer directly to
double-precision registers, result in the RC4650 signalling a “trap” to the
CPU, enabling emulation of the requested function. Table 2 gives the
latencies of some of the floating-point instructions in internal processor
cycles.
In the RC4650, significant changes in CP0—relative to the
RC4700—have been implemented. These changes are designed to
simplify memory management, facilitate debug, and speed real-time
processing.
The RC4650 incorporates all system control co-processor (CP0)
registers on-chip. These registers provide the path through which the
virtual memory system’s address translation is controlled, exceptions
are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RC4650
includes registers to implement a real-time cycle counting facility, which
aids in cache diagnostic testing, assists in data error detection, and
facilitates software debug. Alternatively, this timer can be used as the
operating system reference timer, and can signal a periodic interrupt.
Table 3 shows the CP0 registers of the RC4650.
ADD
SUB
MUL
DIV
4
4
8
32
31
3
SQRT
CMP
FIX
0
1
2
3
IBase
IBound
DBase
DBound
—
Instruction address space base
Instruction address space bound
Data address space base
Data address space bound
Not used
4
FLOAT
ABS
6
1
4-7, 10, 20-
25, 29, 31
MOV
NEG
LWC1
SWC1
1
1
8
BadVAddr Virtual address on address exceptions
Count Counts every other cycle
Compare Generate interrupt when Count = Compare
2
9
1
11
12
13
Table 2 Floating-Point Operation
Status
Cause
Miscellaneous control/status
Exception/Interrupt information
Table 3 RC4650 CPO Registers (Page 1 of 2)
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IDT79RC4650™
Kernel mode addresses do not use the base-bounds registers, but
rather undergo a fixed virtual-to-physical address translation.
14
EPC
Exception PC
0xFFFFFFFF
15
16
17
PRId
Config
CAlg
Processor ID
Kernel virtual address space
(kseg2)
Cache and system attributes
Unmapped, 1.0 GB
0xC0000000
Cache attributes for the eight 512MB regions of
the virtual address space
0xBFFFFFFF
18
19
26
27
28
30
IWatch
DWatch
ECC
Instruction breakpoint virtual address
Data breakpoint virtual address
Used in cache diagnostics
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0xA0000000
CacheErr Cache diagnostics
TagLo Cache index
0x9FFFFFFF
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
ErrorEPC CacheError exception PC
Table 3 RC4650 CPO Registers (Page 2 of 2)
0x80000000
0x7FFFFFF
The RC4650 supports two modes of operation: user mode and
kernel mode. Kernel mode operation is typically used for exception
handling and operating system kernel functions, including CP0 manage-
ment and access to IO devices. In kernel mode, software has access to
the entire address space and all of the co-processor 0 registers, and can
select whether to enable co-processor 1 accesses. The processor
enters kernel mode at reset, and whenever an exception is recognized.
User virtual address space
(useg)
Mapped, 2.0GB
0x00000000
User mode is typically used for applications programs. User mode
accesses are limited to a subset of the virtual address space and can be
inhibited from accessing CP0 functions
Figure 2 Kernel/User Mode Virtual Addressing (32-bit mode)
To facilitate software debug, the RC4650 adds a pair of “watch” regis-
ters to CP0. When enabled, these registers will cause the CPU to take
an exception when a “watched” address is appropriately accessed.
The 4GB virtual address space of the RC4650 is shown in Figure 2.
The 4 GB address space is divided into addresses accessible in either
kernel or user mode (kuseg), and addresses only accessible in kernel
mode (kseg2:0).
The RC4650 also adds the capability to speed interrupt exception
decoding. Unlike the RC4700, which utilizes a single common exception
vector for all exception types (including interrupts), the RC4650 allows
kernel software to enable a separate interrupt exception vector. When
enabled, this vector location speeds interrupt processing by allowing
software to avoid decoding interrupts from general purpose exceptions.
The RC4650 supports the use of multiple user tasks sharing
common virtual addresses, but mapped to separate physical addresses.
This facility is implemented via the “base-bounds” registers contained in
CP0.
When a user virtual address is asserted (load, store, or instruction
fetch), the RC4650 compares the virtual address with the contents of the
appropriate “bounds” register (instruction or data). If the virtual address
is “in bounds”, the value of the corresponding “base” register is added to
the virtual address to form the physical address for that reference. If the
address is not within bounds, an exception is signalled.
To keep the RC4650’s high-performance pipeline full and operating
efficiently, the RC4650 incorporates on-chip instruction and data caches
that can each be accessed in a single processor cycle. Each cache has
its own 64-bit data path and can be accessed in parallel. The cache
subsystem provides the integer and floating-point units with an aggre-
gate bandwidth of over 3200 MB per second at a pipeline clock
frequency of 267MHz. The cache subsystem is similar in construction to
that found in the RC4700, although some changes have been imple-
mented. Table 4 is an overview of the caches found on the RC4650.
This facility enables multiple user processes in a single physical
memory without the use of a TLB. This type of operation is further
supported by a number of development tools for the RC4650, including
real-time operating systems and “position independent code.”
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IDT79RC4650™
The data cache is protected with byte parity and its tag is protected
with a single parity bit. It is virtually indexed and physically tagged to
allow simultaneous address translation and data cache access
The RC4650 incorporates a two-way set associative on-chip instruc-
tion cache. This virtually indexed, physically tagged cache is 8KB in size
and is parity protected.
The normal write policy is writeback, which means that a store to a
cache line does not immediately cause memory to be updated. This
increases system performance by reducing bus traffic and eliminating
the bottleneck of waiting for each store operation to finish before issuing
a subsequent memory operation. Software can however select write-
through for certain address ranges, using the CAlg register in CP0.
Cache protocols supported for the data cache are:
Because the cache is virtually indexed, the virtual-to-physical
address translation occurs in parallel with the cache access, thus further
increasing performance by allowing these two operations to occur simul-
taneously. The tag holds a 20-bit physical address and valid bit, and is
parity protected.
The instruction cache is 64-bits wide, and can be refilled or accessed
in a single processor cycle. Instruction fetches require only 32 bits per
cycle, for a peak instruction bandwidth of 1068MB/sec at 267MHz.
Sequential accesses take advantage of the 64-bit fetch to reduce power
dissipation, and cache miss refill, can write 64 bits-per-cycle to minimize
the cache miss penalty. The line size is eight instructions (32 bytes) to
maximize performance.
Uncached. Addresses in a memory area indicated as uncached will
not be read from the cache. Stores to such addresses will be written
directly to main memory, without changing cache contents.
◆
Writeback. Loads and instruction fetches will first search the
cache, reading main memory only if the desired data is not
cache resident. On data store operations, the cache is first
searched to see if the target address is cache resident. If it is
resident, the cache contents will be updated, and the cache line
marked for later writeback. If the cache lookup misses, the
target line is first brought into the cache before the cache is
updated.
In addition, the contents of one set of the instruction cache (set “A”)
can be “locked” by setting a bit in a CP0 register. Locking the set
prevents its contents from being overwritten by a subsequent cache
miss; refill occurs then only into “set B”.
◆
This operation effectively “locks” time-critical code into one 4kB set,
while allowing the other set to service other instruction streams in a
normal fashion. Thus, the benefits of cached performance are achieved,
while deterministic real-time response is preserved.
Write-through with write allocate. Loads and instruction
fetches will first search the cache, reading main memory only if
the desired data is not cache resident. On data store operations,
the cache is first searched to see if the target address is cache
resident. If it is resident, the cache contents will be updated and
main memory will also be written; the state of the “writeback” bit
of the cache line will be unchanged. If the cache lookup misses,
the target line is first brought into the cache before the cache is
updated.
For fast, single cycle data access, the RC4650 includes an 8KB on-
chip data cache that is two-way set associative with a fixed 32-byte
(eight words) line size. Table 4 lists the RC4650 cache attributes.
◆
Write-through without write-allocate. Loads and instruction
fetches will first search the cache, reading main memory only if
the desired data is not cache resident. On data store operations,
the cache is first searched to see if the target address is cache
resident. If it is resident, the cache contents will be updated, and
the cache line marked for later writeback. If the cache lookup
misses, then only main memory is written.
Size
8KB
8KB
Organization
Line size
Index
2-way set associative 2-way set associative
32B
32B
vAddr11..0
pAddr31..12
n.a.
vAddr11..0
Associated with the Data Cache is the store buffer. When the
RC4650 executes a Store instruction, this single-entry buffer gets
written with the store data while the tag comparison is performed. If the
tag matches, then the data is written into the Data Cache in the next
cycle that the Data Cache is not accessed (the next non-load cycle).
The store buffer allows the RC4650 to execute a store every processor
cycle and to perform back-to-back stores without penalty.
Tag
pAddr31..12
writeback /writethru
Write policy
Line transfer order
read sub-block order read sub-block order
write sequential
entire line
write sequential
first word
Miss restart after
transfer of
Parity
per-word
set A
per-byte
set A
Writes to external memory, whether cache miss writebacks or stores
to uncached or write-through addresses, use the on-chip write buffer.
The write buffer holds up to four address and data pairs. The entire
buffer is used for a data cache writeback and allows the processor to
proceed in parallel with memory update.
Cache locking
Table 4 RC4650 Cache Attributes
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IDT79RC4650™
The 64-bit System Address Data (SysAD) bus is used to transfer
addresses and data between the RC4650 and the rest of the system. It
is protected with an 8-bit parity check bus, SysADC. When initialized for
32-bit operation, SysAD can be viewed as a 32-bit multiplexed bus, with
4 parity check bits.
The RC4650 supports a 64-bit system interface that is bus compat-
ible with the RC4700 system interface. In addition, the RC4650 supports
a 32-bit system interface mode, allowing the CPU to interface directly
with a lower cost memory system.
The RC64475 supports a 64-bit system interface that is bus compat-
ible with the RC4650 system interface.
The system interface is configurable to allow easier interfacing to
memory and I/O systems of varying frequencies. The bus frequency and
reference timing of the RC4650 are taken from the input clock. The rate
at which the CPU transmits data to the system interface is program-
mable via boot time mode control bits. The rate at which the processor
receives data is fully controlled by the external device. Therefore, either
a low cost interface requiring no read or write buffering or a faster, high
performance interface can be designed to communicate with the
RC4650. Again, the system designer has the flexibility to make these
price/performance trade-offs.
The interface consists of a 64-bit Address/Data bus with 8 check bits
and a 9-bit command bus protected with parity. In addition, there are 8
handshake signals and 6 interrupt inputs. The interface has a simple
timing specification and is capable of transferring data between the
processor and memory at a peak rate of 1000MB/sec.
Figure 3 shows a typical system using the RC4650. In this example
two banks of DRAMs are used to supply and accept data with a
DDxxDD data pattern.
The RC4650 clocking interface allows the CPU to be easily mated
with external reference clocks. The CPU input clock is the bus reference
clock, and can be between 50 and 125MHz (somewhat dependent on
maximum pipeline speed for the CPU).
The RC4650 interface has a 9-bit System Command (SysCmd) bus.
The command bus indicates whether the SysAD bus carries an address
or data. If the SysAD carries an address, then the SysCmd bus also indi-
cates what type of transaction is to take place (for example, a read or
write). If the SysAD carries data, then the SysCmd bus also gives infor-
mation about the data (for example, this is the last data word trans-
mitted, or the cache state of this data line is clean exclusive). The
SysCmd bus is bidirectional to support both processor requests and
external requests to the RC4650. Processor requests are initiated by the
RC4650 and responded to by an external device. External requests are
issued by an external device and require the RC4650 to respond.
An on-chip phase-locked-loop generates the pipeline clock from the
system interface clock by multiplying it up an amount selected at system
reset. Supported multipliers are values 2 through 8 inclusive, allowing
systems to implement pipeline clocks at significantly higher frequency
than the system interface clock.
Address
Control
DRAM
(80ns)
Boot
ROM
SCSI
ENET
32 or 64
Memory I/O
Controller
32 or 64
RC4650
9
2
11
Figure 3 Typical RC4650 System Architecture
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IDT79RC4650™
be outstanding at a time and that the request must be serviced by an
external device before the RC4650 issues another request. The RC4650
can issue read and write requests to an external device, and an external
device can issue read and write requests to the RC4650.
The RC4650 supports single datum (one to eight byte) and 8-word
block transfers on the SysAD bus. In the case of a single-datum transfer,
the low-order 3 address bits gives the byte address of the transfer, and
the SysCmd bus indicates the number of bytes being transferred. The
choice of 32- or 64-bit wide system interface dictates whether a cache
line block transaction requires 4 double word data cycles or 8 single
word cycles, and whether a single datum transfer larger than 4 bytes
needs to be broken into two smaller transfers.
The RC4650 asserts ValidOut* and simultaneously drives the
address and read command on the SysAD and SysCmd buses. If the
system interface has RdRdy* or Read transactions asserted, then the
processor tristates its drivers and releases the system interface to slave
state by asserting Release*. The external device can then begin sending
the data to the RC4650.
There are six handshake signals on the system interface. Two of
these signals, RdRdy* and WrRdy*, are used by an external device to
indicate to the RC4650 whether it can accept a new read or write trans-
action. The RC4650 samples these signals before deasserting the
address on read and write requests.
Figure 4 shows a processor block read request and the external
agent read response. The read latency is 4 cycles (ValidOut* to
ValidIn*), and the response data pattern is DDxxDD. Figure 5 shows a
processor block write.
ExtRqst* and Release* are used to transfer control of the SysAD and
SysCmd buses between the processor and an external device. When an
external device needs to control the interface, it asserts ExtRqst*. The
RC4650 responds by asserting Release* to release the system interface
to slave state.
The RC4700 and the RC4650 implement additional write protocols
designed to improve performance. This implementation doubles the
effective write bandwidth. The write re-issue has a high repeat rate of 2
cycles per write. A write issues if WrRdy is asserted 2 cycles earlier and
is still asserted at the issue cycle. If it is not still asserted, the last write
re-issues again. Pipelined writes have the same 2-cycle per write repeat
rate, but can issue one more write after WrRdy de-asserts. They still
follow the issue rule as R4x00 mode for other writes.
ValidOut* and ValidIn* are used by the RC4650 and the external
device respectively to indicate that there is a valid command or data on
the SysAD and SysCmd buses. The RC4650 asserts ValidOut* when it
is driving these buses with a valid command or data, and the external
device drives ValidIn* when it has control of the buses and is driving a
valid command or data.
The RC4650 responds to requests issued by an external device. The
requests can take several forms. An external device may need to supply
data in response to an RC4650 read request or it may need to gain
control over the system interface bus to access other resources which
may be on that bus.
The RC4650 requires a non-overlapping system interface, compat-
ible with the RC4700. This means that only one processor request may
MasterClock
Addr
Read
Data0
CData
Data1
CData
Data3
CEOD
SysAD
Data2
CData
SysCmd
ValidOut
ValidIn
RdRdy
WrRdy
Release
Figure 4 RC4650 Block Read Request (64-bit interface option)
8 of 25
March 28, 2000
IDT79RC4650™
The following is a list of the supported external requests:
◆
Read Response
255..15
14..13
Must be zero
◆
Null
Output driver strength:
10 → 100% strength (fastest)
11 → 83% strength
00 → 67% strength
01 → 50% strength (slowest)
Fundamental operational modes for the processor are initialized by
the boot-time mode control interface. The boot-time mode control inter-
face is a serial interface operating at a very low frequency (MasterClock
divided by 256). The low-frequency operation allows the initialization
information to be kept in a low-cost EPROM; alternatively the twenty-or-
so bits could be generated by the system interface ASIC or a simple
PAL.
11
12
Disable the timer interrupt on Int[5]
0 → 64-bit system interface
1 → 32-bit system interface
10..9
00 → RC4000 compatible
01 → reserved
10 → pipelined writes
11 → write re-issue
To initialize all fundamental, operational modes, immediately after the
VCCOK signal is asserted, the processor reads a serial bit stream of 256
bits. After initialization is complete, the processor continues to drive the
serial clock output, but no further initialization bits are read.
8
0 → Little endian
1 → Big endian
7..5
Clock multiplier:
0 → 2
The boot-time serial mode stream is defined in Table 5. Bit 0 is the bit
presented to the processor when VCCOK is asserted; bit 255 is the last.
1 → 3
2 → 4
3 → 5
4 → 6
5 → 7
6 → 8
7 reserved
CP0 is also used to control the power management for the RC4650.
This is the standby mode and it can be used to reduce the power
consumption of the internal core of the CPU. The standby mode is
entered by executing the WAIT instruction with the SysAD bus idle and
is exited by any interrupt.
4..1
Writeback data rate:
64-bit
32-bit
0 → ∆
0 → Ω
1 → DDx
1 → WWx
2 → DDxx
3 → DxDx
4 → DDxxx
5 → DDxxxx
6 → DxxDxx
7 → DDxxxxxx
8 → DxxxDxxx
9-15 reserved
2 → WWxx
3 → WxWx
4 → WWxxx
5 → WWxxxx
6 → WxxWxx
7 → WWxxxxxx
8 → WxxxWxxx
9-15 reserved
The RC4650 provides a means to reduce the amount of power
consumed by the internal core when the CPU would otherwise not be
performing any useful operations. This is known as “Standby Mode.”
Executing the WAIT instruction enables interrupts and enters
Standby mode. When the WAIT instruction finishes the W pipe-stage, if
the SysAd bus is currently idle, the internal clocks will shut down, thus
freezing the pipeline. The PLL, internal timer, and some of the input pins
(Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. If
the conditions are not correct when the WAIT instruction finishes the W
pipe-stage (i.e. the SysAd bus is not idle), the WAIT is treated as a NOP.
0
Reserved (must be zero)
Table 5 Boot-time mode stream
ꢓꢔꢁꢅꢕꢂꢖꢐꢗꢋꢌꢆꢉꢎꢁꢅꢂꢃꢉꢋꢌꢆ
Once the CPU is in Standby Mode, any interrupt, including the inter-
nally generated timer interrupt, will cause the CPU to exit Standby
Mode.
The RC4650 utilizes special packaging techniques to improve the
thermal properties of high-speed processors. The RC4650 is packaged
using cavity down packaging in a 208-pin QFP (DP). The QFP package
allows for an efficient thermal transfer between the die and the case.
The R4650 and the RV4650 are guaranteed in a case temperature
range of 0°C to +85°C for commercial temperature parts and in a case
temperature range of -40°C to +85°C for industrial temperature parts.
The type of package, speed (power) of the device, and airflow conditions
affect the equivalent ambient temperature conditions that will meet this
specification. The equivalent allowable ambient temperature, TA, can be
9 of 25
March 28, 2000
IDT79RC4650™
calculated using the thermal resistance from case to ambient ( CA) of
the given package. The following equation relates ambient and case
temperatures:
– Added 200 MHz operation frequency.
TA = TC - P * CA
Features:
where P is the maximum power consumption at hot temperature,
calculated by using the maximum ICC specification for the device.
Typical values for CA at various airflows are shown in Table 6.
– Changed dhrystone/sec reference
Power Consumption (RV4650):
– Upgraded System Condition Icc active parameters
Clock Parameters:
– Changed MasterClock period to 200MHz
208 QFP (DP)
21 13
10
9
8
7
Packaging:
Table 6 Thermal Resistance ( CA) at Various Airflows
– MQUAD packaging changed to PQUAD (DP)
Note that the RC4650 implements advanced power management to
substantially reduce the average power dissipation of the device. This
operation is described in the IDT79RC4640 and IDT79RC4650 RISC
Processor Hardware User’s Manual.
– Added 267 MHz speed to the RV4650, removed 100MHz from
the RV4650
ꢇꢂꢃꢂꢐꢘꢔꢁꢁꢃꢐꢙꢁꢒꢉꢆꢉꢋꢌꢐꢍꢉꢆꢃꢋꢅꢚ
– Corrected several incorrect references to figures and tables.
AC Electrical Characteristics:
– Replaced existing figure in Mode Configuration Interface
Reset Sequence section with 3 reset figures.
– Revised values in System Interface Parameters table.
– In System Interface Parameters tables (RC4650 and
RV4650), Data Setup and Data Hold minimums changed.
Features:
– Added 150 MHz operation frequency.
– Upgraded spec to “final.”
MasterClock
Addr
Write
Data0
CData
Data1
CData
Data2
CData
Data3
CEOD
SysAD
SysCmd
ValidOut
ValidIn
RdRdy
WrRdy
Release
Figure 5 RC4650 Block Write Request (64-bit system interface)
10 of 25
March 28, 2000
IDT79RC4650™
ꢛꢉꢌꢐꢇꢁꢆꢈꢅꢉꢊꢃꢉꢋꢌꢆ
The following is a list of interface, interrupt, and miscellaneous pins available on the RC4650. Pins marked with one asterisk are active when low.
System interface:
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
Input
Output
Input
Input
Input
External request
Signals that the system interface needs to submit an external request.
Release interface
Signals that the processor is releasing the system interface to slave state
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write request.
Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com-
mand or data identifier on the SysCmd bus.
ValidOut*
Output
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command
or data identifier on the SysCmd bus.
SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
SysCmdP
Input/Output
Input/Output
Input/Output
Input/Output
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
Reserved system command/data identifier bus parity
For the RC4650 this signal is unused on input and zero on output.
Clock/control interface:
MasterClock
Input
Master clock
Master clock input used as the system interface reference clock. All output timings are relative to this input
clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during
boot initialization.
VCCP
VSSP
Input
Input
Quiet VCC for PLL
Quiet VCC for the internal phase locked loop.
Quiet VSS for PLL
Quiet VSS for the internal phase locked loop.
Interrupt interface:
Int*(5:0)
Input
Input
Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
NMI*
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
11 of 25
March 28, 2000
IDT79RC4650™
Initialization interface:
VCCOk
Input
VCC is OK
When asserted, this signal indicates to the RC4650 that the power supply has been above Vcc minimum
for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the reading of the
boot-time mode control serial stream.
ColdReset*
Reset*
Input
Input
Cold reset
This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted syn-
chronously with MasterClock.
Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchro-
nously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchro-
nously with MasterClock.
ModeClock
ModeIn
Output
Input
Boot mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six.
Boot mode data in
Serial boot-mode data input.
ꢜꢝꢆꢋꢖꢄꢃꢁꢐꢞꢂ ꢉꢕꢄꢕꢐꢙꢂꢃꢉꢌ!ꢆ
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
±
±
±
V
Terminal Voltage with respect to GND
Operating Temperature(case)
Case Temperature Under Bias
Storage Temperature
–0.51 to +7.0
0 to +85
–55 to +125
–55 to +125
202
–0.51 to +4.6
0 to +85
–55 to +125
–55 to +125
202
–0.51 to +4.6
-40 to +85
–55 to +125
–55 to +125
202
V
TERM
TC
°C
°C
°C
mA
mA
TBIAS
TSTG
I
DC Input Current
IN
IOUT
DC Output Current
503
503
503
1.
VIN minimum = –2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts.
When VIN < 0V or VIN > VCC
2.
3.
Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
ꢙꢁꢈꢋꢕꢕꢁꢌꢎꢁꢎꢐꢑꢊꢁꢅꢂꢃꢉꢋꢌꢐꢓꢁꢕꢊꢁꢅꢂꢃꢄꢅꢁꢐꢂꢌꢎꢐꢘꢄꢊꢊꢖꢚꢐ"ꢋꢖꢃꢂ!ꢁ
Commercial
Industrial
0°C to +85°C (Case)
-40°C + 85°C (Case)
5.0V±5%
3.3V±5%
3.3V±5%
N/A
12 of 25
March 28, 2000
IDT79RC4650™
ꢇꢗꢐ#ꢖꢁꢈꢃꢅꢉꢈꢂꢖꢐꢗꢔꢂꢅꢂꢈꢃꢁꢅꢉꢆꢃꢉꢈꢆꢐ$ꢐꢗꢋꢕꢕꢁꢅꢈꢉꢂꢖꢐꢓꢁꢕꢊꢁꢅꢂꢃꢄꢅꢁꢐꢅꢂꢌ!ꢁ$ꢙ%&'(
= 5.0 5
± %, TCASE = 0°C to +85°C)
(V
CC
V
—
0.1V
—
—
0.1V
—
|IOUT| = 20uA
|IOUT| = 4mA
OL
V
VCC - 0.1V
VCC - 0.1V
OH
V
—
0.4V
—
—
0.4V
—
OL
V
2.4V
–0.5V
2.0V
—
2.4V
–0.5V
2.0V
—
OH
V
0.2V
0.2V
CC
—
—
IL
CC
V
VCC + 0.5V
VCC + 0.5V
IH
I
±10uA
10pF
±10uA
10pF
0 ≤ V ≤ V
IN CC
IN
CIN
—
—
—
—
COUT
I/O
—
10pF
—
10pF
—
20uA
—
20uA
Input/Output Leakage
LEAK
ꢛꢋꢏꢁꢅꢐꢗꢋꢌꢆꢄꢕꢊꢃꢉꢋꢌ$ꢙ%&'(
System Condition:
100/50MHz
133/67MHz
—
2
2
ICC
standby
—
—
75 mA
—
—
100 mA
CL = 0pF3
CL = 50pF
2
2
150 mA
200 mA
2
2
2
2
active,
64-bit bus
option
700 mA
900 mA
900 mA
950 mA
CL = 0pF
No SysAd activity3
2
2
2
2
800 mA
1000 mA
1000 mA
1100 mA
CL = 50pF
R4x00 compatible writes,
TC = 25oC
2
4
2
4
800 mA
1200 mA
1000 mA
1350 mA
CL = 50pF
Pipelined writes or write re-
issue,
TC = 25oC
1.
Typical integer instruction mix and cache miss rates, Vcc 3.3V, TA=25×.
2.
3.
4.
These are not tested. They are the results of engineering analysis and are provided for reference only.
Guaranteed by design.
These are the specifications IDT tests to insure compliance.
13 of 25
March 28, 2000
IDT79RC4650™
ꢜꢗꢐꢁꢖꢁꢈꢃꢅꢉꢈꢂꢖꢐꢗꢔꢂꢅꢂꢈꢃꢁꢅꢉꢆꢃꢉꢈꢆꢐ$ꢐꢗꢋꢕꢕꢁꢅꢈꢉꢂꢖꢐꢓꢁꢕꢊꢁꢅꢂꢃꢄꢅꢁꢐꢙꢂꢌ!ꢁ$ꢙ%&'(
(V =5.0V ± 5%; TCASE = -0°C to +85°C)
CC
Pipeline clock frequency
MasterClock HIGH
PClk
tMCHIGH
tMCLOW
—
50
4
100
—
—
50
40
±250
5
50
3
133
—
—
67
40
±250
4
MHz
ns
Transition ≤ tMCRise/Fall
MasterClock LOW
Transition ≤ tMCRise/Fall
4
3
ns
MasterClock Frequency1
—
—
—
—
—
—
25
20
—
—
—
—
25
15
—
—
—
—
MHz
ns
—
MasterClock Period
tMCP
2
Clock Jitter for MasterClock tJitterIn
ps
2
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
tMCRise
ns
2
tMCFall
5
4
ns
2
tModeCKP
256*
tMCP
256*
tMCP
ns
1.
Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled.
Guaranteed by design.
2.
ꢘꢚꢆꢃꢁꢕꢐ)ꢌꢃꢁꢅ*ꢂꢈꢁꢐꢛꢂꢅꢂꢕꢁꢃꢁꢅꢆ$ꢙ%&'(
(V =5.0V ± 5%; TCASE = 0°C to +85°C)
CC
Note: Timings are measured from 1.5V of the clock to 1.5V of the signal.
Data Output1
Data Output Hold
Data Setup
tDO = Max
mode
= 10 (fastest)
1.02
9
1.02
9
ns
14..13
mode14..13 = 11 (85%)
mode14..13 = 00 (66%)
mode
= 01 (slowest)
2.02
1.0
12
—
2.0
1.0
12
—
ns
ns
14..13
3
tDOH
mode14..13 = 10
mode14..13 = 11
mode14..13 = 00
mode14..13 = 01
tDS
t
t
= 5ns
= 5ns
5.5
2
—
—
4.5
1.5
—
—
ns
ns
rise
fall
Data Hold
tDH
1.
Capacitive load for all output timings is 50pF.
Guaranteed by design.
2.
3.
50pf loading on external output signals, fastest settings
14 of 25
March 28, 2000
IDT79RC4650™
+ꢋꢋꢃ,ꢃꢉꢕꢁꢐ)ꢌꢃꢁꢅ*ꢂꢈꢁꢐꢛꢂꢅꢂꢕꢁꢃꢁꢅꢆ$ꢙ%&'(
(V =5.0V ± 5%; TCASE = 0°C to +85°C)
CC
Mode Data Setup
Mode Data Hold
tDS
—
—
3
0
—
—
3
0
—
—
Master Clock Cycle
Master Clock Cycle
tDH
Load Derate
CLD
—
—
2
—
2
ns/25pF
ꢇꢗꢐ#ꢖꢁꢈꢃꢅꢉꢈꢂꢖꢐꢗꢔꢂꢅꢂꢈꢃꢁꢅꢉꢆꢃꢉꢈꢆꢐ$ꢐꢗꢋꢕꢕꢁꢅꢈꢉꢂꢖꢐ-ꢐ)ꢌꢎꢄꢆꢃꢅꢉꢂꢖꢐꢓꢁꢕꢊꢁꢅꢂꢃꢄꢅꢁꢐ
ꢙꢂꢌ!ꢁ$ꢙ"%&'(
= 3.3 5
± %, Commercial TCASE = 0°C to +85°C, Industrial TCASE = -40°C to +85°C)
(V
CC
V
—
0.1V
—
—
0.1V
—
|IOUT| = 20uA
|IOUT| = 4mA
OL
V
VCC - 0.1V
VCC - 0.1V
OH
V
—
0.4V
—
—
0.4V
—
OL
V
2.4V
–0.5V
2.4V
–0.5V
OH
V
0.2V
0.2V
CC
—
—
IL
CC
V
0.7V
VCC + 0.5V
0.7V
CC
VCC + 0.5V
IH
CC
I
—
—
—
—
±10uA
10pF
—
—
—
—
±10uA
10pF
0 ≤ V ≤ V
IN CC
IN
C
—
—
IN
COUT
I/O
10pF
10pF
20uA
20uA
Input/Output Leakage
LEAK
V
—
0.1V
—
0.1V
—
—
0.1V
—
|IOUT| = 20uA
OL
V
VCC - 0.1V
—
VCC - 0.1V
VCC - 0.1V
OH
V
—
0.4V
—
—
0.4V
—
—
0.4V
—
|IOUT| = 4mA
—
OL
V
2.4V
–0.5V
2.4V
–0.5V
2.4V
–0.5V
OH
V
0.2V
0.2V
0.2V
CC
IL
CC
CC
15 of 25
March 28, 2000
IDT79RC4650™
V
0.7V
VCC + 0.5V
0.7V
VCC + 0.5V
0.7V
CC
VCC + 0.5V
—
IH
CC
CC
I
—
—
—
—
±10uA
10pF
—
—
—
—
±10uA
10pF
—
—
—
—
±10uA
10pF
0 ≤ V ≤ V
IN CC
IN
C
—
—
IN
COUT
I/O
10pF
10pF
10pF
20uA
20uA
20uA
Input/Output Leakage
LEAK
1.
Industrial temperature range is not available at 267MHz
ꢛꢋꢏꢁꢅꢐꢗꢋꢌꢆꢄꢕꢊꢃꢉꢋꢌ$ꢙ"%&'(
System Condition
133/67MHz
150/75MHz
—
2
2
ICC
standby
—
—
60 mA
—
—
60mA
CL = 0pF3
2
2
110 mA
110mA
CL = 50pF
2
2
2
2
active,
625 mA
700 mA
700 mA
800mA
CL = 0pF, No SysAd activity3
64-bit bus
option
2
2
2
2
700 mA
800 mA
850mA
900mA
CL = 50pF R4x00 |compatible writes
TC = 25oC
2
4
2
4
700 mA
900 mA
850mA
1000mA
CL = 50pF Pipelined writes or Write re-issue,
TC = 25oC
1.
Typical integer instruction mix and cache miss rates, Vcc 3.3V, TA=25×.
2.
3.
4.
These are not tested. They are the result of engineering analysis and are provided for reference only.
Guaranteed by design.
These are the specifications IDT tests to insure compliance.
System Condition 180/90MHz
200/100MHz
267/89MHz
—
—
2
2
2
ICC standby
—
—
60mA
—
—
60mA
60mA
CL = 0pF3
2
2
2
110mA
110mA
—
110mA
CL = 50pF
2
2
2
2
2
2
active,
855 mA
900mA
925mA
1000mA 925mA
1100mA CL = 0pF, No SysAd activity3
64-bit bus
option
2
2
2
2
2
b
930mA
1000mA 1000mA
1100mA 1000mA
1300mA CL = 50pF R4xxx|compatible writes
TC = 25oC
2
4
2
4
2
a
930mA
1200mA 1000mA
1300mA 1000mA
1500mA CL = 50pF Pipelined writes or Write
re-issue, TC = 25oC
1.
Typical integer instruction mix and cache miss rates, Vcc 3.3V, TA=25×.
These are not tested. They are the result of engineering analysis and are provided for reference only.
Guaranteed by design.
2.
3.
4.
These are the specifications IDT tests to insure compliance.
16 of 25
March 28, 2000
IDT79RC4650™
ꢜꢗꢐ ꢖꢁꢈꢃꢅꢉꢈꢂꢖꢐꢗꢔꢂꢅꢂꢈꢃꢁꢅꢉꢆꢃꢉꢈꢆꢐ$ꢐꢗꢋꢕꢕꢁꢅꢈꢉꢂꢖ-)ꢌꢎꢄꢆꢃꢅꢉꢂꢖꢐꢓꢁꢕꢊꢁꢅꢂꢃꢄꢅꢁ
ꢙꢂꢌ!ꢁ$ꢙ"%&'(
(V =3.3V ± 5%; Commercial TCASE = 0°C to +85°C, Industrial TCASE = -40°C to +85°C)
CC
Note: Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled.
Pipeline clock Frequency
MasterClock HIGH
PClk
50
3
133
—
—
67
40
±250
4
MHz
ns
tMCHIGH
tMCLOW
Transition ≤ tMCRise/Fall
MasterClock LOW
Transition ≤ tMCRise/Fall
3
ns
MasterClock Frequency1
MasterClock Period
—
—
—
—
—
—
25
15
—
—
—
—
MHz
ns
—
tMCP
2
Clock Jitter for MasterClock
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
tJitterIn
ps
2
tMCRise
ns
2
tMCFall
4
ns
2
tModeCKP
256*
tMCP
ns
1.
Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled.
2.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
Pipeline clock Frequency
MasterClock HIGH
50
3
150
—
—
75
40
±250
3
50
3
180
—
50
3
200
—
—
100
40
100
3
267
—
—
125
20
MHz
ns
MasterClock LOW
3
3
—
3
3
ns
(5)
MasterClock Frequency
MasterClock Period
25
13.3
—
—
—
—
25
11.1
—
—
—
—
90
25
10
—
—
—
—
50
8
MHz
ns
40
Clock Jitter for MasterClock
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
±250
2.5
2.5
±250
2
—
—
—
—
±250
2
ps
ns
3
2
2
ns
256*
tMCP
256*
tMCP
256*
tMCP
256*
tMCP
ns
17 of 25
March 28, 2000
IDT79RC4650™
ꢘꢚꢆꢃꢁꢕꢐ)ꢌꢃꢁꢅ*ꢂꢈꢁꢐꢛꢂꢅꢂꢕꢁꢃꢁꢅꢆ$ꢙ"%&'(ꢐ
(V =3.3V ± 5%; Commercial TCASE = 0°C to +85°C, Industrial TCASE = -40°C to +85°C)
CC
Note: Timings are measured from 1.5V of the clock to 1.5V of the signal.
Data Output1
tDM= Min
DO = Max
mode
mode
mode
= 10 (fastest)
= 01 (slowest)
= 10 (fastest)
1.0
2.0
1.0
4.5
1.5
9
1.0
2.0
1.0
4.5
1.5
9
ns
ns
ns
ns
ns
14..13
14..13
14..13
t
12
—
—
—
12
—
—
—
2
Data Output Hold
Input Data Setup
tDOH
tDS
t
= 5ns
= 5ns
rise
t
fall
Input Data Hold
tDH
1.
Capacitive load for all output timings is 50pF.
2.
50pf loading on external output signals, fastest settings
Data Output
tDM= Min
tDO = Max
mode14..13 = 10 (fastest)
mode14..13 = 01 (slowest)
1.0
2.0
1.0
4.5
1.5
9
1.0
4.5
5.0
—
—
—
1.0
—
4.5
ns
ns
ns
ns
ns
10
—
—
—
2.0
1.0
4.5
1.5
5.0
—
—
—
Data Output Hold
Data Input
tDOH*
mode
= 10 (fastest)
1.0
2.5
1.0
14..13
tDS
trise = 3ns
tfall = 3ns
tDH
50pf loading on external output signals, fastest settings
+ꢋꢋꢃꢐꢓꢉꢕꢁꢐ)ꢌꢃꢁꢅ*ꢂꢈꢁꢐꢛꢂꢅꢂꢕꢁꢃꢁꢅꢆ$ꢙ"%&'(
Mode Data
Setup
tDS
—
—
3
0
—
—
3
0
—
—
3
0
—
—
3
0
—
3
0
—
—
ns
ns
Master Clock
Cycle
Mode Data
Hold
tDH
—
Master Clock
Cycle
Load Derate
CLD
—
—
2
—
2
—
2
—
2
—
1
ns/25pF
18 of 25
March 28, 2000
IDT79RC4650™
ꢓꢉꢕꢉꢌ!ꢐꢗꢔꢂꢅꢂꢈꢃꢁꢅꢉꢆꢃꢉꢈꢆ$ꢙ"%&'(
1
2
3
4
Cycle
MasterClock
t
MCkHigh
t
MCkLow
t
MCkP
SysAD,SysCmd Driven
SysADC
D
D
D
t
t
DOH
t
DM
DZ
t
DO
SysAD,SysCmd Received
SysADC
D
D
D
D
t
DS
t
DH
Control Signal CPU driven
ValidOut*
Release*
t
DO
t
DOH
Control Signal CPU received
RdRdy*
WrRdy*
ExtRqst*
ValidIn*
NMI*
t
t
DS
DH
Int*(5:0)
* = active low signal
Figure 6 System Clocks Data Setup, Output, and Hold timing
19 of 25
March 28, 2000
IDT79RC4650™
2.3V
2.3V
Vcc
MasterClock
(MClk)
TDS
> 100ms
256
MClk
256 MClk cycles
VCCOK
ModeClock
ModeIn
cycles
TMDS
TMDH
Bit
255
Bit 1
Bit 0
TDS
TDS
TDS
> 64K MClk cycles
ColdReset*
Reset*
> 64 MClk cycles
TDS
Figure 7 Power-on Reset
Vcc
Master
Clock
(MClk)
TDS
TDS
> 100ms
256
MClk
VCCOK
256 MClk cycles
cycles
ModeClock
ModeIn
TMDS
TMDH
Bit
1
Bit
255
Bit
0
TDS
TDS
> 64K MClk cycles
ColdReset*
Reset*
> 64 MClk cycles
TDS
TDS
Figure 8 Cold Reset
Vcc
Master
Clock
(MClk)
VCCOK
256 MClk cycles
ModeClock
ModeIn
ColdReset*
Reset*
TDS
TDS
> 64 MClk cycles
Figure 9 Warm Reset
20 of 25
March 28, 2000
IDT79RC4650™
ꢐꢛꢔꢚꢆꢉꢈꢂꢖꢐꢘꢊꢁꢈꢉ*ꢉꢈꢂꢃꢉꢋꢌꢆꢐ$ꢐ.(/,ꢛꢉꢌꢐ0ꢀꢛ
21 of 25
March 28, 2000
IDT79RC4650™
22 of 25
March 28, 2000
IDT79RC4650™
ꢙꢗ%&'(ꢐ0ꢀꢛꢐꢛꢂꢈ1ꢂ!ꢁꢐꢛꢉꢌ,ꢑꢄꢃ
Note: N.C. pins should be left floating for maximum flexibility and compatibility with future designs.
1
N.C.
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
N.C.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
N.C.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
N.C.
2
N.C.
N.C.
N.C.
N.C.
3
N.C.
N.C.
N.C.
SysAD59
ColdReset1
SysAD28
VCC
4
N.C.
N.C.
N.C.
5
N.C.
SysCmd2
SysAD36
SysAD4
SysCmd1
VSS
N.C.
6
N.C.
N.C.
7
N.C.
N.C.
VSS
8
N.C.
N.C.
SysAD60
Reset1
SysAD29
SysAD61
SysAD30
VCC
9
N.C.
N.C.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
SysAD11
VSS
VCC
SysAD52
ExtRqst1
VCC
SysAD35
SysAD3
SysCmd0
SysAD34
VSS
VCC
SysCmd8
SysAD42
SysAD10
SysCmd7
VSS
VSS
SysAD21
SysAD53
RdRdy1
Modein
SysAD22
SysAD54
VCC
VSS
SysAD62
SysAD31
SysAD63
VCC
VCC
SysAD2
Int51
VCC
SysAD41
SysAD9
SysCmd6
SysAD40
VSS
SysAD33
SysAD1
VSS
VSS
VCCOK
SysADC3
SysADC7
N.C.
VSS
VCC
Release1
SysAD23
SysAD55
NMI1
Int41
VCC
SysAD32
SysAD0
Int31
N.C.
SysAD8
SysCmd5
SysADC4
SysADC0
VSS
N.C.
VCC
N.C.
VSS
VSS
N.C.
VCC
SysADC2
SysADC6
SysAD24
VCC
N.C.
Int21
VCCP
VCC
SysAD16
SysAD48
Int11
VSSP
SysCmd4
SysAD39
SysAD7
SysCmd3
VSS
MasterClock
VCC
VSS
VSS
SysAD56
SysAD25
SysAD57
VSS
VCC
SysADC5
SysADC1
SysAD17
23 of 25
March 28, 2000
IDT79RC4650™
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
VCC
88
SysAD49
Int01
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
VCC
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VCC
SysAD38
SysAD6
ModeClock
WrRdy1
SysAD37
SysAD5
VSS
89
VSS
VSS
90
SysAD18
VSS
N.C
SysAD47
SysAD15
SysAD46
VCC
91
SysAD26
SysAD58
N.C.
92
VCC
93
SysAD50
ValidIn1
SysAD19
SysAD51
VSS
94
VCC
VSS
95
VSS
SysAD14
SysAD45
SysAD13
SysAD44
VCC
96
SysAD27
N.C.
N.C.
97
N.C.
98
VCC
N.C.
N.C.
99
ValidOut1
SysAD20
N.C.
N.C.
V
SS
N.C.
100
101
102
103
104
N.C.
V
CC
N.C.
N.C.
SysAD12
SysCmdP
SysAD43
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
52
N.C.
N.C.
N.C.
1.
N.C. pins should be left floating for maximum flexibility and compatibility with future designs.
24 of 25
March 28, 2000
IDT79RC4650™
IDT79
YY
XXXX
A
999
A
Temp range/
Process
Package
Speed
Device
Type
Operating
Voltage
Commercial
Blank
I
°
°
(0 C to +85 C Case)
Industrial
°
°
(-40 C to +85 C Case)
DP
208-pin QFP
100
133
150
180
200
100 MHz
133 MHz
150 MHz
180 MHz
200 MHz
267 MHz
267
64-bit processor w/ DSP
Capability
4650
5.0+/-5%
3.3+/-5%
R
RV
"ꢂꢖꢉꢎꢐꢗꢋꢕꢝꢉꢌꢂꢃꢉꢋꢌꢆꢐ
IDT79R4650 - 100, 133MHz DP
QFP package, Commercial Temperature
QFP package, Commercial Temperature
QFP package, Industrial Temperature
IDT79RV4650 - 133, 150, 180, 200, 267MHz DP
IDT79RV4650- 133, 150, 180, 200MHz DPI
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
Santa Clara, CA 95054
800-345-7015 or 408-727-5116
fax: 408-492-8674
email: rischelp@idt.com
phone: 408-492-8208
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
25 of 25
March 28, 2000
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