IDT79RV4700-80DF [IDT]
64-Bit RISC Microprocessor; 64位RISC微处理器
| 型号： | IDT79RV4700-80DF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 64-Bit RISC Microprocessor |
| 文件： | 总25页 (文件大小：325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT79R4700
64-Bit RISC Microprocessor
◆
Available at 80-200MHz, with mode bit dependent output
clock frequencies
Features
◆
True 64-bit microprocessor
◆
◆
64GB physical address space
–
–
–
–
64-bit integer operations
64-bit floating-point operations
64-bit registers
Processor family for a wide variety of embedded
applications
64-bit virtual address space
–
–
–
LAN switches
Routers
Color printers
◆
High-performance microprocessor
–
260 Dhrystone MIPS at 200MHz
100 peak MFLOP/s at 200MHz
Two-way set associative caches
Simple 5-stage pipeline
–
–
–
Description
◆
The IDT79R4700 64-bit RISC Microprocessor is both software and
pin-compatible with the R4XXX processor family. With 64-bit processing
capabilities, the R4700 provides more computational power and data
movement bandwidth than is delivered to typical embedded systems by
32-bit processors.
High level of integration
–
64-bit, 200 MHz integer CPU
64-bit floating-point unit
16KB instruction cache
16KB data cache
Flexible MMU with large, fully associative TLB
–
–
–
–
The R4700 is upwardly software compatible with the IDT79R3000™
microprocessor family, including the IDTRISController™ 79R3051™,
R3052™, R3041™, R3081™ as well as the R4640™, R4650™, RC64474/
475™ and R5000™. An array of development tools facilitates rapid
development of R4700-based systems, allowing a variety of customers
access to the MIPS Open Architecture philosophy.
◆
Low-power operation
–
3.3V power supply, for the “RV” part
5V power supply, for the “R” part
Dynamic power management
–
–
–
Standby mode reduces internal power
◆
Fully software & pin-compatible with 40XX Processor Family
Available in 179-pin PGA or 208-pin QFP
◆
Block Diagram
Data Tag A
Data Set A
Instruction Set A
DTLB Physical
Data Tag B
Store Buffer
SysAD
Instruction Select
Write Buffer
Read Buffer
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Register
Data Set B
DBus
Instruction Set B
Instruction Tag B
IBus
Control
AuxTag
Tag
Load Aligner
Floating-point
Register File
Joint TLB
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
Unpacker/Packer
Floating-point
Add/Sub/Cvt/Div/Sqrt
Integer Divide
Coprocessor 0
DVA
PC Incrementer
Floating-point/Integer
Multiply
System/Memory
Control
Branch Adder
Instruction TLB Virtual
Program Counter
IVA
Phase Lock Loop, Clocks
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.
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April 10, 2001
DSC 9096
2001 Integrated Device Technology, Inc.
IDT79R4700
This data sheet provides an overview of the R4700’s CPU features
and architecture. A more detailed description of this processor is
provided in the IDT79R4700 RISC Processor Hardware User’s Manual,
available from Integrated Device Technology (IDT). Information on
development support, applications notes and complementary products
is available on the IDT Web site www.idt.com or through your local IDT
sales representative.
resource dependencies are made transparent to the programmer,
insuring transportability among implementations of the MIPS instruction
set architecture.
The MIPS integer unit implements a load/store architecture with
single cycle ALU operations (logical, shift, add, sub) and an autono-
mous multiply/divide unit. Register resources include:
◆
32 general-purpose orthogonal integer registers
Note: Throughout this data sheet and any other IDT materials for this
device, the R4700 indicates a 5V part; RV4700 designates a reduced
voltage (3V) part; and the RC4700 reflects either.
◆
HI/LO result registers, for the integer multiply/divide unit
◆
Program counter
Also, the on-chip floating-point co-processor adds 32 floating-point
registers and a floating-point control/status register.
Count
9*
Compare
11*
Register File
PageMask
5*
EntryLo0
2*
Status
Cause
The R4700 has 32 general-purpose registers (shown in Figure 2).
These registers are used for scalar integer operations and address
calculation. The register file consists of two read ports and one write
port and is fully bypassed to minimize operation latency in the pipeline.
EntryHi
10*
EntryLo1
33**
12*
13*
47
EPC
14*
ErrorEPC
30*
Index
0*
Context
4*
XContext
20*
General Purpose Registers
Multiply/Divide Registers
TLB
Random
1*
63
0
BadVAddr
8*
LLAddr
17*
0
r1
r2
•
63
63
0
0
Wired
6*
PRId
Config
HI
(entries protected
15*
16*
from TLBWR)
0
TagHi
29*
TagLo
28*
LO
* Register number
•
ECC
26*
CacheErr
27*
•
Program Counter
•
63
0
r29
r30
r31
PC
Figure 1 The RC4700 CPO Registers
Hardware Overview
Figure 2 R4700 CPU Registers
The RC4700 processor family brings a high-level of integration
designed for high-performance computing. The R4700’s key elements
are briefly described below. A more detailed explanation of each
subsystem is available in the user’s manual.
ALU
The RC4700 ALU consists of the integer adder and logic unit. The
adder performs address calculations in addition to arithmetic operations,
and the logic unit performs all logical and shift operations. Each of these
units is highly optimized and can perform an operation in a single pipe-
line cycle.
Pipeline
The RC4700 uses a simple 5-stage pipeline, similar to the pipeline
structure implemented in the IDT79R32364. This pipeline’s simplicity
allows the RC4700 to be lower cost and lower power than super-scalar
or super-pipelined processors. The pipeline stages are shown in Figure
3 on page 3.
Integer Multiply/Divide
To perform integer multiply and divide operations, the RC4700 uses
the floating-point unit. The results of the operation are placed in the HI
and LO registers. The values can then be transferred to the general
purpose register file using the MFHI/MFLO instructions. To prevent the
Integer Execution Engine
The R4700 implements the MIPS-III Instruction Set architecture and
is upwardly compatible with applications that run on earlier generation
parts.
Implementation of the MIPS-III architecture results in 64-bit opera-
tions, better code density, greater multi-processing support, improved
performance for commonly used code sequences in operating system
kernels and faster execution of floating-point intensive applications. All
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IDT79R4700
I0
I1
I2
I3
I4
1I
2I
1R
1I
2R
2I
1A
1R
1I
2A
2R
2I
1D
1A
1R
1I
2D
2A
2R
2I
1W
1D
1A
1R
1I
2W
2D
2A
2R
2I
1W
1D
1A
1R
2W
2D
2A
2R
1W
1D
1A
•••
•••
•••
one cycle
Key to Figure
1I-1R
2I
2A-2D
1D
1D-2D
2R
Instruction cache access
Instruction virtual-to-physical address translation in ITLB
Data cache access and load align
Data virtual-to-physical address translation in DTLB
Virtual-to-physical address translation in JTLB
Register file read
2R
Bypass calculation
2R
Instruction decode
2R
1A
Branch address calculation
Issue or slip decision
1A-2A
1A
2A
Integer add, logical, shift
Data virtual address calculation
Store align
1A
Branch decision
2W
Register file write
Figure 3 RC4700 Pipeline Stages
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IDT79R4700
occurrence of an interlock or stall, a required number of processor
internal cycles must occur between an integer multiply or divide and a
subsequent MFHI or MFLO operation.
Single
Double
Operation
ADD
Precision
Precision
4
4
4
4
Operation
MULT
DIV
32-bit
64-bit
SUB
6 - 9
42
7 - 10
74
MUL
4
5
DIV
32
31
3
61
60
3
SQRT
CMP
Floating-Point Co-Processor
The RC4700 incorporates a complete floating-point co-processor on
chip and includes a floating-point register file and execution units. The
floating-point co-processor forms a “seamless” interface with the integer
unit, decoding and executing instructions in parallel with the integer unit.
FIX
4
4
FLOAT
ABS
6
6
1
1
Floating-Point Units
MOV
1
1
The RC4700 floating-point execution units support single and double
precision arithmetic, as specified in the IEEE Standard 754. The execu-
tion unit is separated into a multiply unit and a combined add/convert/
divide/square root unit. Overlap of multiplies and add/subtract is
supported. The multiplier is partially pipelined, allowing a new multiply to
begin every four cycles.
NEG
1
1
LWC1, LDC1
SWC1, SDC1
2
2
1
1
Table 1 RC4700 Instruction Latencies
The RC4700 maintains fully precise floating-point exceptions while
allowing both overlapped and pipelined operations. Precise exceptions
are extremely important in mission-critical environments and highly
desirable for debugging in any environment.
System Control Co-processor (CP0)
The system control co-processor in the MIPS architecture is respon-
sible for the virtual memory sub-system, the exception control system
and the diagnostics capability of the processor. In the MIPS architec-
ture, the system control co-processor (and thus the kernel software) is
implementation dependent.
The floating-point unit operation’s set includes floating-point add,
subtract, multiply, divide, square root, conversion between fixed-point
and floating-point format, conversion among floating-point formats and
floating-point compare. These operations comply with the IEEE Stan-
dard 754.
System Control Co-Processor Registers
The RC4700 incorporates all system control co-processor (CP0)
registers, on-chip. These registers (shown in Figure 1 on page 2)
provide the path through which the virtual memory system’s page
mapping is examined and changed, exceptions are handled and oper-
ating modes are controlled (kernel vs. user mode, interrupts enabled or
disabled, cache features). In addition, to aid in cache diagnostic testing
and assist in data error detection, the RC4700 includes registers to
implement a real-time cycle counting facility.
Table 1 lists the latencies of some of the floating-point instructions in
internal processor cycles. Note that multiplies are pipelined so that a
new multiply can be initiated every four pipeline cycles
Floating-Point General Register File
The floating-point register file is made up of thirty-two 64-bit regis-
ters. With the LDC1 and SDC1 instructions the floating-point unit can
take advantage of the 64-bit wide data cache and issue a co-processor
load or store doubleword instruction in every cycle.
Virtual-to-Physical Address Mapping
The floating-point control register space contains two registers: one
for determining configuration and revision information for the copro-
cessor and one for control and status information. These are primarily
involved with diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
To establish a secure environment for user processing, the RC4700
provides the user, supervisor, and kernel modes of virtual addressing,
available to system software. Bits in a status register determine which
virtual addressing mode is used.
While in user mode, the RC4700 provides a single, uniform virtual
address space of 256GB (2GB for 32-bit address mode). When oper-
ating in the kernel mode, four distinct virtual address spaces—totalling
1024GB (4GB in 32-bit address mode)—are simultaneously available
and are differentiated by the high-order bits of the virtual address.
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IDT79R4700
of mappings can be locked into the TLB and avoid being randomly
replaced. This facilitates the design of real-time systems, by allowing
deterministic access to critical software.
The RC4700 processor also supports a supervisor mode in which the
virtual address space is 256.5GB (2.5GB in 32-bit address mode),
divided into three regions that are based on the high-order bits of the
virtual address. If the RC4700 is configured for 64-bit virtual addressing,
the virtual address space layout is an upwardly compatible extension of
the 32-bit virtual address space layout. Figure 4 on page 5 shows the
address space layout for the 32-bit virtual address operation.
The joint TLB also contains information to control the cache coher-
ency protocol for each page. Specifically, each page has attribute bits to
determine whether the coherency algorithm is uncached, non-coherent
write-back, non-coherent write-through write-allocate or non-coherent
write-through no write-allocate. Non-coherent write-back is typically
used for both code and data on the RC4700; however, hardware-based
cache coherency is not supported.
Memory Management Unit (MMU)
The Memory management unit controls the virtual memory system
page mapping. It consists of an instruction address translation buffer
(the ITLB), a data address translation buffer (the DTLB), a Joint TLB (the
JTLB), and co-processor registers used for the virtual memory mapping
sub-system.
0xFFFFFFFF
Kernel virtual address space
(kseg3)
0xE0000000
0xDFFFFFFF
Mapped, 0.5GB
Supervisor virtual address space
(sseg)
Instruction TLB (ITLB)
Mapped, 0.5GB
The RC4700 also incorporates a two-entry instruction TLB. Each
entry maps a 4KB page. The instruction TLB improves performance by
allowing instruction address translation to occur in parallel with data
address translation. When a miss occurs on an instruction address
translation, the least-recently used ITLB entry is filled from the JTLB.
The operation of the ITLB is invisible to the user.
0xC0000000
0xBFFFFFFF
Uncached kernel physical address space
(kseg1)
0xA0000000
0x9FFFFFFF
Unmapped, 0.5GB
Cached kernel physical address space
(kseg0)
Data TLB (DTLB)
Unmapped, 0.5GB
The RC4700 also incorporates a four-entry data TLB. Each entry
maps a 4KB page. The data TLB improves performance by allowing
data address translation to occur in parallel with instruction address
translation. When a miss occurs on a data address translation, the DTLB
is filled from the JTLB. The DTLB refill is pseudo-LRU: the least recently
used entry of the least recently used half is filled. The operation of the
DTLB is invisible to the user.
0x80000000
0x7FFFFFF
User virtual address space
(useg)
Mapped, 2.0GB
Joint TLB (JTLB)
For fast virtual-to-physical address decoding, the RC4700 uses a
large, fully associative TLB that maps 96 virtual pages to their corre-
sponding physical addresses. The TLB is organized as 48 pairs of even-
odd entries and maps a virtual address and address space identifier into
the large, 64GB physical address space.
0x00000000
Figure 4 Kernel Mode Virtual Addressing (32-bit Mode)
Cache Memory
Two mechanisms are provided to assist in controlling the amount of
mapped space and the replacement characteristics of various memory
regions. First, the page size can be configured, on a per-entry basis, to
map a page size of 4KB to 16MB (in multiples of 4). A CP0 register is
loaded with the page size of a mapping, and that size is entered into the
TLB when a new entry is written. Thus, operating systems can provide
special purpose maps; for example, a typical frame buffer can be
memory mapped using only one TLB entry.
To keep the RC4700’s high-performance pipeline full and operating
efficiently, the RC4700 incorporates on-chip instruction and data caches
that can be accessed in a single processor cycle. Each cache has its
own 64-bit data path and can be accessed in parallel.
Instruction Cache
The RC4700 incorporates a two-way set associative on-chip instruc-
tion cache. This virtually indexed, physically tagged cache is 16KB in
size and is protected with word parity.
The second mechanism controls the replacement algorithm, when a
TLB miss occurs. The RC4700 provides a random replacement algo-
rithm to select a TLB entry to be written with a new mapping; however,
the processor provides a mechanism whereby a system specific number
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IDT79R4700
Because the cache is virtually indexed, the virtual-to-physical
address translation occurs in parallel with the cache access, further
increasing performance by allowing these two operations to occur simul-
taneously. The tag holds a 24-bit physical address and valid bit and is
parity protected.
The system interface consists of a 64-bit Address/Data bus with
eight check bits and a 9-bit command bus protected with parity. In addi-
tion, there are eight handshake signals and six interrupt inputs. The
interface has a simple timing specification and is capable of transferring
data between the processor and memory at a peak rate of 500MB/sec
with a 67MHz bus.
The instruction cache is 64-bits wide and can be refilled or accessed
in a single processor cycle. For a peak instruction bandwidth of 800MB/
sec at 200MHz, instruction fetches require only 32 bits per cycle. To
reduce power dissipation, sequential accesses take advantage of the
64-bit fetch. To minimize the cache miss penalty, cache miss refill writes
use 64 bits-per-cycle, and to maximize cache performance, the line size
is eight instructions (32 bytes).
System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to transfer
addresses and data between the RC4700 and the rest of the system. It
is protected with an 8-bit parity check bus, SysADC.
The system interface is configurable to allow easier interfacing to
memory and I/O systems of varying frequencies. The data rate and the
bus frequency at which the RC4700 transmits data to the system inter-
face are programmable via boot time mode control bits. Also, the rate at
which the processor receives data is fully controlled by the external
device. Therefore, either a low cost interface requiring no read or write
buffering or a faster, high performance interface can be designed to
communicate with the RC4700. Again, the system designer has the flex-
ibility to make these price/performance trade-offs.
Data Cache
For fast, single cycle data access, the RC4700 includes a 16KB on-
chip data cache that is two-way set associative with a fixed 32-byte
(eight words) line size.
The data cache is protected with byte parity and its tag is protected
with a single parity bit. It is virtually indexed and physically tagged to
allow simultaneous address translation and data cache access
The normal write policy is writeback, which means that a store to a
cache line does not immediately cause memory to be updated. This
increases system performance by reducing bus traffic and eliminating
the bottleneck of waiting for each store operation to finish before issuing
a subsequent memory operation. Software can however select write-
through on a per-page basis when it is appropriate, such as for frame
buffers.
System Command Bus
The RC4700 interface has a 9-bit System Command (SysCmd) bus.
The command bus indicates whether the SysAD bus carries an address
or data. If the SysAD carries an address, then the SysCmd bus also
indicates what type of transaction is to take place (for example, a read
or write). If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data word trans-
mitted, or the cache state of this data line is clean exclusive). The
SysCmd bus is bidirectional to support both processor requests and
external requests to the RC4700. Processor requests are initiated by
the RC4700 and responded to by an external device. External requests
are issued by an external device and require the RC4700 to respond.
Associated with the data cache is the store buffer. When the RC4700
executes a Store instruction, this single-entry buffer gets written with the
store data while the tag comparison is performed. If the tag matches,
then the data is written into the data cache in the next cycle that the data
cache is not accessed (the next non-load cycle). The store buffer allows
the R4700 to execute a store instruction every processor cycle and to
perform back-to-back stores without penalty.
The RC4700 supports one to eight byte and block transfers on the
SysAD bus. In the case of a sub-doubleword transfer, the low-order
three address bits give the byte address of the transfer, and the
SysCmd bus indicates the number of bytes being transferred.
The data cache can provide 8 bytes each clock cycle, for a peak
bandwidth of 1.6 GB/sec.
Handshake Signals
Write Buffer
There are six handshake signals on the system interface. Two of
these, RdRdy* and WrRdy* are used by an external device to indicate to
the RC4700 whether it can accept a new read or write transaction. The
RC4700 samples these signals before deasserting the address on read
and write requests.
Writes to external memory—whether they are cache miss write-
backs, stores to uncached or write-through addresses—use the on-chip
write buffer. The write buffer holds a maximum of four 64-bit address and
64-bit data pairs. The entire buffer is used for a data cache writeback
and allows the processor to proceed in parallel with memory updates.
ExtRqst* and Release* are used to transfer control of the SysAD and
SysCmd buses between the processor and an external device. When
an external device needs to control the interface, it asserts ExtRqst*.
The RC4700 responds by asserting Release* to release the system
interface to slave state.
System Interface
The RC4700 supports a 64-bit system interface. This interface oper-
ates from two clocks—TClock[1:0] and RClock[1:0]—provided by the
RC4700, at some division of the internal clock.
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IDT79R4700
information to be kept in a low-cost serial EEPROM; alternatively, the
20-or-so bits could be generated by the system interface ASIC or a
simple PAL.
ValidOut* and ValidIn* are used by the RC4700 and the external
device respectively to indicate that there is a valid command or data on
the SysAD and SysCmd buses. The RC4700 asserts ValidOut* when it
is driving these buses with a valid command or data, and the external
device drives ValidIn* when it has control of the buses and is driving a
valid command or data.
Immediately after the VCCOK signal is asserted, the processor reads a
bit stream of 256 bits to initialize all fundamental operational modes.
After initialization is complete, the processor continues to drive the serial
clock output, but no further initialization bits are read.
Non-overlapping System Interface
JTAG Interface
The RC4700 bus uses a non-overlapping system interface. This
means that only one processor request may be outstanding at a time
and that the request must be serviced by an external device before the
RC4700 issues another request. The RC4700 can issue read and write
requests to an external device, and an external device can issue read
and write requests to the RC4700.
The RC4700 supports the JTAG interface pins, with the serial input
connected to serial output. Boundary scan is not supported.
Boot-Time Modes
The boot-time serial mode stream is defined in Table 3. Bit 0 is the
first bit presented to the processor when VCCOK is asserted; bit 255 is the
last.
For processor read transaction the RC4700 asserts ValidOut* and
simultaneously drives the address and read command on the SysAD
and SysCmd buses. If the system interface has RdRdy* asserted, then
the processor tristates its drivers and releases the system interface to
slave state by asserting Release*. The external device can then begin
sending the data.
Power Management1
CP0 is also used to control the power management for the RC4700.
This is the standby mode and can be used to reduce the power
consumption of the internal core of the CPU. Standby mode is entered
by executing the WAIT instruction with the SysAD bus idle and is exited
by an interrupt.
Figure 5 on page 10 shows a processor block read request and the
external agent read response. The read latency is four cycles (ValidOut*
to ValidIn*), and the response data pattern is DDxxDD. Figure 6 on
page 10 shows a processor block write.
Write Reissue and Pipeline Write
Standby Mode Operations
The RC4700 provides a means to reduce the amount of power
consumed by the internal core when the CPU would otherwise not be
performing any useful operations. This is known as “Standby Mode.”
The RC4700 implements additional write protocols that have been
designed to improve performance. This implementation doubles the
effective write bandwidth. The write re-issue has a high repeat rate of
two cycles per write. A write issues if WrRdy* is asserted two cycles
earlier and is still asserted at the issue cycle. If it is not still asserted, the
last write re-issues again. Pipelined writes have the same two cycle per
write repeat rate but can issue one additional write after WrRdy* de-
asserts. They still follow the issue rule as R4x00 mode for other writes.
Entering Standby Mode
Executing the WAIT instruction enables interrupts and enters
Standby mode. When the WAIT instruction finishes the W pipe-stage, if
the SysAd bus is currently idle, the internal clocks will shut down, thus
freezing the pipeline. The PLL, internal timer, some of the input pin
clocks (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*), and the
output clocks—TClock[1:0], RClock[1:0] SyncOut, Modeclock and
MasterOut—will continue to run. If the conditions are not correct when
the WAIT instruction finishes the W pipe-stage (such as the SysAd bus
is not idle), the WAIT is treated as a NOP.
External Requests
The RC4700 responds to requests issued by an external device. The
requests can take several forms. An external device may need to supply
data in response to an RC4700 read request or it may need to gain
control over the system interface bus to access other resources which
may be on that bus. It also may issue requests to the processor, such as
a request for the RC4700 to write to the RC4700 interrupt register. The
RC4700 supports Write, Null, and Read Response external requests.
Once the CPU is in Standby Mode, any interrupt— including the
internally generated timer interrupt—will cause the CPU to exit Standby
Mode.
Boot-Time Options
Fundamental operational modes for the processor are initialized by
the boot-time mode control interface. The boot-time mode control inter-
face is a serial interface operating at a very low frequency (MasterClock
divided by 256). The low-frequency operation allows the initialization
1.
The R4700 implements advanced power management, to substantially
reduce the average power dissipation of the device. This operation is described
in the R4700 Microprocessor Hardware User’s Manual.
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IDT79R4700
Thermal Considerations
The RC4700 uses special packaging techniques to improve the
thermal properties of high-speed processors. The RC4700 is packaged
using cavity down packaging in a 179-pin PGA package, and a 208-lead
QFP package. These packages effectively dissipate the power of the
CPU, increasing device reliability.
The R4700 is guaranteed in a case temperature range of 0° to +85°
C. The type of package, speed (power) of the device, and airflow condi-
tions affect the equivalent ambient temperature conditions that will meet
this specification.
The equivalent allowable ambient temperature, TA, can be calculated
using the thermal resistance from case to ambient ( CA) of the given
package. The following equation relates ambient and case tempera-
tures:
TA = TC - P * CA
where P is the maximum power consumption at hot temperature,
calculated by using the maximum ICC specification for the device.
Typical values for CA at various airflows are shown in Table 2:.
CA
Airflow (ft/min)
PGA
0
200
7
400
5
600
3
800
2.5
8
1000
16
21
2
7
QFP
13
10
9
Table 2: Thermal Resistance ( CA) at Various Airflows
Revision History
Revision History
January 1996: Initial draft.
March 1997: Deleted data on 150MHz speed for 5V part only.
August 1997: Upgraded 80 to 175 MHz speed specs from “Prelimi-
nary” to “Final.”
June 1999: Upgraded speed to 200MHz on 3V part specs. Package
change to DP.
June 29, 2000: Added back 175 and 200 MHz speeds.
April 10, 2001: In the Data Output category of the System Interface
Parameters tables, changed values in the Min column for all speeds
from 1.0 to 0.
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IDT79R4700
Mode bit
Description
reserved (must be zero)
Mode bit
Description
Output driver strength
0
14:13
10 → 100% strength (fastest),
11 → 83% strength,
00 → 67% strength,
01 → 50% strength (slowest)
4:1
Writeback data rate
0 → ∆,
bit 15
0 → TClock[0] enabled
1 → TClock[0] disabled
1 → DDx,
2 → DDxx,
3 → DxDx,
4 → DDxxx,
5 → DDxxxx,
6 → DxxDxx,
7 → DDxxxxxx,
8 → DxxxDxxx,
9-→ reserved
7:5
Clock divisor
0 → 2,
bit 16
0 → TClock[1] enabled
1 → TClock[1] disabled
1 → 3,
2 → 4,
3 → 5,
4 → 6,
5 → 7,
6 → 8,
7 reserved
8
0 → Little endian,
1 → Big endian
bit 17
bit 18
0 →RClock[0] enabled
1 → RClock[0] disabled
10:9
00 → R4000 compatible,
01 → reserved,
0 → RClock[1] enabled
1 →RClock[1] disabled
10 → pipelined writes,
11 → write re-issue
11
12
Disable the timer interrupt on Int[5].
0 → Enabled
1 → Disabled
255:19
Reserved (must be zero)
reserved (must be zero)
Table 3 Boot-time Serial Mode Stream
9 of 25
April 10, 2001
IDT79R4700
TClock
RClock
Addr
Read
Data0
CData
Data1
CData
Data3
CEOD
SysAD
Data2
CData
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Figure 5 Processor Block Read
TClock
RClock
Addr
Data0
CData
Data1
CData
Data2
CData
Data3
SysAD
Write
CEOD
SysCmd
ValidOut*
ValidIn
RdRdy*
WrRdy*
Release*
Figure 6 Processor Block Write
10 of 25
April 10, 2001
IDT79R4700
Pin Description
The table below provides a list of interface, interrupt and miscellaneous pins that are available on the RC4700. Note that signals marked with an
asterisk are active when low. Boundary scan is not supported.
Pin Name Type
Description
System Interface
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
I
O
I
External request
Signals that the system interface needs to submit an external request.
Release interface
Signals that the processor is releasing the system interface to slave state.
Read Ready
Signals that an external agent can now accept a processor read.
I
Write Ready
Signals that an external agent can now accept a processor write request.
I
Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com-
mand or data identifier on the SysCmd bus.
ValidOut*
O
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or
data identifier on the SysCmd bus.
SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
SysCmdP
I/O
I/O
I/O
I/O
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
Reserved system command/data identifier bus parity
for the R4700 unused on input and zero on output.
Clock/Control Interface
MasterClock
MasterOut
RClock(1:0)
TClock(1:0)
IOOut
I
Master clock
Master clock input at one half the processor operating frequency.
O
O
O
O
I
Master clock out
Master clock output aligned with MasterClock.
Receive clocks
Two identical receive clocks at the system interface frequency.
Transmit clocks
Two identical transmit clocks at the system interface frequency.
Reserved for future output
Always HIGH.
IOIn
Reserved for future input
Should be driven HIGH.
SyncOut
O
Synchronization clock out
Must be connected to SyncIn through an interconnect that models the interconnect between MasterOut,
TClock, RClock, and the external agent.
SyncIn
Fault*
I
Synchronization clock in
Synchronization clock input. See SyncOut.
O
Fault
Always HIGH.
11 of 25
April 10, 2001
IDT79R4700
Pin Name Type
Description
VCCP
I
Quiet VCC for PLL
Quiet VCC for the internal phase locked loop.
VSSP
I
Quiet VSS for PLL
Quiet VSS for the internal phase locked loop.
Interrupt Interface
Int*(5:0)
I
I
Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
NMI*
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
Initialization Interface
VCCOk
I
I
I
VCC is OK
When asserted, this signal indicates to the R4700 that the power supply has been above the Vcc minimum
for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the reading of the
boot-time-mode-control serial stream.
ColdReset*
Reset*
Cold reset
This signal must be asserted for a power on reset or a cold reset. The clocks SClock, TClock, and RClock
begin to cycle and are synchronized with the de-assertion edge of ColdReset. ColdReset must be de-
asserted synchronously with MasterOut.
Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously
for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with
MasterOut.
ModeClock
ModeIn
O
I
Boot-mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six.
Boot-mode data in
Serial boot-mode data input.
Absolute Maximum Ratings
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RV4700
3.3V±5%
R4700
5.0V±5%
Symbol
Rating
Unit
Commercial
Commercial
VTERM
Terminal Voltage with respect to GND
–0.51 to +7.0
V
–0.51 to +4.6
0 to +85
TC
Operating Temperature (case)
Case Temperature Under Bias
Storage Temperature
0 to +85
–55 to +125
–55 to +125
202
°C
°C
°C
mA
mA
TBIAS
TSTG
IIN
–55 to +125
–55 to +125
202
DC Input Current
IOUT
DC Output Current
50
503
1.
V
minimum = -2.0V for pulse width less than 15ns. V should not exceed V +0.5V.
IN CC
IN
2.
3.
When V < 0.0V or V >V .
CC
IN
IN
Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
12 of 25
April 10, 2001
IDT79R4700
Recommended Operation Temperature and Supply Voltage
RV4700
R4700
Grade
Temperature
GND
VCC
VCC
Commercial
0°C to +85°C (Case)
0V
3.3V±5%
5.0V±5%
DC Electrical Characteristics—R4700
(V = 5.0±5%, TCASE = 0°C to +85°C)
cc
Parameter
R4700 80 MHz
R4700 100MHz
R4700 133MHz
Conditions
Min
Max
Min
Max
Min
Max
VOL
VOH
VOL
VOH
VIL
—
VCC - 0.1V
—
0.1V
—
—
VCC - 0.1V
—
0.1V
—
—
VCC - 0.1V
—
0.1V
—
|IOUT|= 20uA
|IOUT|= 4mA
0.4V
—
0.4V
—
0.4V
—
3.5V
3.5V
3.5V
–0.5V
2.0V
0.8V
–0.5V
2.0V
0.8V
–0.5V
2.0V
0.8V
—
—
VIH
VCC
+
VCC
+
VCC +
0.5V
±10uA
15pF
15pF
20uA
0.5V
±10uA
15pF
15pF
20uA
0.5V
±10uA
15pF
15pF
20uA
IIN
—
—
—
—
—
—
—
—
—
—
—
—
0 ≤ VIN ≤ VCC
CIN
—
—
COUT
I/O
Input/Output
Leakage
LEAK
Power Consumption—R4700
R4700 80 MHz
Parameter
R4700 100MHz
R4700 133MHz
Conditions
—
Typical
Max
Typical1
Max
Typical1
Max
System
80/20 MHz
100/25MHz
133/33MHz
Condition:
—
150mA2
215mA2
850 mA2
—
175mA2
250mA2
1000mA2
—
225mA2
325mA2
1300mA2
CL = 0pF3
standby
—
750mA2
—
875mA2
—
CL = 50pF
1175mA2
CL = 0pF
No SysAd activity3
ICC
850mA2
850mA2
1050mA2
1250mAa
975mA2
975mA2
1200mA2
1400mA4
1275mA2
1275mA2
1500mA2
1675mA4
CL = 50pF
R4x00 compatible writes
TC = 25oC
active
CL = 50pF
Pipelined writes or write
re-issue
TC = 25oC
1.
2.
3.
4.
Typical integer instruction mix and cache miss rates.
These are not tested. They are the result of engineering analysis and are provided for reference only.
Guaranteed by design.
These are the specifications IDT tests to insure compliance.
13 of 25
April 10, 2001
IDT79R4700
AC Electrical Characteristics—R4700
(VCC=5.0V ± 5%; TCASE = 0°C to +85°C)
Clock Parameters—R4700
R4700
80MHz
R4700
R4700
Test
Conditions
100MHz
133MHz
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
MasterClock HIGH
tMCHIGH
tMCLOW
Transition ≤ tMCRise
4
—
4
—
—
50
40
3
—
ns
MasterClock LOW
Transition ≤ tMCFall
4
—
4
3
—
ns
MasterClock Frequency1
—
—
—
—
25
25
—
—
40
25
20
—
—
25
15
—
—
67
MHz
ns
—
MasterClock Period
tMCP
40
40
2
Clock Jitter for MasterClock
tJitterIn
±250
±500
±250
±500
±250
±500
ps
2
Clock Jitter for
tJitterOut
ps
MasterOut, SyncOut, TClock, RClock
2
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
tMCRise
—
—
—
—
—
—
—
—
—
—
5.5
—
—
—
—
—
5
—
—
—
—
—
4
ns
ns
ns
ns
ns
2
tMCFall
5.5
5
4
2
tModeCKP
256*tMCP
4*t MCP
2*tMCP
256*tMCP
4*t MCP
2*tMCP
256*tMCP
4*t MCP
2*tMCP
2
JTAG Clock Period
tJTAGCKP
2,3
SyncOut to SyncIn Delay
tSync
1.
Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.
Guaranteed by design.
2.
3.
Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.
System Interface Parameters—R4700
Note: Timings are measured from 1.5V of the clock to 1.5V of the signal.
R4700
80MHz
R4700
R4700
133MHz
100MHz
Parameter
Data Output
Symbol
Test Conditions
Units
Min
Max
Min
Max
Min Max
tDO
mode
= 10 (fastest)
= 01 (slowest)
01
9
01
9
01
9
ns
ns
ns
ns
14..13
mode
01
15
—
—
01
15
—
—
01
12
—
—
14..13
Input Data Setup
tDS
tDH
t
t
= 5ns
= 5ns
3.5
1.5
3.5
1.5
3.5
1.5
rise
fall
Input Data Hold
1.
Guaranteed by design.
Boot-Time Interface Parameters—R4700
R4700
80MHz
R4700
100MHz
R4700
133MHz
Test
Conditions
Parameter
Symbol
Units
Min
Max
Min Max
Min Max
Mode Data Setup
Mode Data Hold
tDS
tDH
—
—
3
0
—
3
0
—
—
3
0
—
—
Master ClockCycle
Master ClockCycle
—
14 of 25
April 10, 2001
IDT79R4700
Capacitive Load Deration—R4700
R4700 80MHz
Min Max
R4700 100MHz
R4700 133MHz
Parameter
Load Derate
Symbol
CLD
Units
ns/25pF
Min
Max
Min
Max
—
2
—
2
—
2
AC Electrical Characteristics — RV4700
(VCC=3.3V ± 5%; TCASE = 0°C to +85°C)
Clock Parameters
RV4700
100MHz
RV4700
133MHz
RV4700
150MHz
Test
Conditions
Parameter
Symbol
Units
Min Max
Min
Max
Min
Max
MasterClock HIGH
tMCHIGH
tMCLOW
Transition ≤ tMCRise/Fall
4
—
—
3
—
—
3
—
—
ns
MasterClock LOW
Transition ≤ tMCRise/Fall
4
3
3
ns
MasterClock Frequency1
—
—
—
—
25
20
—
—
50
25
15
—
—
67
25
13.3
—
75
MHz
ns
—
MasterClock Period
tMCP
40
40
40
2
Clock Jitter for MasterClock
tJitterIn
±250
±500
±250
±500
±250
±500
ps
2
Clock Jitter for MasterOut,
SyncOut, TClock, RClock
tJitterOut
—
ps
2
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
tMCRise
—
—
—
—
—
—
—
—
5
—
—
—
—
4
—
—
—
—
3.5
3.5
ns
ns
2
tMCFall
5
4
tModeCKP
256*tMCP
2*tMCP
256*tMCP
2*tMCP
256*tMCP ns
2*tMCP ns
2, 3
SyncOut to SyncIn Delay
tSync
1.
Typical integer instruction mix and cache miss rates.
Guaranteed by Design.
Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.
2.
3.
RV4700
RV4700
175MHz1
200MHz1
Parameter
Symbol
Test Conditions
Units
Min
Max
Min
Max
MasterClock HIGH
tMCHIGH
tMCLOW
Transition ≤ tMCRise/Fall
3
3
—
—
3
—
ns
MasterClock LOW
Transition ≤ tMCRise/Fall
3
—
ns
MasterClock Frequency2
—
—
—
—
25
87.5
40
25
10
—
—
100
40
MHz
ns
—
MasterClock Period
tMCP
11.4
—
3
Clock Jitter for MasterClock
tJitterIn
±250
±500
±250
±500
ps
3
Clock Jitter for MasterOut,
SyncOut, TClock, RClock
tJitterOu
—
ps
3
MasterClock Rise Time
MasterClock Fall Time
ModeClock Period
tMCRise
—
—
—
—
—
—
—
—
3.5
—
—
—
—
3.5
ns
ns
ns
—
3
tMCFall
3.5
3.5
tModeCKP
256*tMCP
2*tMCP
256*tMCP
2*tMCP
3, 4
SyncOut to SyncIn Delay
tSync
1.
Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.
Typical integer instruction mix and cache miss rates.
Guaranteed by design.
2.
3.
4.
Rise and fall times of the SyncIn signal must match those of MasterClock to avoid the introduction of additional clock skew.
15 of 25
April 10, 2001
IDT79R4700
DC Electrical Characteristics—RV4700
(VCC = 3.3±5%, TCASE = 0°C to +85°C)
RV4700 100MHz
Parameter
RV4700 133MHz
Min Max
Conditions
|IOUT|= 20uA
Min
Max
VOL
VOH
VOL
VOH
VIL
—
0.1V
—
—
0.1V
—
VCC - 0.1V
—
VCC - 0.1V
—
0.4V
—
0.4V
—
|IOUT|= 4mA
2.4V
–0.5V
0.7VCC
—
2.4V
–0.5V
0.7VCC
—
0.2VCC
VCC + 0.5V
±10uA
15pF
0.2VCC
VCC + 0.5V
±10uA
15pF
—
VIH
—
IIN
0 ≤ VIN ≤ VCC
CIN
—
—
—
COUT
I/OLEAK
—
15pF
—
15pF
—
—
20uA
—
20uA
Input/Output Leakage
RV4700 150MHz
RV4700 175MHz
Min Max
RV4700 200MHz
Parameter
Conditions
|IOUT|= 20uA
Min
Max
Min
Max
VOL
VOH
VOL
VOH
VIL
—
0.1V
—
—
0.1V
—
—
0.1V
—
VCC- 0.1V
—
VCC - 0.1V
—
VCC - 0.1V
—
0.4V
—
0.4V
—
0.4V
—
|IOUT|= 4mA
2.4V
–0.5V
0.7VCC
—
2.4V
–0.5V
0.7VCC
—
2.4V
–0.5V
0.7VCC
—
0.2VCC
VCC + 0.5V
±10uA
15pF
0.2VCC
VCC + 0.5V
±10uA
15pF
0.2VCC
VCC + 0.5V
±10uA
15pF
—
VIH
—
IIN
0 ≤ VIN ≤ VCC
CIN
—
—
—
—
COUT
I/OLEAK
—
15pF
—
15pF
—
15pF
—
—
20uA
—
20uA
—
20uA
Input/Output Leakage
16 of 25
April 10, 2001
IDT79R4700
System Interface Parameters—RV4700
Note: Operation of the R4700 is only guaranteed with the Phase Lock Loop enabled.
RV4700
100MHz
RV4700
133MHz
RV4700
150MHz
Parameter
Symbol
Test Conditions
Units
Min Max Min Max Min Max
Data Output1
tDM= Min
tDO = Max
mode14..13 = 10 (fastest)
mode14..13 = 01 (slowest)
trise = 3ns
0
9
0
9
0
8
ns
ns
ns
ns
0
15
—
—
0
12
—
—
0
12
—
—
Input Data Setup
tDS
tDH
3.5
1.5
3.5
1.5
3.5
1.5
tfall = 3ns
Input Data Hold
1.
Timings are measured from 1.5V of the clock to 1.5V of the signal.
RV4700
175MHz
RV4700
200MHz
Parameter
Data Output1
Symbol
Test Conditions
Units
Min Max Min Max
tDM= Min
DO = Max
mode14..13 = 10 (fastest)
mode14..13 = 01 (slowest)
0
8
0
8
ns
ns
ns
ns
t
0
12
—
—
0
12
—
—
Input ata Setup
tDS
tDH
trise = 3ns
tfall = 3ns
3.5
1.5
3.5
1.5
Input Data Hold
1.
Capacitive load for all output timings is 50pF.
Boot-Time Interface Parameters—RV4700
RV4700 100MHz RV4700 133MHz RV4700 150MHz
Min Max Min Max Min Max
Test
Conditions
Parameter
Symbol
Units
Mode Data Setup
Mode Data Hold
tDS
tDH
—
—
3
0
—
—
3
0
—
—
3
0
—
—
Master Clock Cycle
Master Clock Cycle
RV4700 175MHz
Min Max
RV4700 200MHz
Min Max
Test
Conditions
Parameter
Symbol
Units
Mode Data Setup
Mode Data Hold
tDS
tDH
—
—
3
0
—
—
3
0
—
—
Master Clock Cycle
Master Clock Cycle
17 of 25
April 10, 2001
IDT79R4700
Power Consumption—RV4700
RV4700 100MHz RV4700 133MHz RV4700 150MHz
Parameter
Conditions
—
Typical1
Max
Typical1
Max
Typical1
Max
System
Condition
100/25MHz
133/33MHz
150/38MHz
standby
—
—
125mA2
175mA2
875mA2
—
—
175mA2
225mA2
—
—
200mA2
250mA2
CL = 0pF3
CL = 50pF
575mA2
650mA2
650mA2
775mA2
1150mA2 875mA2
1375mA2 950mA2
1525mA4 950mA2
1300mA2 CL = 0pF, No SysAd activity3
ICC
active
1100mA2 850mA2
1275mA4 850mA2
1550mA2 CL = 50pF R4x00 compatible writes, TC = 25oC3
1725mA2 CL = 50pF Pipelined writes or write re-issue, TC = 25oC
1.
2.
3.
4.
Typical integer instruction mix and cache miss rates.
These are not tested. They are the result of engineering analysis and are provided for reference only.
Guaranteed by design.
These are the specifications IDT tests to insure compliance.
RV4700 175MHz
Typical1
Max
175/44MHz
RV4700 200MHz
Typical1
Max
200/50MHz
Parameter
Conditions
—
System Condition
standby
—
200mA2
250mA2
1500mA2
1800mA2
2000mA4
—
200mA2
250mA2
1500mA2
1800mA2
2000mA4
CL = 0pF3
CL = 50pF
—
—
1025mA2
1200mA2
1200mA2
1025mA2
1200mA2
1200mA2
CL = 0pF, No SysAd activity3
ICC
active
CL = 50pF R4x00 compatible writes, TC = 25oC3
CL = 50pF Pipelined writes or write re-issue, TC = 25oC
1.
2.
3.
4.
Typical integer instruction mix and cache miss rates.
These are not tested. They are the result of engineering analysis and are provided for reference only.
Guaranteed by design.
These are the specifications IDT tests to insure compliance.
18 of 25
April 10, 2001
IDT79R4700
RC4700 QFP Package Pin-Out
Note: N.C. pins should be left floating for maximum flexibility and compatibility with future designs.
Pin
Function
Pin
Function
Pin
Function
Pin
Function
1
2
3
4
5
6
7
8
9
N.C.
53
N.C.
105
N.C.
157
N.C.
N.C.
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
N.C.
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
N.C.
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
N.C.
VSS
SysCmd2
SysAD36
SysAD4
SysCmd1
VSS
N.C.
RClock0
RClock1
SyncOut
SysAD30
VCC
VCC
N.C.
SysAD45
SysAD13
Fault*
VCC
VSS
SysAD21
SysAD53
RdRdy*
ModeIn
SysAD22
SysAD54
VCC
SysAD44
VSS
VCC
VSS
SysAD35
SysAD3
SysCmd0
SysAD34
VSS
SysAD62
MasterOut
SysAD31
SysAD63
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VCC
SysAD12
SysCmdP
SysAD43
SysAD11
VSS
VCC
VSS
VSS
N.C.
Release*
SysAD23
SysAD55
NMI*
VCCOK
SysADC3
SysADC7
VCC
VCC
N.C.
SysCmd8
SysAD42
SysAD10
SysCmd7
VSS
SysAD2
Int5*
SysAD33
SysAD1
VSS
VCC
VSS
VSS
N.C.
SysADC2
SysADC6
VCC
N.C.
VCC
VCC
N.C.
SysAD41
SysAD9
SysCmd6
SysAD40
N.C.
Int4*
N.C.
SysAD32
SysAD0
Int3*
SysAD24
VCC
N.C.
VCCP
VSSP
N.C.
VSS
VSS
SysAD56
N.C.
N.C.
VCC
N.C.
VSS
Int2*
SysAD25
SysAD57
VCC
MasterClock
VCC
VCC
SysAD16
SysAD48
Int1*
SysAD8
SysCmd5
SysADC4
SysADC0
VSS
VSS
VSS
SyncIn
VCC
VSS
IOOut
VCC
SysAD26
SysAD58
IOIn
VSS
SysAD17
SysAD49
Int0*
N.C.
VCC
SysADC5
SysADC1
JTDI
SysCmd4
SysAD39
SysAD7
SysCMD3
VSS
VCC
SysAD18
VSS
VSS
SysAD27
SysAD59
ColdReset*
SysAD28
VCC
VCC
VCC
VSS
SysAD50
ValidIn*
SysAD19
SysAD51
VSS
SysAD47
SysAD15
JTDO
VCC
SysAD38
SysAD6
ModeClock
WrRdy*
SysAD37
SysAD5
VSS
VSS
SysAD46
VCC
SysAD60
Reset*
SysAD29
SysAD61
VCC
VCC
VSS
ValidOut*
SysAD20
SysAD52
ExtRqst*
N.C.
SysAD14
N.C.
TClock0
TClock1
N.C.
VCC
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
19 of 25
April 10, 2001
IDT79R4700
Physical Specifications — 208-pin QFP
20 of 25
April 10, 2001
IDT79R4700
Physical Specifications - page 2
21 of 25
April 10, 2001
IDT79R4700
RC4700 PGA Package Pin-Out
Note: N.C. pins should be left floating for maximum flexibility and compatibility with future designs.
Function
ColdReset*
Pin
T14
Function
SysAD36
Pin
Function
VCC
Pin
B18
C3
ExtRqst*
Fault*
U2
SysAD37
SysAD38
SysAD39
SysAD40
SysAD41
SysAD42
SysAD43
SysAD44
SysAD45
SysAD46
SysAD47
SysAD48
SysAD49
SysAD50
SysAD51
SysAD52
SysAD53
SysAD54
SysAD55
SysAD56
SysAD57
SysAD58
SysAD59
SysAD60
SysAD61
SysAD62
SysAD63
SysADC0
SysADC1
SysADC2
SysADC3
SysADC4
SysADC5
SysADC6
SysADC7
SysCmd0
SysCmd1
SysCmd2
SysCmd3
SysCmd4
SysCmd5
SysCmd6
SysCmd7
SysCmd8
SysCmdP
B3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C1
B16
U10
T9
C6
D18
F1
Reserved O (NC)
Reserved I (Vcc)
IOIn
C7
C10
C11
B13
A15
C15
B17
E17
F17
L2
G18
H1
T13
U12
N2
IOOut
J18
K1
Int0
Int1
L3
L18
M1
N18
R1
Int2
K3
Int3
J3
Int4
H3
Int5
F2
T18
U1
MasterClock
MasterOut
ModeClock
ModeIn
NMI
J17
P17
B4
M3
N3
V3
R2
V6
U4
T3
V8
U7
U3
V10
V12
V14
V17
A3
RClock0
RClock1
RdRdy*
Release
Reset*
T17
R16
T5
T6
T7
T10
T11
U13
V15
T15
U17
N16
N17
C8
V5
U16
J16
P16
J2
A6
SyncIn
A8
SyncOut
SysAD0
SysAD1
SysAD2
SysAD3
SysAD4
SysAD5
SysAD6
SysAD7
SysAD8
SysAD9
SysAD10
SysAD11
SysAD12
SysAD13
SysAD14
SysAD15
SysAD16
SysAD17
SysAD18
SysAD19
SysAD20
A10
A12
A14
A17
A18
B1
G2
E1
E3
C2
G17
T8
C4
C18
D1
B5
L16
B8
B6
F18
G1
B9
H16
U8
B11
C12
B14
B15
C16
D17
E18
K2
H18
J1
L17
E2
K18
L1
D3
B2
M18
N1
A5
B7
P18
R18
T1
C9
M2
P1
B10
B12
C13
C14
U18
V1
P3
T2
V2
22 of 25
April 10, 2001
IDT79R4700
Function
SysAD21
Pin
Function
TClock1
Pin
Function
VSS
Pin
T4
U5
U6
U9
C17
D16
M17
P2
V4
V7
V9
SysAD22
SysAD23
SysAD24
SysAD25
SysAD26
SysAD27
SysAD28
SysAD29
SysAD30
SysAD31
SysAD32
SysAD33
SysAD34
SysAD35
TClock0
VCCOk
ValidIn*
ValidOut*
WrRdy*
VCCP
VSS
VSS
VSS
VSS
VSS
VSS
JTMS
JTDO
JTDI
JTCK
V11
V13
V16
V18
E16
F16
G16
H17
U11
T12
U14
U15
T16
R17
M16
H2
R3
C5
K17
K16
A2
VSSP
VCC
VCC
A4
Reserved I (VCC)
VCC
A7
A9
G3
VCC
A11
A13
A16
F3
VCC
D2
VCC
23 of 25
April 10, 2001
IDT79R4700
Physical Specifications — PGA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
V
U
T
V
U
T
R
P
N
M
L
R
P
N
M
L
R4700
K
J
K
J
Pinout
Bottom
H
G
F
H
G
F
E
D
C
B
A
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
2884 drw 12
24 of 25
April 10, 2001
IDT79R4700
Ordering Information
YY
XXXX
999
A
A
IDT79
Configuration
Device
Type
Speed
Package
Process/
Temperature
Range
Blank
Commercial
(0°C to +85°C (Case))
GH
DP
PGA 179
208-Pin QFP
80
100
133
150
80 MHz
100 MHz
133 MHz
150 MHz
175
200
175 MHz
200 MHz
4700
Enhanced 64-bit CPU
RV
R
3.3V± 5%
5.0V± 5%
Valid Combinations
IDT79R4700 - 80, 100, 133 - GH, DP
PGA, QFP Package
PGA, QFP Package
IDT79RV4700 -100, 133, 150, 175, 200 - GH, DP
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-330-1748
for Tech Support:
email: rischelp@idt.com
phone: 408-492-8208
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
25 of 25
April 10, 2001
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