IDT79RV5000250G_技术文档

79RC5000

MULTI-ISSUE

64-BIT MICROPROCESSOR

◆

Large, efficient on-chip caches

–

32KB Instruction Cache, 32KB Data Cache

2-set associative in each cach

Virtually indexed and physically tagged to minimize cache

flushes

Write-back and write-through selectable on a per page basis

Critical word first cache miss processing

Supports back-to-back loads and stores in any combination at

full pipeline rate

◆

Dual issue super-scalar execution core

–

250 MHz frequency

Dual issue floating-point ALU operations with other instruction

classes

Traditional 5-stage pipeline, minimizes load and branch laten-

cies

–

◆

Single-cycle repeat rate for most floating point ALU

operations

◆

High-performance memory system

High level of performance for a variety of applications

–

Large primary caches integrated on-chip

Secondary cache control interface on-chip

High-frequency 64-bit bus interface runs up to 125MHz

Aggregate bandwidth of on-chip caches, system interface of

5.6GB/s

High-performance write protocols for graphics and data

communications

–

High-performance 64-bit integer unit achieves 330 dhrystone

MIPS (dhrystone 2.1)

Ultra high-performance floating-point accelerator, directly

implementing single- and double-precision operations

achieves 500mflops

–

Extremely large on-chip primary cache

On-chip secondary cache controller

◆

Compatible with a variety of operating systems

◆

MIPS-IV 64-bit ISA for improved computation

–

Windows™ CE

Numerous MIPS-compatible real-time operating systems

–

Compound floating-point operations for 3D graphics and

floating-point DSP

Conditional move operations

◆

Uses input system clock, with processor pipeline clock

multiplied by a factor of 2-8

–

◆

Large on-chip TLB

◆

Industrial and commercial temperature range

◆

Active power management, including use of WAIT operation

Phase Lock Loop

Instruction Set A

Instruction Select

Data Set A

Data Tag A

Store Buffer

DTLB Physical

SysAD

Integer Instruction Register

FP Instruction Register

Address Buffer

Instruction Tag A

ITLB Physical

Write Buffer

Read Buffer

Data Set B

DBus

Instruction Set B

IntIBus

Instruction Tag B

FPIBus

Control

AuxTag

Joint TLB

Tag

Load Aligner

Floating Point Register File

Unpacker/Packer

Integer Register File

Integer/Address Adder

Coprocessor 0

Data TLB Virtual

DVA

System/Memory

Control

Floating Point

MAdd,Add,Sub, Cvt

Div, SqRt

Shifter/Store Aligner

IVA

PC Incrementer

Branch Adder

Logic Unit

ABus

Instruction TLB Virtual

Program Counter

Integer Multiply, Divide

The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-

marks of Integrated Device Technology, Inc.

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April 10, 2001

DSC 5719

2001 Integrated Device Technology, Inc.

79RC5000

The RC5000 serves many performance critical embedded applica-

tions, such as high-end internetworking systems, color printers, and

graphics terminals.

The RC5000 implements the MIPS-IV 64-bit ISA, including CP1 and

CP1X functional units (and their instruction set).

The RC5000 is optimized for high-performance applications, with

special emphasis on system bandwidth and floating point operations,

through integration of high-performance computational units and a high-

performance memory hierarchy. For this class of application, the result

is a relatively low-cost CPU capable of approximately 330 Dhrystone

MIPS.

The RC5000 is a limited dual-issue machine that utilizes a traditional

5-stage integer pipeline. This basic integer pipeline of the RC5000 is

illustrated in Figure 1. The integer instruction execution speed is tabu-

lated (in number of pipeline clocks) as follows:

IDT’s objectives in offering the RC5000 include:

◆

Offering a high performance upgrade path to existing embedded

Load

2

1

customers in the internetworking, office automation and

visualization markets.

Store

2

1

◆

Providing a significant improvement in the floating- point

performance currently available in a moderately priced MIPS

CPU.

MULT/MULTU

DMULT/DMULTU

DIV/DIVU

DDIV/DDIVU

Other Integer ALU

Branch

8

12

36

68

1

12

36

68

1

◆

Providing improvements in the memory hierarchy of desktop

systems by using large primary caches and integrating a

secondary cache controller.

◆

Enabling improvements in performance through the use of the

MIPS-IV ISA.

2

Jump

2

Table 1 Integer Instruction Execution Speed

The RC5000 recognizes two general classes of instructions for multi-

issue:

The RC5000’s short pipeline keeps the load and branch latencies

very low. The caches contain special logic that allows any combination

of loads and stores to execute in back-to-back cycles without requiring

pipeline slips or stalls. (This assumes that the operation does not miss

in the cache.)

◆

Floating-point ALU

◆

All others

These instruction classes are pre-decoded by the RC5000, as they

are brought on-chip. The pre-decoded information is stored in the

instruction cache.

Assuming that there are no pending resource conflicts, the RC5000

can issue one instruction per class per pipeline clock cycle. Note that

this broad separation of classes insures that there are no data depen-

dencies to restrict multi-issue.

However, long-latency resources in either the floating-point ALU (e.g.

DIV or SQRT instructions) or instructions in the integer unit (such as

multiply) can restrict the issue of instructions. Note that the R5000 does

not perform out-of-order or speculative execution; instead, the pipeline

slips until the required resource becomes available.

There are no alignment restrictions on dual-issue instruction pairs.

The RC5000 fetches two instructions from the cache per cycle. Thus, for

optimal performance, compilers should attempt to align branch targets

to allow dual-issue on the first target cycle, since the instruction cache

only performs aligned fetches.

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April 10, 2001

79RC5000

I0

I1

I2

1I

2I

1R

1I

2R

2I

1A

1R

1I

2A

2R

2I

1D

1A

1R

2D

2A

2R

1W

1D

1A

2W

2D

2A

1W

1D

2W

2D

1

W

I3

I4

1I

2I

1R

1I

2R

2I

1A

1R

2A

2R

1D

1A

one cycle

Figure 1 R5000 Integer Pipeline Stages

Key to Figure

1I-1R

2I

Instruction cache access

Instruction virtual to physical address translation

Data cache access and load align

Data virtual to physical address translation

Virtual to physical address translation

Register file read

2A-2D

1D

1D-2D

2R

Bypass calculation

2R

Instruction decode

2R

Branch address calculation

Issue or slip decision

1A

1A-2A

1A

Integer add, logical, shift

Data virtual address calculation

Store align

2A

1A

Branch decision

2W

Register file write

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April 10, 2001

79RC5000

where P is the maximum power consumption at hot temperature,

calculated by using the maximum ICC specification for the device.

Typical values for CA at various airflows are shown in Table 1.

The RC5000 contains the following computational units:

Integer ALU. The RC5000 implements a full, single-cycle 64-bit ALU

for all integer ALU functions other than multiply and divide. Bypassing is

used to support back-to-back ALU operations at the full pipeline rate,

without requiring stalls for data dependencies.

CA

Airflow (ft/min)

PGA

0

200 400

600

3

800

2.5

1000

16

14

7

6

5

4

2

Integer Multiply/Divide Unit. This unit is separated from the primary

ALU, to allow these longer latency operations to run in parallel with other

operations. The pipeline stalls only if an attempt to access the HI or LO

registers is made before the operation completes.

BGA

3

Table 2 Thermal Resistance (ýCA) at Various Airflows

Note: The RC5000 implements advanced power manage-

ment to substantially reduce the average power dissipation of

the device. This operation is described in the IDT79RV5000

RISC Microprocessor Reference Manual.

Floating-point ALU. This unit is responsible for all CP1/CP1X ALU

operations other than DIV/SQRT. The unit is pipelined to allow a single-

cycle repeat rate for single-precision operations

Floating-point DIV/SQRT unit. This unit is separated from the other

floating-point ALU, so that these long latency operations do not prevent

the issue of other floating point operations.

Per the RC5000 Documentation errata, Revision 1.0, dated February

1999 and per the RC5000 Device errata, dated February 1999, mode

bits 20, 33 and 37 must be set to 1.

In addition, the RC5000 implements separate logical units to imple-

ment loads, stores, and branches.

The input clock operates in a frequency range of 33MHz to 100MHz.

The pipeline frequency for the RC5000 is 2 to 8 times the input clock (up

to the maximum for the speed grade of CPU).

January 1996: Corrected pin list for Clock/Control, Initialization, and

Secondary Cache interfaces in Pin Description section. Changed pins

AA19 and AA21 from Vcc to Vss in Advance Pin-Out section.

March 1997: Upgraded data sheet status from “Preliminary” to Final.

Added section on thermal considerations. Added section on absolute

maximum ratings.

The RC5000 utilizes special packaging techniques, to improve the

thermal properties of high-speed processors. The RC5000 is packaged

using cavity down packaging in a 223-pin PGA package with integral

thermal slug, and a 272-pin BGA package. These packages effectively

dissipate the power of the CPU, increasing device reliability.

June 1997: Revised Power Consumption and System Interface

Parameters.

September 1997: Added user notation on Boot Mode Bits 20 and 33

The RC5000 utilizes an all-aluminum package with the die attached

to a normal copper lead frame mounted to the aluminum casing. Due to

the heat-spreading effect of the aluminum, the package allows for an

efficient thermal transfer between the die and the case. The aluminum

offers less internal resistance from one end of the package to the other,

reducing the temperature gradient across the package and therefore

presenting a greater area for convection and conduction to the PCB for

a given temperature. Even nominal amounts of airflow will dramatically

reduce the junction temperature of the die, resulting in cooler operation.

for 200 MHz frequency.

June 1998: Added 250 MHz. Changed naming conventions.

June 1999: Added 267 MHz and 300 MHz.

October 28, 1999: Added industrial temperature data and revised

package designation code in the Ordering Information section.

March 23, 2000: Expanded the data presentation in the System

Interface Parameters table and revised the values in this table.

April 10, 2001: In the Data Output and Data Output Hold categories

of the System Interface Parameters table, changed values in the Min

column for all speeds from 1.5 and 1.0 to 0.

The RC5000 is guaranteed in a case temperature range of 0° to

+85° C. The type of package, speed (power) of the device, and airflow

conditions affect the equivalent ambient temperature conditions that will

meet this specification.

The equivalent allowable ambient temperature, TA, can be calculated

using the thermal resistance from case to ambient ( CA) of the given

package.

The following equation relates ambient and case temperatures:

TA = TC - P * CA

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79RC5000

64

8

2

SysAD(63:0)

SysADC(7:0)

SysCmd(8:0)

SysCmdP

ValidIn*

ScWord (1:0)

ScTCE*

9

ScTDE*

ScTOE*

ScCLR*

ValidOut*

ExtRqst*

ScDCE*

ScDOE*

Release*

RdRdy*

ScCWE*

ScLine (15:0)

16

WrRdy*

ScMATCH

ScVALID

RC5000

Logic

6

SysClock

VccP

Int (5:0)*

NMI*

Symbol

VssP

34

Vcc

Vss

BigEndian

ModeClock

ModeIN

VccOk

ColdReset*

Reset*

JTDI

JTDO

JTMS

JTCK

Figure 2 RC5000 Logic Symbol Diagram

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79RC5000

The RC5000 implements a bus similar to that of the RC4700. Table 2 lists and describes the RC5000 signals.

System interface

ExtRqst*

Release*

RdRdy*

WrRdy*

ValidIn*

Input

External Request.

Signals that the system interface needs to submit an external request.

Output Release Interface.

Signals that the processor is releasing the system interface to slave state

Input

Read Ready.

Signals that an external agent can now accept a processor read.

Write Ready.

Signals that an external agent can now accept a processor write request.

Valid Input.

Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the

SysCmd bus.

ValidOut*

Output Valid Output.

Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the

SysCmd bus.

SysAD(63:0)

Input/ System Address/Data bus.

Output A 64-bit address and data bus for communication between the processor and an external agent.

SysADC(7:0) Input/ System Address/Data check bus.

Output An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.

SysCmd(8:0) Input/ System Command/data identifier bus.

Output A 9-bit bus for command and data identifier transmission between the processor and an external agent.

SysCmdP

Input/ Reserved System Command/data identifier bus parity.

Output For the RC5000, unused on input and zero on output.

Clock/control interface

SysClock

Input

Master Clock.

Master clock input at the bus frequency. The pipeline clock is derived by multiplying this clock up.

VCCP

Quiet VCC for PLL.

Quiet VCC for the internal phase locked loop.

VSSP

Quiet VSS for PLL.

Quiet VSS for the internal phase locked loop.

Interrupt interface

Int(5:0)*

Input

Interrupt.

Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.

NMI*

Input

Non-maskable interrupt. Non-maskable interrupt, ORed with bit 6 of the interrupt register.

JTAG interface:

JTDI

Input

JTAG Data In.

Connected directly to JTDO. No JTAG implemented; should be pulled High.

JTCK

JTAG Clock Input.

Unused input; should be pulled High.

Table 3: RC5000 Signal Names and Descriptions (Page 1 of 2)

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April 10, 2001

79RC5000

JTDO

JTMS

Output JTAG Data Out.

Connected directly to JTDI. If no external scan used, this is a no connect.

Input

JTAG Command.

Unused input. Should be pulled High.

Initialization interface:

VCCOk

Input

VCC is OK.

When asserted, this signal indicates to the RC5000 that the power supply has been above Vcc minimum for more than100 milliseconds

and will remain stable. The assertion of VCCOk initiates the reading of the boot-time mode control serial stream.

ColdReset*

Reset*

Input

Cold Reset.

This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with SysClock.

Reset.

This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or syn chro-

nously to initiate a warm reset. Reset must be synchronously de-asserted with SysClock.

ModeClock

ModeIn

Output Boot Mode Clock.

Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six.

Input

Boot Mode Data In.

Serial boot-mode data input.

BigEndian

Input

Endian mode select.

Allows the system to change the processor addressing mode without rewriting the mode ROM. If endianness is to be specified by using

the BigEndian pin, program mode ROM bit 8 to 0; if endianness is to be specified by the mode ROM, ground the BigEndian pin.

Secondary cache interface:

ScCLR* Output Secondary Cache Block Clear.

Clears all valid bits in those Tag RAM’s which support this function.

ScCWE*(1:0) Output Secondary Cache Write Enable.

Asserted during writes to the secondary cache

ScDCE*(1:0)

ScDOE*

Output Data RAM Chip Enable.

Chip Enable for Secondary Cache Data RAM

Input

Data RAM Output Enable.

Asserted by the external agent to enable data onto the SysAD bus

ScLine (15:0) Output Data RAM Output Enable.

Cache line index for secondary cache

ScMATCH

ScTCE*

ScTDE*

ScTOE*

Input

Secondary cache Tag Match.

Asserted by Tag RAM on Secondary cache tag match

Output Secondary cache Tag RAM Chip Enable.

Chip enable for secondary cache tag RAM.

Output Secondary cache Tag RAM Data Enable.

Data Enable for Secondary Cache Tag RAM.

Output Secondary cache Tag RAM Output Enable.

Tag RAM Output enable for Secondary Cache Tag RAM’s

ScWord (1:0) Input/ Secondary cache Word Index.

Output Determines correct double-word of Secondary cache Index

ScValid

Input/ Secondary cache Valid.

Output Always driven by the CPU except during a cache probe operation, when it is driven by the tag RAM.

Table 3: RC5000 Signal Names and Descriptions (Page 2 of 2)

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April 10, 2001

79RC5000

Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

1

V

Terminal Voltage with respect to GND –0.5 to +4.6

–0.5 to +4.6

V

TERM

T

Operating Temperature (case)

Case Temperature Under Bias

Storage Temperature

0 to +85

-40 to +85

°C

mA

C

T

–55 to +125

BIAS

T

STG

2

3

I

DC Input Current

20

IN

4

5

I

DC Output Current

50

OUT

^1.IN minimum = –2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts.

^2..When VIN < 0V or VIN > VCC.

^3..When VIN < 0V or VIN > VCC.

^4.Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.

^5.Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.

Commercial

Industrial

0°C to +85°C (Case)

0V

3.3V±5%

-40°C to +85°C (Case)

(V = 3.3V± 5%; T

= 0°C to +85°C for commercial or T

= -40°C to +85°C for industrial)

case

CC

case

Note: Boot Mode Bits 20, 33 and 37 must be set to “1” for all frequencies

Min

100

3

Max

180

—

Min

100

3

Max

200

—

100

30

Min

100

3

Max

250

—

125

30

Pipeline Clock Frequency

SysClock HIGH

PCLk

t

ns

SCHIGH

SysClock LOW

t

3

—

3

ns

SCLOW

SysClock Frequency

SysClock Period

33

11.1

—

90

33

10

—

33

8

MHz

ns

—

t

30

SCP

1

SysClock Rise Time

t

2.5

256

2

—

2

ns

SCRise

1

SysClock Fall Time

t

2

ns

SCFall

ModeClock Period

t

256

ns

ModeCKP

t

SCP

^1.Rise and Fall times are measured between 10% and 90%

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April 10, 2001

79RC5000

Min

Max

Min

Max

Min

Max

Load Derate

C

—

2

—

2

—

2

ns/25pF

LD

Note: 50 pf loading on external output signals

Min

Max

7

Min

Max

Min

Max

4.7

5

1

Data Output

t

= Max mode

= 10 (fastest, 100%)

= 11 (83%)

0

5

0

ns

DO

14..13

= Min

DM

1

mode

0

8

0

7

0

1

mode

= 00 (67%)

0

9

0

9

0

6

1

mode

= 01 (slowest, 50%)

= 10 (fastest)

= 11 (83%)

0

11

—

0

11

—

0

7

1

Data Output Hold

t

mode

0

—

DOH

0

= 00 (67%)

0

= 01 (slowest)

0

t

= 3ns

1.5

0.5

1.5

0.5

1.5

0.5

DS

rise

Data Input

t

fall

t

DH

^1.Guaranteed by design.

Min Max Min

Max Min

Max

—

Mode Data Setup

Mode Data Hold

t

—

4

0

—

4

0

—

4

0

ns

Master Clock Cycle

DS

t

—

DH

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April 10, 2001

79RC5000

(V = 3.3V± 5%; T

= 0°C to +85°C for commercial or T = -40°C to +85°C for industrial)

case

cc

case

Min

Max

0.1V

—

Min

Max

0.1V

—

Min

Max

0.1V

—

VOL

VOH

—

|IOUT|= 20uA

|IOUT|= 4mA

VCC

- 0.1V

VOL

VOH

VIL

—

0.4V

—

0.4V

—

0.4V

—

2.4V

–0.5V

—

2.4V

—

2.4V

0.2VCC –0.5V

0.2VCC

—

VIH

0.7VCC VCC +

0.5V

0.7VCC VCC +

0.5V

0.7VCC VCC +

0.5V

IIN

—

±10uA

10pF

20uA

—

±10uA

10pF

20uA

—

±10uA 0 ≤ VIN ≤ VCC

CIN

10pF

20uA

—

CIO

Cclk

I/OLEAK

Input/Output Leakage

Max

System Condition

180/45MHz

120mA

200/50MHz

120mA

250/62.5MHz

120mA C = 50 pF

L

—

I

Standby

Active

cc

1100mA

1300mA

1800mA

C = 50pF

L

Pipelined writes or write re-issue

o

T = 25 C

c

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April 10, 2001

79RC5000

The RC5000 is available in two packages, the 223-pin CPGA and the 272-ball SBGA. The 223-pin CPGA package is shown in Figure 2 and Table

3; information on the SBGA package is shown in Figure 3 and Table 4.

V

U

T

R

P

N

M

L

K

223-Pin CPGA

J

H

G

F

E

D

C

B

A

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18

Figure 3 RC5000 223-pin CPGA Pin Orientation (Bottom View)

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April 10, 2001

79RC5000

A2

Vcc

C5

SysADC[6]

SysAD[16]

SysAD[50]

SysAD[22]

SysAD[24]

SysAD[28]

SysAD[62]

SysAD[44]

SysAD[10]

SysAD[38]

SysAD[4]

SysAD[34]

SysAD[2]

Vss

E18

F1

Vcc

K17

K18

L1

VssP

R6

SysAD[51]

SysAD[55]

SysAD[27]

SysAD[31]

SysAD[43]

SysAD[39]

SysAD[35]

SysAD[1]

ScWord[1]

ScLine[0]

ScLine[3]

ScLine[6]

Vss

U9

SysAD[63]

SysAD[13]

SysAD[11]

SysAD[9]

SysAD[37]

SysAD[3]

ScWord[0]

Vcc

A3

Vss

C6

Vcc

Vss

R7

U10

U11

U12

U13

U14

U15

U16

U17

U18

V1

A4

Vcc

C7

F2

Reserved

ScValid

INT[1]*

ScDCE[0]*

ScCWE[0]*

ScTDE*

Vss

R8

A5

Vss

C8

F3

L2

SysCmd[8]

SysCmd[7]

SysCmd[5]

ScLine[12]

ScLine[14]

ScLine[15]

Vcc

R9

A6

Vss

C9

F4

L3

R10

R11

R12

R13

R14

R15

R16

R17

R18

T1

A7

Vcc

C10

C11

C12

C13

C14

C15

C16

C17

C18

D1

F15

F16

F17

F18

G1

L4

A8

Vss

L15

L16

L17

L18

M1

M2

M3

M4

M15

M16

M17

M18

N1

A9

Vcc

A10

A11

A12

A13

A14

A15

A16

A17

A18

B1

Vss

Vcc

Vss

G2

Reserved

ScCLR*

ScTCE*

ModeIn

Vcc

Vss

Vcc

G3

SysCmd[6]

SysCmd[4]

SysCmd[1]

ScLine[8]

ScLine[10]

ScLine[13]

Vss

V2

Vss

G4

V3

Vcc

Vss

G15

G16

G17

G18

H1

Vss

V4

Vss

Vcc

Vss

T2

SysAD[15]

SysAD[47]

SysAD[17]

SysAD[19]

SysAD[23]

SysAD[57]

SysAD[29]

Vcc

V5

Vss

D2I

D3

INT3*

T3

V6

Vcc

Vss

INT5*

T4

V7

Vss

D4

Release*

Vcc

T5

V8

Vcc

B2

Vss

D5

H2

Reserved

VccOK

ModeClock

SysClock

Vss

T6

V9

Vss

B3

Vcc

D6

SysADC[2]

SysAD[48]

SysAD[52]

SysAD[56]

SysAD[60]

SysAD[14]

SysAD[42]

SysAD[8]

SysAD[36]

ColdReset*

SysAD[0]

ScTOE*

Vcc

H3

N2

SysCmd[3]

SysCmd[2]

SysADC[7]

ScLine[5]

ScLine[7]

ScLine[11]

Vcc

T7

V10

V11

V12

V13

V14

V15

V16

V17

V18

Vcc

B4

SysADC[4]

SysADC[0]

SysAD[18

SysAD[20]

SysAD[54]

SysAD[26]

0SysAD[58]

SysAD[30]

SysAD[46]

SysAD[12]

SysAD[40]

SysAD[6]

Vss

D7

H4

N3

T8

Vss

B5

D8

H15

H16

H17

H18

J1

N4

T9

Vcc

B6]

B7]

B8

D9

N15

N16

N17

N18

P1

T10

T11

T12

T13

T14

T15

T16

T17

T18

U1

SysAD[45]

SysAD[41]

SysAD[7]

SysAD[5]

SysAD[33]

Reset*

Vss

D10

D11

D12S

D13

D14

D15

D16

D17

D18

E1

Vcc

Vss

B9

Vss

B10

B11

B12

B13

B14

B15

B16

B17

B18

C1

J2

WrRdy*

ValidIn*

ExtReq*

JTDO

Vcc

J3

P2

SysCmd[0]

SysCmdP

SysADC[1]

ScLine[2]

ScLine[4]

ScLine[9]

Vss

J4

P3

ScLine[1]

Vcc

J15

J16

J17

J18

K1

P4

JTDI

P15

P16

P17

P18

R1

Vcc

JTCK

Vcc

Vss

Vcc

U2

Vcc

E2

INT[0]*

Vcc

U3

Vss

Vcc

E3

INT[2]*

K2

ScMatch

RdRdy*

cDOE*

JTMS

Vcc

U4

SysAD[21]

SysAD[53]

SysAD[25]

SysAD[59]

SysAD[61]

Vcc

E4

NT[4]*

K3

R2

SysADC[5]

SysADC[3]

BigEndian

SysAD[49]

U5

C2

Vcc

E15

E16

E17

SysAD[32]

ScDCE[1]*

ScCWE[1]*

K4S

K15

K16

R3

U6

C3

ValidOut*

NMI*

R4

U7

C4

VccP

R5

U8

12 of 15

April 10, 2001

79RC5000

21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

272-Ball SBGA

M

N

P

R

T

U

V

W

Y

AA

Figure 4 Ball Grid Array Package (Bottom View)

13 of 15

April 10, 2001

79RC5000

Pkg Pin Function

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

A1

Vss

B5

SysAD0

ScTOE*

ScCLR*

ScTDE*

D9

Vss

J2

SysAD46

SysAD14

Vss

P21

R1

SysAD55

Vss

W1

Vss

Vcc

B6

D10

D11

D12

Vcc

J3

W2

Vcc

Vss

B7

Vccp

J4

R2

SysAD18

SysAD48

Vcc

W3

Vcc

ValidOut*

Vss

B8

Vcc

J18

J19

J20

J21

K1

Vss

R3

W4

Vcc

B9

ModeClock D13

Vss

SysAD9

SysAD41

Vss

R4

W5

Int*5

Int*0

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

C1

JTDI

D14

D15

D16

D17

D18

D19

D20

D21

E1

Vcc

R18

R19

R20

R21

T1

Vcc

W6

Int*4

Vss

JTCK

N/C

Vcc

SysAD53

SysAD23

Vss

W7

Int*1

Reserved

Vss

SysAD60

SysAD30

SysAD62

Vcc

W8

Reserved

ValidIn*

ScDOE*

SysCmd7

SysCmd4

SysCmd1

SysADC7

SysADC5

SysAD47

BigEndian

Vcc

ScLine14

ScLine10

ScLine9

ScLine6

ScLine3

ScLine1

Vcc

K2

W9

WrRdy*

Vss

K3

SysAD16

SysADC0

SysADC2

Vss

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

Y1

Vcc

K4

T2

ScMatch

Vss

Vcc

K18

K19

K20

K21

L1

Vcc

T3

Vcc

SysAD11

SysAD43

SysAD13

Vss

T4

SysCmd6

Vss

T18

T19

T20

T21

U1

Vss

E2

SysAD36

SysAD4

Vcc

SysAD19

SysAD51

SysAD21

Vss

SysCmd2

Vss

Vcc

E3

Vcc

E4

L2

SysAD58

SysAD28

Vcc

SysADC3

Vss

E18

E19

Vcc

L3

C2

Vcc

ScWord1

ScWord0

Vss

L4

U2

SysADC4

SysADC6

Vcc

C3

ColdReset* E20

L18

L19

L20

L21

M1

M2

M3

M4

M18

M19

M20

M21

N1

Vcc

U3

Vss

C4

SysAD34

ScDCE*1

ScDCE*0

ScCWE*0

ScTCE*

ModeIn

JTDO

Vssp

E21

F1

SysAD45

SysAD63

Vss

U4

Vss

C5

SysAD8

SysAD38

SysAD6

Vss

U18

U19

U20

U21

V1

Vcc

A2

Vcc

C6

F2

SysAD17

SysAD49

Vss

Y2

Vcc

A3

Vss

C7

F3

SysAD26

SysAD56

SysAD24

Vcc

Y3

Vcc

A4

SysAD32

Vss

C8

F4

Y4

Release*

Int*3

A5

C9

F18

F19

F20

F21

G1

Vss

Vcc

Y5

A6

ScCWE*1

Vss

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

D1

SysAD1

SysAD33

SysAD3

Vss

V2

Vcc

Y6

Int*2

A7

Vcc

V3

Vcc

Y7

ScValid

Reserved

ExtRqst*

RdRdy*

SysCmd8

SysCmd5

SysCmd3

SysCmd0

SysCmdP

SysADC1

SysAD15

Vcc

A8

VCCOK

Vss

JTMS

SysAD29

SysAd61

SysAD31

Vss

V4

Vss

Y8

A9

ScLine13

ScLine11

ScLine8

ScLine5

ScLine4

ScLine0

Reset*

Vcc

V5

NMI*

Vss

Y9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

B1

MasterClk

Vss

G2

SysAD10

SysAD40

Vcc

V6

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

G3

V7

Vcc

ScLine15

Vss

G4

N2

SysAD54

SysAD22

Vss

V8

Vcc

G18

G19

G20

G21

H1

Vcc

N3

V9

Vss

ScLine12

Vss

SysAD35

SysAD5

Vss

N4

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

Vcc

N18

N19

N20

N21

P1

Vss

Vcc

ScLine7

Vss

SysAD27

SysAD59

Vss

Vcc

Vss

SysAD42

SysAD44

SysAD12

Vcc

Vss

ScLine2

Vss

Vcc

H2

Vcc

D2

Vcc

H3

SysAD50

SysAD52

SysAD20

Vcc

D3

Vcc

H4

P2

Vss

D4

Vss

H18

H19

H20

H21

J1

Vcc

P3

Vcc

D5

Vcc

SysAD7

SysAD39

SysAD37

Vss

P4

Vss

B2

Vcc

D6

Vss

P18

P19

P20

Vcc

B3

Vcc

D7

Vcc

SysAD25

SysAD57

Vcc

B4

SysAD2

D8

Vcc

14 of 15

April 10, 2001

79RC5000

IDT79

YY

XXXX

999

A

Operating

Voltage

Device

Type

Speed

Package

Temp range/

Process

Blank Commercial Temperature

(0°C to +85°C Case)

Industrial Temperature

(-40°C to +85°C Case)

I

G

223-ball CPGA

BS272 272-ball SBGA

180 MHz Pipeline

200 MHz Pipeline

250 MHz Pipeline

180

200

250

5000 Multi-Issue

64-bit Microprocessor

RV

3.3+/-5%

IDT79RV5000 - 180, 200MHz

IDT79RV5000 - 180, 200, 250MHz

IDT79RV5000 - 180, 200MHz

G

CPGA package

SBGA package

BS272

BS272 I

CORPORATE HEADQUARTERS

2975 Stender Way

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-330-1748

for Tech Support:

email: rischelp@idt.com

phone: 408-492-8208

www.idt.com

The IDT logo is a registered trademark of Integrated DeviceTechnology, Inc.

15 of 15

April 10, 2001


型号：	IDT79RV5000250G
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	MULTI-ISSUE 64-BIT MICROPROCESSOR 多种64位微处理器微处理器
文件：	总15页 (文件大小：289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT79RV5000250G [IDT]

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