IDT82V1074PF [IDT]

CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT (RSLIC) & QUAD PROGRAMMABLE PCM CODEC; 芯片组振铃用户线接口电路( RSLIC )和四通道可编程PCM编解码器
IDT82V1074PF
型号: IDT82V1074PF
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT (RSLIC) & QUAD PROGRAMMABLE PCM CODEC
芯片组振铃用户线接口电路( RSLIC )和四通道可编程PCM编解码器

解码器 编解码器 PC
文件: 总107页 (文件大小:1109K)
中文:  中文翻译
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CHIPSET OF RINGING SUBSCRIBER  
LINE INTERFACE CIRCUIT (RSLIC) &  
QUAD PROGRAMMABLE PCM CODEC  
IDT82V1671 (RSLIC)  
IDT82V1074 (CODEC)  
FEATURES  
DESCRIPTION  
Programmable DC feeding characteristics  
Programmable digital filters adapting to different requirements:  
Impedance matching  
The RSLIC-CODEC chipset is comprised of one four-channel  
programmable PCM CODEC (IDT82V1074) and four single-channel  
ringing SLICs (IDT82V1671). The chipset provides a total solution for  
line card designs. In addition to providing a complete software  
programmable solution for BORSCHT, additional functions such as FSK  
generator, Universal Tone Detection (UTD) unit, tone generators, ringing  
generator, Integrated Test and Diagnosis Functions (ITDF), line polarity  
reversal and three-party conference are integrated in to the chipset. The  
high integration of system functions reduces board space requirements  
of the line card and saves cost.  
Transhybrid balance  
Transmit and receive gain adjustment  
Frequency response correction  
Off-hook and ground-key detection  
AC/DC ring trip detection  
Programmable internal balanced ringing without external  
components  
Supports external ringing  
The chipset is fully programmable via a Microprocessor Interface  
(MPI) or a General Circuit Interface (GCI). In both MPI and GCI modes,  
the chipset supports A/µ-law companding format or linear data format.  
Programmable digital filters on the chipset provide the necessary  
transmit and receive filtering to realize impedance matching, transhybrid  
balance, frequency response correction and transmit/receive gains  
adjustment. The full programmability optimizes the performance of line  
card products and allows one line card to adapt to different requirements  
worldwide.  
The powerful Integrated Test and Diagnosis Functions (ITDF)  
accomplish necessary tests and measurements without external test  
equipment or relays. This brings convenience to system maintenance  
and diagnosis.  
Selectable MPI and GCI interfaces  
Supports A/µ-law compressed and linear data formats  
Programmable IO pins with relay-driving or analog input  
capability  
Line polarity reversal  
Integrated FSK generator for sending Caller ID information  
On-hook transmission  
2 programmable tone generators per channel  
Integrated Universal Tone Detection (UTD) unit for fax/modem  
tone detection  
Integrated Test and Diagnosis Functions (ITDF)  
Three-party conference  
Only battery and 3.3 V power supply needed  
Package available:  
This chipset can be used in digital telecommunication applications  
such as VoIP, VoATM, PBX, CO and DLC etc.  
IDT82V1671: 28 pin PLCC  
IDT82V1074: 100 pin TQFP  
CHIPSET FUNCTIONAL BLOCK DIAGRAM  
CODEC  
RSLIC  
1#  
Protection  
Circuit  
Level  
Telephone  
Telephone  
Telephone  
Metering  
MPI  
Interface  
Microprocessor  
PCM/GCI  
Off-hook  
Detection  
Protection  
Circuit  
RSLIC  
2#  
DC Feed  
DSP  
PCM/GCI  
Interface  
Protection  
Circuit  
RSLIC  
3#  
Filtering  
Self Test  
CID  
Protection  
Circuit  
RSLIC  
4#  
UTD  
Telephone  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
FEBRUARY 16, 2004  
INDUSTRIAL TEMPERATURE RANGE  
1
DSC-6042/3  
2003 Integrated Device Technology, Inc.  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
RSLIC FUNCTIONAL BLOCK DIAGRAM  
VBL VBH  
VCM  
VDD  
GND  
IL  
Sense  
VL  
Battery  
Switch  
VTDC  
VTAC  
CA  
IT  
Sense  
TIS  
TIP  
Line  
Driver  
ACN  
ACP  
DCN  
DCP  
RING  
RIS  
Input  
Stage  
CS  
RSP  
RSN  
Ring  
Trip  
Logic  
Control  
M1  
M2  
M3  
RT  
2
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
CODEC FUNCTIONAL BLOCK DIAGRAM  
MPI/GCI INT/INT RESET  
Channel1 for AC  
Channel1 for DC  
Filter and A/D for AC  
VTAC1  
General Control  
Logic  
VTDC1  
Filter and A/D for DC  
ACP1  
ACN1  
D/A and Filter for AC  
SLIC Signaling  
DCP1  
DCN1  
4 I/Os  
CS1  
D/A and Filter for DC  
Channel2 for AC  
Channel3 for AC  
Channel4 for AC  
Channel2 for DC  
Channel3 for DC  
Channel4 for DC  
DSP CORE  
PLL and Clock  
Generation  
DR1/DD  
DR2  
MCLK  
M1  
MPI Interface  
PCM/GCI Interface  
DX1/DU  
SLIC Interface  
Control  
M2  
M3  
DX2  
CI/S1 CO FSC BCLK/DCL  
CCLK/S0 CS  
TSX1 TSX2  
3
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
TABLE OF CONTENTS  
1
2
3
Pin Configurations.............................................................................................................................................................................................9  
1.1 RSLIC Pin Configuration ...........................................................................................................................................................................9  
1.2 CODEC Pin Configuration.......................................................................................................................................................................10  
Pin Descriptions...............................................................................................................................................................................................11  
2.1 RSLIC Pin Description.............................................................................................................................................................................11  
2.2 CODEC Pin Description ..........................................................................................................................................................................12  
Functional Description ....................................................................................................................................................................................16  
3.1 Functions Overview.................................................................................................................................................................................16  
3.1.1 Basic Functions..........................................................................................................................................................................16  
3.1.2 Additional Functions...................................................................................................................................................................16  
3.1.3 Programmable Functions ...........................................................................................................................................................16  
3.2 DC Feeding .............................................................................................................................................................................................17  
3.2.1 DC Feeding Characteristic Zones ..............................................................................................................................................17  
3.2.2 Constant Current Zone...............................................................................................................................................................17  
3.2.3 Resistive Zone............................................................................................................................................................................17  
3.2.4 Constant Voltage Zone...............................................................................................................................................................17  
3.2.5 DC Feeding Characteristics Configuration .................................................................................................................................18  
3.3 Speech Processing..................................................................................................................................................................................20  
3.3.1 AC Transmission........................................................................................................................................................................20  
3.3.1.1 Transmit Path ............................................................................................................................................................20  
3.3.1.2 Receive Path ..............................................................................................................................................................21  
3.3.2 Programmable Filters .................................................................................................................................................................21  
3.3.2.1 Impedance Matching ..................................................................................................................................................21  
3.3.2.2 Transhybrid Balance...................................................................................................................................................22  
3.3.2.3 Frequency Response Correction................................................................................................................................22  
3.3.2.4 Gain Adjustment.........................................................................................................................................................22  
3.4 Ring and Ring Trip...................................................................................................................................................................................23  
3.4.1 Internal Ringing Mode ................................................................................................................................................................23  
3.4.1.1 Internal Ringing Generation........................................................................................................................................23  
3.4.1.2 Ring Trip Detection In Internal Ringing Mode.............................................................................................................23  
3.4.2 External Ringing Mode...............................................................................................................................................................24  
3.4.2.1 Ring Trip Detection In External Ringing Mode............................................................................................................25  
3.5 Supervision..............................................................................................................................................................................................27  
3.5.1 Off-hook Detection .....................................................................................................................................................................27  
3.5.2 Ground-Key Detection................................................................................................................................................................29  
3.6 Metering by Polarity Reversal..................................................................................................................................................................29  
3.7 Enhanced Signal Processing...................................................................................................................................................................30  
3.7.1 Tone Generator..........................................................................................................................................................................30  
3.7.1.1 DTMF Generation.......................................................................................................................................................30  
3.7.2 FSK Generation for Caller ID .....................................................................................................................................................30  
3.7.3 Universal Tone Detection (UTD) ................................................................................................................................................34  
3.7.3.1 Introduction.................................................................................................................................................................34  
3.7.3.2 UTD Principle .............................................................................................................................................................34  
3.7.3.3 UTD Programming......................................................................................................................................................36  
3.8 Three-Party Conference..........................................................................................................................................................................37  
3.8.1 Introduction.................................................................................................................................................................................37  
3.8.2 PCM Interface Configuration ......................................................................................................................................................37  
3.8.3 Control the Active PCM Channels..............................................................................................................................................38  
3.9 ITDF.........................................................................................................................................................................................................40  
3.9.1 Introduction.................................................................................................................................................................................40  
3.9.2 Diagnosis and Test Functions ....................................................................................................................................................40  
3.9.3 Integrated Signal Generators .....................................................................................................................................................40  
3.9.4 Level Meter.................................................................................................................................................................................40  
3.9.4.1 Level Meter Source Selection.....................................................................................................................................40  
4
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
3.9.4.2 Level Meter Gain Filter and Rectifier..........................................................................................................................41  
3.9.4.3 Level Meter Integrator ................................................................................................................................................42  
3.9.4.4 Level Meter Result Register .......................................................................................................................................43  
3.9.4.5 Level Meter Shift Factor .............................................................................................................................................43  
3.9.4.6 Level Meter Threshold Setting....................................................................................................................................43  
3.9.5 Measurement via AC Level Meter ..............................................................................................................................................45  
3.9.5.1 Current Measurement via VTAC.................................................................................................................................45  
3.9.5.2 AC Level Meter Operational State Flow .....................................................................................................................45  
3.9.6 Measurement via DC Level Meter..............................................................................................................................................45  
3.9.6.1 Offset Current Measurement ......................................................................................................................................45  
3.9.6.2 Leakage Current Measurement..................................................................................................................................45  
3.9.6.3 Loop Resistance Measurement..................................................................................................................................46  
3.9.6.4 Line Resistance Tip/GND and Ring/GND...................................................................................................................46  
3.9.6.5 Capacitance Measurement.........................................................................................................................................47  
3.9.6.6 Voltage Measurement ................................................................................................................................................48  
3.9.6.7 Voltage Offset Measurement......................................................................................................................................49  
3.9.6.8 Ring Trip Operational Amplifier Offset Measurement.................................................................................................49  
4
Interface ............................................................................................................................................................................................................50  
4.1 PCM/MPI Interface ..................................................................................................................................................................................50  
4.1.1 MPI Control Interface .................................................................................................................................................................50  
4.1.2 PCM Interface ............................................................................................................................................................................51  
4.1.2.1 PCM Clock Configuration ...........................................................................................................................................51  
4.1.2.2 Time Slot Assignment.................................................................................................................................................52  
4.1.2.3 PCM Highway Selection .............................................................................................................................................52  
4.2 GCI Interface ...........................................................................................................................................................................................52  
4.2.1 Compressed GCI Mode..............................................................................................................................................................52  
4.2.2 Linear GCI Mode........................................................................................................................................................................52  
4.2.3 Command/Indication (C/I) Channel ............................................................................................................................................55  
4.2.3.1 Downstream C/I Channel Byte ...................................................................................................................................55  
4.2.3.2 Upstream C/I Channel Byte........................................................................................................................................55  
4.2.4 GCI Monitor Transfer Protocol....................................................................................................................................................56  
4.2.4.1 Monitor Channel Operation ........................................................................................................................................56  
4.2.4.2 Monitor Handshake Procedure...................................................................................................................................56  
4.3 Analog POTS Interface............................................................................................................................................................................58  
4.4 RSLIC and CODEC Interface..................................................................................................................................................................58  
5
Programming....................................................................................................................................................................................................59  
5.1 Overview..................................................................................................................................................................................................59  
5.1.1 MPI Programming ......................................................................................................................................................................59  
5.1.1.1 Broadcast Mode for MPI Programming ......................................................................................................................59  
5.1.1.2 Identification Code for MPI Programming...................................................................................................................59  
5.1.2 GCI Programming ......................................................................................................................................................................59  
5.1.2.1 Program Start Byte for GCI Programming..................................................................................................................59  
5.1.2.2 Identification Command for GCI Programming...........................................................................................................59  
5.2 Register/RAM Commands.......................................................................................................................................................................59  
5.2.1 Register/RAM Command Format ...............................................................................................................................................59  
5.2.2 Addressing the Local Registers..................................................................................................................................................59  
5.2.3 Addressing the Global Registers................................................................................................................................................60  
5.2.4 Addressing the FSK-RAM ..........................................................................................................................................................60  
5.2.5 Addressing the Coe-RAM...........................................................................................................................................................61  
5.3 Registers Description ..............................................................................................................................................................................63  
5.3.1 Registers Overview ....................................................................................................................................................................63  
5.3.2 Global Registers List ..................................................................................................................................................................65  
5.3.3 Local Registers List....................................................................................................................................................................73  
5.4 Programming Examples ..........................................................................................................................................................................83  
5.4.1 Programming Examples for MPI Mode.......................................................................................................................................83  
5.4.1.1 Example of Programming the Local Registers via MPI ..............................................................................................83  
5
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
5.4.1.2 Example of Programming the Global Registers via MPI.............................................................................................84  
5.4.1.3 Example of Programming the Coefficient-RAM via MPI.............................................................................................84  
5.4.1.4 Example of Programming the FSK-RAM via MPI.......................................................................................................84  
5.4.2 Programming Examples for GCI Mode.......................................................................................................................................85  
5.4.2.1 Example of Programming the Local Registers via GCI ..............................................................................................85  
5.4.2.2 Example of Programming the Global Registers via GCI.............................................................................................85  
5.4.2.3 Example of Programming the Coefficient-RAM via GCI.............................................................................................85  
5.4.2.4 Example of Programming the FSK-RAM via GCI.......................................................................................................86  
6
Operational Description ..................................................................................................................................................................................87  
6.1 Operating Modes.....................................................................................................................................................................................87  
6.1.1 RSLIC Control Signaling ............................................................................................................................................................87  
6.1.2 RSLIC Operating Modes ............................................................................................................................................................89  
6.1.3 CODEC Operating Modes..........................................................................................................................................................89  
6.2 PLL Power Down.....................................................................................................................................................................................90  
6.3 Programmable I/Os of the CODEC .........................................................................................................................................................90  
6.4 Interrupt Handling....................................................................................................................................................................................91  
6.5 Signal Path and Test Loopbacks.............................................................................................................................................................91  
6.6 RSLIC Power On Sequence....................................................................................................................................................................93  
6.7 CODEC Power On Sequence .................................................................................................................................................................93  
6.8 Default State After Reset.........................................................................................................................................................................93  
6.8.1 Power-On Reset and Hardware Reset.......................................................................................................................................93  
6.8.2 Software Reset...........................................................................................................................................................................93  
7
Electrical Characteristics ................................................................................................................................................................................94  
7.1 RSLIC Electrical Characteristics..............................................................................................................................................................94  
7.1.1 RSLIC Absolute Maximum Ratings ............................................................................................................................................94  
7.1.2 RSLIC Recommended Operating Conditions.............................................................................................................................94  
7.1.3 RSLIC Thermal Information........................................................................................................................................................94  
7.1.4 RSLIC Power Consumption .......................................................................................................................................................94  
7.2 CODEC Electrical Characteristics ...........................................................................................................................................................95  
7.2.1 CODEC Absolute Maximum Ratings..........................................................................................................................................95  
7.2.2 CODEC Recommended Operating Conditions ..........................................................................................................................95  
7.2.3 CODEC Digital Interface ............................................................................................................................................................95  
7.2.4 CODEC Power Dissipation.........................................................................................................................................................95  
7.3 Chipset Transmission Characteristics .....................................................................................................................................................96  
7.3.1 Absolute Gain.............................................................................................................................................................................96  
7.3.2 Gain Tracking.............................................................................................................................................................................96  
7.3.3 Frequency Response .................................................................................................................................................................96  
7.3.4 Return Loss................................................................................................................................................................................96  
7.3.5 Group Delay ...............................................................................................................................................................................97  
7.3.6 Distortion ....................................................................................................................................................................................97  
7.3.7 Noise ..........................................................................................................................................................................................97  
7.3.8 Interchannel Crosstalk................................................................................................................................................................98  
7.4 CODEC Timing Characteristics...............................................................................................................................................................99  
7.4.1 Clock Timing...............................................................................................................................................................................99  
7.4.2 Microprocessor Interface Timing ..............................................................................................................................................100  
7.4.3 PCM Interface Timing...............................................................................................................................................................101  
7.4.4 GCI Interface Timing ................................................................................................................................................................103  
8
9
Application Circuits .......................................................................................................................................................................................104  
8.1 Application Circuit for the Internal Ringing Mode ..................................................................................................................................104  
8.2 Application Circuit for the External Ringing Mode .................................................................................................................................105  
Ordering Information .....................................................................................................................................................................................106  
6
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LIST OF FIGURES  
Figure - 1  
Figure - 2  
Figure - 3  
Figure - 4  
Figure - 5  
Figure - 6  
Figure - 7  
Figure - 8  
Figure - 9  
Line Circuit Functions Included in the RSLIC-CODEC Chipset ........................................................................................................ 16  
DC Feeding Zones ............................................................................................................................................................................ 17  
Constant Current Zone...................................................................................................................................................................... 17  
Resistive Zone................................................................................................................................................................................... 17  
Constant Voltage Zone...................................................................................................................................................................... 18  
DC Feeding Characteristics Configuration........................................................................................................................................ 18  
DC Feeding Configuration Example for Short Loop Applications...................................................................................................... 18  
Signal Paths for AC Transmission..................................................................................................................................................... 20  
Voice Signal Path of the CODEC...................................................................................................................................................... 20  
Figure - 10 Nyquist Diagram................................................................................................................................................................................ 21  
Figure - 11 Internal Balanced Ringing ................................................................................................................................................................. 23  
Figure - 12 External Ringing Synchronization ..................................................................................................................................................... 25  
Figure - 13 Hysteresis for Off-Hook Detection..................................................................................................................................................... 27  
Figure - 14 Debounce Filter for Off-hook/Ground-key Detection......................................................................................................................... 28  
Figure - 15 FSK Signal Transmission Sequence................................................................................................................................................. 31  
Figure - 16 Recommended Programming Flow Chart for FSK Generation......................................................................................................... 33  
Figure - 17 UTD Functional Diagram................................................................................................................................................................... 34  
Figure - 18 Example of UTD Recognition Timing ................................................................................................................................................ 35  
Figure - 19 Example of UTD Tone End Detection Timing ................................................................................................................................... 35  
Figure - 20 Conference Block Diagram ............................................................................................................................................................... 37  
Figure - 21 Level Meter Block Diagram ............................................................................................................................................................... 41  
Figure - 22 Continuous Measurement Sequence (AC & DC Level Meter) .......................................................................................................... 42  
Figure - 23 Single Measurement Sequence (AC & DC Level Meter) .................................................................................................................. 42  
Figure - 24 Example for Resistance Measurement ............................................................................................................................................. 46  
Figure - 25 Differential Resistance Measurement ............................................................................................................................................... 46  
Figure - 26 Capacitance Measurement ............................................................................................................................................................... 47  
Figure - 27 External Voltage Measurement Principle .......................................................................................................................................... 48  
Figure - 28 MPI Read Operation Timing.............................................................................................................................................................. 50  
Figure - 29 MPI Write Operation Timing.............................................................................................................................................................. 50  
Figure - 30 PCM Clock Slope Select Waveform.................................................................................................................................................. 51  
Figure - 31 Compressed GCI Frame Structure.................................................................................................................................................... 53  
Figure - 32 Linear GCI Frame Structure.............................................................................................................................................................. 54  
Figure - 33 Monitor Channel Operation ............................................................................................................................................................... 56  
Figure - 34 State Diagram of the Monitor Transmitter ......................................................................................................................................... 57  
Figure - 35 State Diagram of the Monitor Receiver ............................................................................................................................................. 58  
Figure - 36 Waveform of Programming Example: Writing to Local Registers ..................................................................................................... 83  
Figure - 37 Waveform of Programming Example: Reading Local Registers ....................................................................................................... 83  
Figure - 38 RSLIC Mode Control Signaling ......................................................................................................................................................... 87  
Figure - 39 RSLIC Control Timing Diagram......................................................................................................................................................... 88  
Figure - 40 RSLIC Internal Test Circuit................................................................................................................................................................ 89  
Figure - 41 IO Debounce Filter ............................................................................................................................................................................ 90  
Figure - 42 AC/DC Signal Path and Test Loopbacks .......................................................................................................................................... 92  
Figure - 43 Clock Timing...................................................................................................................................................................................... 99  
Figure - 44 MPI Input Timing ............................................................................................................................................................................. 100  
Figure - 45 MPI Output Timing .......................................................................................................................................................................... 100  
Figure - 46 PCM Interface Timing (Single Clock Mode) .................................................................................................................................... 101  
Figure - 47 PCM Interface Timing (Double Clock Mode)................................................................................................................................... 102  
Figure - 48 GCI Interface Timing ....................................................................................................................................................................... 103  
Figure - 49 Application Circuit for the Internal Ringing Mode ............................................................................................................................ 104  
Figure - 50 Application Circuit for the External Ringing Mode........................................................................................................................... 105  
7
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LIST OF TABLES  
Table - 1  
Table - 2  
Table - 3  
Table - 4  
Table - 5  
Table - 6  
Table - 7  
Table - 8  
Table - 9  
Table - 10  
Table - 11  
Table - 12  
Table - 13  
Table - 14  
Table - 15  
Table - 16  
Table - 17  
Table - 18  
Table - 19  
Table - 20  
Table - 21  
Table - 22  
Table - 23  
Table - 24  
Table - 25  
Table - 26  
Table - 27  
Table - 28  
Registers and Coe-RAM Locations Used for DC Feeding Configuration...........................................................................................19  
Registers and Coe-RAM Locations Used for Internal Ringing Mode .................................................................................................24  
Registers and Coe-RAM Locations Used for External Ringing Mode................................................................................................26  
Off-hook Detection in Different Modes ...............................................................................................................................................27  
Registers and Coe-RAM Locations Used for Off-hook Detection ......................................................................................................28  
Registers Used for Ground-key Detection..........................................................................................................................................29  
Registers and Coe-RAM Locations Used for Tone Generation .........................................................................................................30  
FSK Modulation Characteristics.........................................................................................................................................................31  
Registers and FSK-RAM Used for the FSK Generator ......................................................................................................................32  
Registers and Coe-RAM Locations Used for UTD.............................................................................................................................36  
Conference Mode...............................................................................................................................................................................38  
Active PCM Channel Configuration Bits.............................................................................................................................................38  
Level Meter Source Selection ............................................................................................................................................................40  
Level Meter Result Value Range........................................................................................................................................................43  
Shift Factor Selection .........................................................................................................................................................................43  
Level Meter Threshold Setting ...........................................................................................................................................................43  
Registers and Coe-RAM Locations Used for the Level Meter............................................................................................................44  
Registers and Coe-RAM Locations Used for Ramp Generator..........................................................................................................48  
Time Slot Selection For Compressed GCI .........................................................................................................................................53  
Time Slot Selection For Linear GCI....................................................................................................................................................54  
Local Register Addressing in MPI Mode ............................................................................................................................................60  
Local Register Addressing in GCI Mode ............................................................................................................................................60  
Coefficient RAM Mapping...................................................................................................................................................................62  
Global Registers Mapping..................................................................................................................................................................63  
Local Registers Mapping....................................................................................................................................................................64  
RSLIC Operating Mode......................................................................................................................................................................89  
Interrupt Source and Interrupt Mask...................................................................................................................................................91  
External Components in Application Circuits ...................................................................................................................................105  
8
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
1
PIN CONFIGURATIONS  
1.1  
RSLIC PIN CONFIGURATION  
5
6
25  
24  
23  
22  
21  
20  
19  
VCMB  
RSP  
RSN  
RT  
VDD  
AGND  
CF  
7
8
IDT82V1671  
VCM  
ACN  
ACP  
DCN  
9
CS  
10  
11  
M1  
M2  
9
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
1.2  
CODEC PIN CONFIGURATION  
81  
82  
83  
84  
85  
86  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
IO1_1  
IO2_1  
IO3_1  
IO4_1  
IOGND  
IO1_4  
IO2_4  
IO3_4  
IO4_4  
IOGND  
IO1_3  
IO2_3  
IO3_3  
IO4_3  
IO1_2  
IO2_2  
IO3_2  
87  
88  
89  
90  
91  
IO4_2  
IDT82V1074  
VDDA4  
RTIN4  
VL4  
ACN1  
ACP1  
DCN1  
CA2_1  
CA1_1  
DCP1  
AGND  
92  
93  
94  
95  
96  
97  
VTDC4  
VTAC4  
AGND  
DCP4  
CA1_4  
CA2_4  
DCN4  
ACP4  
VTAC1  
VTDC1  
VL1  
98  
99  
RTIN1  
100  
10  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
2
PIN DESCRIPTIONS  
2.1  
RSLIC PIN DESCRIPTION  
Name  
VBH  
Type  
Pin Number  
Description  
Power  
1
Negative battery supply (70 V VBH ≤ −52 V)  
Ring sense, connected to the RING pin through an external resistor RS. Refer to “8 Application Circuits” on page 104  
for details.  
RIS  
2
BGND  
TIS  
Power  
Power  
Power  
3
4
5
6
Battery ground. This pin should be externally connected to AGND.  
Tip sense, connected to the TIP pin through an external resistor RS.  
+3.3 V power supply.  
VDD  
AGND  
Analog ground. This pin should be externally connected to BGND.  
Output voltage of VBAT/2 (VBAT represents the selected battery voltage VBH or VBL). An external capacitor is  
connected between this pin and the ground for filtering.  
CF  
Ο
7
VCM  
ACN  
ACP  
DCN  
DCP  
VTAC  
I
I
8
Reference voltage input, typical 1.5 V.  
Differential AC voltage, negative.  
Differential AC voltage, positive.  
Differential DC voltage, negative.  
Differential DC voltage, positive.  
Sense transversal AC voltage.  
9
I
10  
11  
12  
13  
I
I
O
External capacitor connection. An external capacitor is connected between this pin and the CB pin to separate the DC  
component from the sense transversal voltage.  
CA  
14  
VTDC  
VL  
O
O
15  
16  
Sense transversal DC voltage.  
Sense longitudinal voltage.  
External capacitor connection. An external capacitor is connected between this pin and the CA pin to separate the DC  
component from the sense transversal voltage.  
CB  
M3  
17  
18  
Mode control input 3 or temperature information output.  
The logic level of the CS pin determines the direction of the M3 pin. See the description of the CS pin for details.  
I/O  
M2  
M1  
I
I
19  
20  
Mode control input 2. This is a binary logic pin, together with M1 and M3, controlling the operating mode of the RSLIC.  
Mode control input 1. This is a binary logic pin, together with M2 and M3, controlling the operating mode of the RSLIC.  
Chip select input. It is a ternary logic pin.  
When the CS pin is logic 0 (0 V< CS < 0.8 V), the RSLIC receives the mode control data from the CODEC through  
the M1 to M3 pins.  
CS  
I
21  
When the CS pin is logic 1 (2.2 V< CS < 3.3 V), the RSLIC sends the temperature information of itself to the  
CODEC through the M3 pin.  
When the CS pin is 1.5 V (with ±0.5 V tolerance), the RSLIC neither receives the data from the CODEC nor sends  
temperature information to it.  
RT  
RSN  
RSP  
VCMB  
RING  
TIP  
O
22  
23  
24  
25  
26  
27  
28  
Ring trip operational amplifier output.  
I
I
Negative ring trip operational amplifier input.  
Positive ring trip operational amplifier input.  
VCM buffer output, 1.5 V, used for external ringing mode.  
Subscriber loop connection Ring.  
O
I/O  
I/O  
Power  
Subscriber loop connection Tip.  
VBL  
Negative battery supply (52 V VBL ≤ −20 V).  
11  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
2.2  
CODEC PIN DESCRIPTION  
Name  
Type Pin Number  
Description  
VTDC1  
VTAC1  
VL1  
I
I
33  
34  
32  
31  
40  
41  
36  
39  
DC component of the transversal voltage (Channel 1).  
AC component of transversal voltage (Channel 1).  
Longitudinal voltage (Channel 1).  
I
RTIN1  
ACP1  
ACN1  
DCP1  
DCN1  
I
Analog voltage that can be used for external ring trip detection (channel 1).  
Differential AC voltage, positive (Channel 1).  
O
O
O
O
Differential AC voltage, negative (Channel 1).  
Differential DC voltage, positive (Channel 1).  
Differential DC voltage, negative (Channel 1).  
Ternary logic output 1, controlling the operating mode of the RSLIC1 (Channel 1).  
When the CS1 pin is logic 0 (0 V< CS1 < 0.8 V), the CODEC sends mode control data to the RSLIC1 through the M1 to M3  
pins.  
CS1  
O
52  
When the CS1 pin is logic 1 (2.2 V< CS1 < 3.3 V), the CODEC receives the temperature information of the RSLIC1 through  
the M3 pin.  
When the CS1 pin is 1.5 V (with ±0.5 V tolerance), no mode control data or temperature information is transferred between  
the CODEC and the RSLIC1.  
Programmable IO pin with relay-driving capability (Channel 1). In external ringing mode, the IO1_1 pin can be used to control  
the external ring relay.  
IO1_1  
I/O  
50  
IO2_1  
IO3_1  
IO4_1  
CA1_1  
CA2_1  
VTDC2  
VTAC2  
VL2  
I/O  
I/O  
I/O  
I/O  
I/O  
I
49  
48  
47  
37  
38  
21  
22  
20  
19  
28  
29  
24  
27  
Programmable IO pin with relay-driving capability (Channel 1).  
Programmable IO pin with analog input functionality (Channel 1).  
Programmable IO pin with analog input functionality (Channel 1).  
External capacitor connection. An external capacitor is connected between this pin and the DCP1 pin for filtering (Channel 1).  
External capacitor connection. An external capacitor is connected between this pin and the DCN1 pin for filtering (Channel 1).  
DC component of the transversal voltage (Channel 2).  
I
AC component of the transversal voltage (Channel 2).  
I
Longitudinal voltage (Channel 2).  
RTIN2  
ACP2  
ACN2  
DCP2  
DCN2  
I
Analog voltage that can be used for external ring trip detection (channel 2).  
Differential AC voltage, positive (Channel 2).  
O
O
O
O
Differential AC voltage, negative (Channel 2).  
Differential DC voltage, positive (Channel 2).  
Differential DC voltage, negative (Channel 2).  
Ternary logic output 2, controlling the operating mode of the RSLIC2 (Channel 2).  
When the CS2 pin is logic 0 (0 V< CS2 < 0.8 V), the CODEC sends mode control data to the RSLIC2 through the M1 to M3  
pins.  
CS2  
O
51  
When the CS2 pin is logic 1 (2.2 V< CS2 < 3.3 V), the CODEC receives the temperature information of the RSLIC2 through  
the M3 pin.  
When the CS2 pin is 1.5 V (with ±0.5 V tolerance), no mode control data or temperature information is transferred between  
the CODEC and the RSLIC2.  
Programmable IO pin with relay-driving capability (Channel 2). In external ringing mode, the IO1_2 pin can be used to control  
the external ring relay.  
IO1_2  
I/O  
45  
IO2_2  
IO3_2  
IO4_2  
CA1_2  
CA2_2  
I/O  
I/O  
I/O  
I/O  
I/O  
44  
43  
42  
25  
26  
Programmable IO pin with relay-driving capability (Channel 2).  
Programmable IO pin with analog input functionality (Channel 2).  
Programmable IO pin with analog input functionality (Channel 2).  
External capacitor connection. An external capacitor is connected between this pin and the DCP2 pin for filtering (Channel 2).  
External capacitor connection. An external capacitor is connected between this pin and the DCN2 pin for filtering (Channel 2).  
12  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Name  
VTDC3  
VTAC3  
VL3  
Type Pin Number  
Description  
I
I
5
6
DC component of the transversal voltage (Channel 3).  
AC component of the transversal voltage (Channel 3).  
Longitudinal voltage (Channel 3).  
I
4
RTIN3  
ACP3  
ACN3  
DCP3  
DCN3  
I
3
Analog voltage that can be used for external ring trip (channel 3).  
Differential AC voltage, positive (Channel 3).  
O
O
O
O
12  
13  
8
Differential AC voltage, negative (Channel 3).  
Differential DC voltage, positive (Channel 3).  
Differential DC voltage, negative (Channel 3).  
11  
Ternary logic output 3, controlling the operating mode of the RSLIC3 (Channel 3).  
When the CS3 pin is logic 0 (0 V< CS3 < 0.8 V), the CODEC sends mode control data to the RSLIC3 through the M1 to M3  
pins.  
CS3  
O
80  
When the CS3 pin is logic 1 (2.2 V< CS3 < 3.3 V), the CODEC receives the temperature information of the RSLIC3 through  
the M3 pin.  
When the CS3 pin is 1.5 V (with ±0.5 V tolerance), no mode control data or temperature information is transferred between  
the CODEC and the RSLIC3.  
Programmable IO pin with relay-driving capability (Channel 3). In external ringing mode, the IO1_3 pin can be used to control  
the external ring relay.  
IO1_3  
I/O  
86  
IO2_3  
IO3_3  
IO4_3  
CA1_3  
CA2_3  
VTDC4  
VTAC4  
VL4  
I/O  
I/O  
I/O  
I/O  
I/O  
I
87  
88  
89  
9
Programmable IO pin with relay-driving capability (Channel 3).  
Programmable IO pin with analog input functionality (Channel 3).  
Programmable IO pin with analog input functionality (Channel 3).  
External capacitor connection. An external capacitor is connected between this pin and the DCP3 pin for filtering (Channel 3).  
External capacitor connection. An external capacitor is connected between this pin and the DCN3 pin for filtering (Channel 3).  
DC component of the transversal voltage (Channel 4).  
10  
93  
94  
92  
91  
100  
1
I
AC component of the transversal voltage (Channel 4).  
I
Longitudinal voltage (Channel 4).  
RTIN4  
ACP4  
ACN4  
DCP4  
DCN4  
I
Analog voltage that can be used for external ring trip (Channel 4).  
Differential AC voltage, positive (Channel 4).  
O
O
O
O
Differential AC voltage, negative (Channel 4).  
96  
99  
Differential DC voltage, positive (Channel 4).  
Differential DC voltage, negative (Channel 4).  
Ternary logic output 4, controlling the operating mode of the RSLIC4 (Channel 4).  
When the CS4 pin is logic 0 (0 V< CS4 < 0.8 V), the CODEC sends mode control data to the RSLIC4 through the M1 to M3  
pins.  
CS4  
O
79  
When the CS4 pin is logic 1 (2.2 V< CS4 < 3.3 V), the CODEC receives the temperature information of the RSLIC4 through  
the M3 pin.  
When the CS4 pin is 1.5 V (with ±0.5 V tolerance), no mode control data or temperature information is transferred between  
the CODEC and the RSLIC4.  
Programmable IO pin with relay-driving capability (Channel 4). In external ringing mode, the IO1_4 pin can be used to control  
the external ring relay.  
IO1_4  
I/O  
81  
IO2_4  
IO3_4  
IO4_4  
CA1_4  
CA2_4  
I/O  
I/O  
I/O  
I/O  
I/O  
82  
83  
84  
97  
98  
Programmable IO pin with relay-driving capability (Channel 4).  
Programmable IO pin with analog input functionality (Channel 4).  
Programmable IO pin with analog input functionality (Channel 4).  
External capacitor connection. An external capacitor is connected between this pin and the DCP4 pin for filtering (Channel 4).  
External capacitor connection. An external capacitor is connected between this pin and the DCN4 pin for filtering (Channel 4).  
13  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Name  
M1  
Type Pin Number  
Description  
RSLIC operating mode control output 1. The M1to M3 pins together with the CSn pin (n = 1 to 4 for Channel 1 to 4 respectively)  
determine the operating mode of the RSLIC connected to Channel n of the CODEC. Refer to the description of the CSn pin for  
details.  
O
O
54  
55  
M2  
RSLIC operating mode control output 2. See the description of the M1 pin for details.  
RSLIC operating mode control output 3 or RSLIC temperature information input. The direction of this pin is determined by the  
logic level of the CSn pin (n = 1 to 4 for Channel 1 to 4 respectively):  
CSn = 0: M3 is an output pin. It, together with M1 and M2, carries the mode control data to RSLICn;  
CSn = 1: M3 is an input pin, carrying the temperature information of RSLICn to the CODEC.  
M3  
I/O  
56  
MPI/GCI  
I
I
60  
75  
Interface mode selection. Logic 0 selects MPI mode and logic 1 selects GCI mode.  
Frame Synchronization Clock for PCM or GCI interface. The FSC signal is 8 kHz, identifying the beginning of the PCM frame  
(MPI mode) or indicating the beginning of Time Slot 0 in GCI frame (GCI mode).  
FSC  
PCM Bit Clock (BCLK) for MPI mode or Data Clock (DCL) for GCI mode.  
In MPI mode, the PCM data is transferred between the CODEC and the PCM highway, following the BCLK. The BCLK is  
required to be synchronous to the FSC. The frequency of the BCLK can be from 256 kHz to 8.192 MHz in steps of 64 kHz.  
In GCI mode, the DCL is either 2.048 MHz or 4.096 MHz. The internal circuit of the CODEC automatically monitors this input to  
determine which frequency is being used.  
DCL/BCLK  
I
76  
Data Transmit PCM highway one (for MPI mode) or Data Upstream (for GCI mode).  
DX1/DU  
DR1/DD  
O
I
69  
70  
In MPI mode, the PCM data is transmitted to the PCM highway one (DX1) or two (DX2), following the BCLK.  
In GCI mode, the GCI data of all four channels is transmitted via the DU pin to the master device.  
Data Receive PCM highway one (for MPI mode) or Data Downstream (for GCI mode).  
In MPI mode, the PCM Data is received from PCM highway one (DR1) or two (DR2), following the BCLK.  
In GCI mode, the GCI data is received from the master device via the DD pin.  
TSX1  
TSX2  
DX2  
O
O
O
I
68  
72  
73  
74  
Transmit Indicator for PCM highway one, open drain. This pin becomes low when the data is transmitted via DX1.  
Transmit Indicator for PCM highway two, open drain. This pin becomes low when the data is transmitted via DX2.  
Data Transmit PCM highway two (for MPI mode). Refer to the description of the DX1 pin for details.  
Data Receive PCM highway two (for MPI mode). Refer to the description of the DR1 pin for details.  
DR2  
Control Clock (CCLK) for MPI mode or Time Slot Selection 0 (S0) for GCI mode.  
In MPI mode, the CCLK pin provides clock for the serial control interface. The frequency of the CCLK can be up to 8.192 MHz.  
In GCI mode, the S0 together with Time Slot Selection 1 (S1) determines which time slot is used to transmit the voice or control  
data.  
CCLK/S0  
I
62  
CO  
CI/S1  
CS  
O
I
64  
63  
61  
66  
Control Data Output (CO) for MPI mode.  
Control Data Input (CI) for MPI mode or Time Slot Selection 1 (S1) for GCI mode.Refer to the description of the S0 pin for  
details.  
I
CODEC Chip Selection signal for MPI mode, active low.  
Master Clock input. The MCLK pin provides the clock for the DSP of the CODEC. The frequency of the MCLK can be 1.536  
MHz, 1.544 MHz, 2.048 MHz, 3.072 MHz, 3.088 MHz, 4.096 MHz, 6.144 MHz, 6.176 MHz or 8.192 MHz.  
MCLK  
I
Interrupt output pin for MPI mode. The active level of this pin is programmable. If any of the active interrupts occurs, this pin will  
be set to active level, high or low. It is active low by default.  
INT/INT  
O
77  
VCM  
O
I
17  
67  
Reference voltage output. Typical 1.5 V.  
Reset signal input. Active low.  
RESET  
External Ringing Synchronization signal. In external ringing mode, the synchronization signal provided by the external ringer is  
applied to the CODEC via this pin. The external relay can be switched on or off by the IO1 pin synchronously following the  
RSYNC.  
RSYNC  
I
59  
TEST  
CNF  
I
57  
15  
Input pin for internal test purpose. This pin must be connected to the ground.  
External capacitor connection. An external capacitor is connected between this pin and the AGND for noise filtering.  
VDDA1  
VDDA2  
VDDA3  
VDDA4  
30  
18  
2
Power  
+3.3 V analog power supply.  
90  
VDDD  
VDDB  
Power  
Power  
71, 53  
16  
+3.3 V digital power supply.  
+3.3 V bias power supply.  
14  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Name  
Type Pin Number  
Description  
VDDIO  
Power  
Power  
Power  
78  
Power supply for IO pins.  
Analog ground.  
7, 14, 23,  
35, 95  
AGND  
DGND  
58, 65  
46, 85  
Digital ground.  
IOGND Power  
Ground for IO pins.  
15  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
signals, test tones, dial tones etc.  
3
FUNCTIONAL DESCRIPTION  
FSK generator  
The chipset provides a built-in FSK generator for sending Caller  
ID information.  
Universal Tone Detection (UTD)  
The chipset provides a built-in UTD unit per channel to detect  
special tones in the receive or transmit path (fax and modem  
tones, for example)  
Line polarity reversal  
The chipset supports teletax metering by reversing the polarity of  
the Tip/Ring voltage.  
3.1  
FUNCTIONS OVERVIEW  
3.1.1  
BASIC FUNCTIONS  
All BORSCHT functions are integrated in the RSLIC-CODEC  
chipset:  
Battery feeding  
The chipset provides programmable DC feeding characteristics.  
Over voltage protection  
Over voltage protection is realized by the RSLIC and additional  
protection circuits.  
Ringing  
3.1.3  
PROGRAMMABLE FUNCTIONS  
The RSLIC-CODEC chipset provides a highly flexible programmable  
solution for line card designs. By programming the corresponding  
registers or coefficient RAM in the CODEC, users can design one line  
card to meet different requirements worldwide. That means, adjusting  
the receive/transmit gain and the transhybrid balance can be realized by  
software with a single hardware design.  
The chipset supports both internal and external ringing modes.  
Supervision (signaling)  
The chipset supports off-hook and ground-key detection, DC and  
AC ring trip detection.  
Coding  
Supports A/µ-law compressed code and linear code.  
Hybrid  
Provides hybrid for 2/4-wire conversion.  
Testing  
Supports integrated test and diagnostic functions (ITDF).  
The chipset provides many programmable functions including:  
DC feeding characteristics  
Impedance matching  
Transhybrid balance  
Frequency response correction in transmit and receive paths  
Gain in transmit and receive paths  
Off-hook and ground-key detect threshold and debounce interval  
AC and DC ring trip thresholds  
Internal ringing frequency, amplitude and DC ringing offset voltage  
Analog and digital test loopbacks  
3.1.2  
ADDITIONAL FUNCTIONS  
Besides full BORSCHT functions, the following additional functions  
are also integrated in the RSLIC-CODEC chipset:  
Tone generators  
The CODEC provides two tone generators (TG1 & TG2) per  
channel. The tone generators can be used to generate DTMF  
These functions are described in detail in the following chapters.  
RSLIC 1#  
CODEC  
Current  
Sensor  
FSK  
General  
DSP  
Core  
Serial Control  
Interface  
ITDF  
MPI Interface  
Generator  
Control Logic  
Battery  
Switch  
Ring  
Trip  
Channel 1  
Filter  
ADC  
DAC  
Programmable  
Filters and Gain  
PCM  
Timeslot  
Compander  
Assignment  
Ring  
Tip  
Input  
Line  
Stage  
Driver  
Off-hook  
Detector  
Ground Key  
Detector  
Ring Trip  
Detector  
Ring  
Generator  
PCM Interface  
GCI Interface  
SLIC Control  
Interface  
Tone  
Ramp  
Polarity  
Logic  
UTD  
Generators  
Generator  
Reverse  
Control  
PCM/GCI  
Interface  
Ring  
Tip  
RSLIC 2#  
Channel 2  
Ring  
Tip  
RSLIC 3#  
RSLIC 4#  
Channel 3  
Channel 4  
Ring  
Tip  
Figure - 1 Line Circuit Functions Included in the RSLIC-CODEC Chipset  
16  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Depending on the load, the operating point is determined by the  
3.2  
DC FEEDING  
voltage V  
between the Tip and Ring lines as follows:  
Tip/Ring  
V
= R I  
L Tip/Ring  
3.2.1  
DC FEEDING CHARACTERISTIC ZONES  
Tip/Ring  
Where, R represents the equivalent loop resistance. The lower the  
Analog telephones require a DC current in the off-hook state with AC  
voice signals in the transmit and receive directions superimposed. Thus,  
once the telephone has gone off-hook, the SLIC must supply a DC  
current to the subscriber line. The RSLIC-CODEC chipset provides a  
fully programmable DC feeding characteristic to meet the requirements  
of different applications.  
L
load resistance R , the lower the voltage V  
.
Tip/Ring  
L
When the DC feeding is operating in the constant current zone, the  
indication bit FEED_I in register LREG21 will be set to 1, otherwise it is  
set to 0.  
The DC feeding characteristic has three different zones: the constant  
current zone, the resistive zone and the constant voltage zone (see  
3.2.3  
RESISTIVE ZONE  
The resistive zone is flexible in a wide range of applications,  
especially applicable to medium line loops where the battery is unable to  
feed a constant current to the line. In this zone, the DC feeding is  
considered as a voltage source with a programmable internal resistance  
Figure - 2). A voltage reserve V  
is provided to avoid clipping the high  
RES  
level AC signal.  
ITIP-RING  
(R ).  
LIN  
The operating point crosses from the constant current zone to the  
Constant current zone  
resistive zone, as shown in Figure - 4.  
Resistive zone  
ITIP-RING  
Constant voltage zone  
RL  
RLIN  
Necessary Voltage Reserve VRES  
VTIP-RING  
VBAT  
Figure - 2 DC Feeding Zones  
VTIP-RING  
3.2.2  
CONSTANT CURRENT ZONE  
In applications of short local loops, the DC feeding can be considered  
Figure - 4 Resistive Zone  
as an ideal current source with an infinite internal resistance (R ), see  
I
Figure - 3. When the loop is in the off-hook state, the feeding current  
usually must be kept at a constant level independent of the load. The  
RSLIC senses the DC current and provides this information to CODEC  
via the VTDC pin. The CODEC compares this value with the  
programmed value and adjusts the RSLIC drivers as required.  
When the DC feeding is operating in the resistive zone, the indication  
bit FEED_R in register LREG21 will be set to 1, otherwise it is set to 0.  
3.2.4  
In very high impedance loops (long loops), the DC feeding can be  
considered as a voltage source with zero internal resistance (R ).  
CONSTANT VOLTAGE ZONE  
ITIP-RING  
V
In this zone, the voltage V  
is constant and the current I  
Tip/Ring  
Tip/Ring  
depends on the load between the Tip and Ring lines. See Figure - 5.  
To avoid clipping the high level AC speech signals, a voltage reserve  
RL  
RI  
V
should be provided:  
RES  
V
= V  
V  
BAT LIM  
RES  
Where, V is the selected battery voltage, V is the open circuit  
BAT  
LIM  
voltage.  
Normally, V  
= 2 V.  
RES  
When the DC feeding is operating at the constant voltage zone, the  
indication bit FEED_V in register LREG21 will be set to 1, otherwise it is  
set to 0.  
VTIP-RING  
Figure - 3 Constant Current Zone  
17  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
ITIP-RING  
ITIP-RING  
(25 mA)  
IMax  
IK1  
(18 V, 23 mA)  
RLIN  
IK2  
(19.5 V, 16 mA)  
RV  
RL  
RV  
VTIP-RING  
(22 V)  
VTIP-RING  
VK1  
VK2 VLIM  
Figure - 5 Constant Voltage Zone  
Figure - 6 DC Feeding Characteristics Configuration  
3.2.5  
DC FEEDING CHARACTERISTICS CONFIGURATION  
The DC feeding characteristic is programmable. When the  
DC_FEED bit in register LREG5 is set to 1, the default DC feeding  
characteristic will be selected (see Figure - 6). The default configuration  
is typically for -24 V battery voltage application. When the DC_FEED bit  
is set to 0, the DC feeding characteristic is determined by the  
coefficients written in the Coe-RAM.  
ITIP-RING  
RI  
I
MAX (25 mA)  
IDT provides a software (Cal74) that can calculate the coefficients for  
IK1 (20 mA)  
DC feeding. When users input the desired values for I  
I
V
I
Max, K1, K1, K2,  
14mA  
V
and V  
Cal74 will automatically calculate the DC feeding  
LIM,  
K2  
coefficients. When these coefficients are loaded to the Coe-RAM, the  
DC feeding characteristic will meet the requirements.  
To reduce power consumption and make the DC loop stable, it is  
VTIP-RING  
36 40 48  
VK1 (20 V)  
recommended to reduce I  
and keep the output resistance (R ) less  
MAX  
I
than 5 kwhen the loop is operated in the constant current zone.  
Here is an example for short loop applications (see Figure - 7):  
Loop resistance < 600 ;  
Figure - 7 DC Feeding Configuration Example for Short Loop  
Applications  
I
= 25 mA;  
MAX  
V
= 20 V;  
K1  
I
= 20 mA (loop current requirement)  
K1  
R = |(V – 0)/(I – I )| = |(20 – 0)/(20 – 25)| = 4 kΩ  
I
K1  
K1 MAX  
18  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Table - 1 lists the registers and the Coe-RAM locations used for DC  
feeding configuration. For more information about the Coe-RAM, please  
refer to “5.2.5 Addressing the Coe-RAM” on page 61 and Table - 23 on  
page 62.  
Table - 1 Registers and Coe-RAM Locations Used for DC Feeding Configuration  
Parameter  
Register Bits/Coe-RAM Words  
Notes  
DC_FEED = 0: The DC feeding coefficient in the Coe-RAM is selected.  
DC_FEED = 1: The DC feeding coefficient in the ROM is selected (default);  
DC Feeding Coefficients Selection  
Bit DC_FEED in LREG5  
When the DC feeding is operating at the constant current zone, the FEED_I bit is set to  
1, otherwise it is set to 0.  
When the DC feeding is operating at the resistive zone, the FEED_R bit is set to 1,  
otherwise it is set to 0.  
When the DC feeding is operating at the constant voltage zone, the FEED_V bit is set to  
1, otherwise it is set to 0.  
Constant current zone indication  
Resistive zone indication  
Constant voltage zone indication  
IMax  
Bit FEED_I in LREG21  
Bit FEED_R in LREG21  
Bit FEED_V in LREG21  
Programmable via the Coe-RAM. Programmable range: 0 to 50 mA with ±7% tolerance.  
Default value (in the ROM): 25 mA.  
Programmable via the Coe-RAM. Programmable range: 0 to 50 mA with ±7% tolerance.  
Default value (in the ROM): 23 mA.  
IK1  
VK1  
IK2  
Programmable via the Coe-RAM. Programmable range: 0 to 48 V with ±7% tolerance.  
The default value (in the ROM): 18 V.  
DC Feeding Coefficients in the  
Coe-RAM  
Programmable via the Coe-RAM. Programmable range: 0 to 50 mA with ±7% tolerance.  
Default value (in the ROM): 16 mA.  
Programmable via the Coe-RAM. Programmable range: 0 to 48 V with ±7% tolerance.  
Default value (in the ROM): 19.5 V.  
VK2  
VLIM  
Programmable via the Coe-RAM. Programmable range: 0 to 48 V with ±7% tolerance.  
Default value (in the ROM): 22 V.  
19  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
and the corresponding voltages are fed to the CODEC via VTAC and VL  
pins. The voltage signals are further processed within the CODEC and  
finally transmitted to the PCM highway. In the receive direction, the  
CODEC processes data received from the PCM highway and outputs a  
differential analog signal to the RSLIC via the ACP and ACN pins. The  
RSLIC then amplifies this signal and applies it to the subscriber line.  
3.3  
SPEECH PROCESSING  
3.3.1  
AC TRANSMISSION  
The signal paths for AC transmission between the RSLIC and the  
CODEC is shown in Figure - 8. In the transmit direction, the transversal  
and longitudinal currents on the subscriber line are sensed by the RSLIC  
Transmit Path  
VL  
VL1  
TIP  
VTAC  
VTAC1  
ACP1  
ACN1  
RSLIC  
#1  
RING  
ACP  
ACN  
PCM out  
Transmit  
(Data Upstream)  
VL  
VL2  
TIP  
RSLIC  
#2  
VTAC  
ACP  
ACN  
VTAC2  
ACP2  
ACN2  
RING  
MPI or GCI Interface  
CODEC  
VL  
VL3  
TIP  
VTAC  
ACP  
ACN  
VTAC3  
ACP3  
ACN3  
RSLIC  
#3  
RING  
PCM in  
(Data Downstream)  
Receive  
VL  
VL4  
TIP  
RSLIC  
#4  
VTAC  
ACP  
ACN  
VTAC4  
ACP4  
ACN4  
RING  
Receive Path  
Figure - 8 Signal Paths for AC Transmission  
3.3.1.1  
Transmit Path  
The voice signal path within the CODEC for one channel is shown in  
Figure - 9.  
Transmit Path  
Sigma-Delta  
Modulator  
(SDM)  
1st  
Decimation  
Filter  
Digital Gain  
Transmit  
(GTX)  
2nd  
Decimation  
Filter  
Low-Pass  
Filter  
Transmit  
Frequency Response  
Correction Transmit  
(FRX)  
High-Pass  
Filter Transmit  
(HPF)  
Anti-Alias  
Filter (AAF)  
PCM  
Encoder  
Time Slot  
Assignment  
DX1/DX2  
VTAC  
Transhbrid  
Balance Filter  
(ECF)  
Analog Gain for  
Impedance  
Scaling (AGIS)  
Gain for  
Impedance  
Scaling (GIS)  
Impedance  
Matching  
Filter (IMF)  
Sigma-Delta  
Demodulator  
(D-SDM)  
3rd  
Interpolation  
Filter  
Digital Gain  
Receive  
(GRX)  
2nd  
Interpolation  
Filter  
Low-Pass  
Filter  
Receive  
Frequency Response  
Correction Receive  
(FRR)  
1st  
Interpolation  
Filter  
ACP  
ACN  
Analog Gain  
Receive  
Smoothing  
Filter & SCF  
PCM  
Decoder  
Time Slot  
Assignment  
DR1/DR2  
Programmable Filter  
Fixed Filter  
Receive Path  
Figure - 9 Voice Signal Path of the CODEC  
20  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
PROGRAMMABLE FILTERS  
In the transmit path, the analog voltage from the RSLIC is first filtered  
by an anti-aliasing filter (AAF) and then is converted to a digital signal by  
a 1-bit sigma-delta modulator (SDM). The digital signal is down-sampled  
to an intermediate sample frequency to feed to the digital impedance  
matching filter (IMF). Simultaneously, the down-sampled signal is  
summed up with the output of the transhybrid balance filter (ECF). The  
sum signal is transmitted through the transmit gain filter (GTX) and  
further down-sampled to the baseband. A lowpass filter removes the  
unwanted signals to meet ITU-T requirements and a frequency  
response correction filter (FRX) follows to compensate for the  
attenuation brought up by the impedance matching loop. The final stage  
is a highpass filter (HPF) before the data is sent to the PCM encoder,  
where data is A-law or µ-law compressed. At last, the data is assigned  
to the selected time slot and transmitted to the PCM highway.  
3.3.2  
A comprehensive multi-rate signal process scheme with fixed/  
programmable filters is applied to the AC loop of the RSLIC-CODEC  
chipset to optimize the performance of the line card. In addition to fully  
complying with the ITU-T G.712 specifications, the chipset also provides  
additional programmable analog/digital filters to match impedance,  
balance transhybrid, correct frequency response and adjust gains. All of  
the coefficients of the digital filters can be calculated automatically by a  
software (Cal74) provided by IDT. When these coefficients are written to  
coefficient RAM, the final AC transmission characteristics of the line card  
will meet ITU-T specifications.  
Figure - 9 shows the programmable filters in the transmit and receive  
paths.  
3.3.2.1  
Impedance Matching  
3.3.1.2  
Receive Path  
For the RSLIC-CODEC chipset, impedance matching is realized with  
three feedback loops in each channel: one analog loopback, the AGIS  
(Analog Gain for Impedance Scaling) stage, and two digital loopbacks in  
the programmable filters stage GIS (Gain for Impedance Scaling) and  
IMF (Impedance Matching Filter). See Figure - 9 for details. The analog  
In the receive path, the signal received from the PCM highway is first  
passed through the time slot assignment stage before being expanded  
to a linear code at the baseband frequency of 8 kHz by the PCM  
decoder. The expanded data is then up-sampled to a higher frequency  
before passing through the frequency response correction filter (FRR)  
that compensates for the attenuation brought up by the impedance  
matching loop. The compensated signal is filtered by a lowpass filter and  
further up-sampled to the intermediate frequency. The signal is then sent  
to the receive gain filter (GRX). The output of the GRX goes in two ways:  
one feeds to the transhybrid balance filter (ECF) and the other sums up  
with the output of the digital impedance matching filter (IMF). This sum is  
then up-sampled and processed by a digital sigma-delta demodulator  
(D-SDM). An analog filter smooths the signal and outputs it to the RSLIC  
via the ACP and ACN pins.  
loopback realizes the real part value (Re Z ) of the impedance, while the  
L
digital loopbacks realize the imaginary part value (Im Z ) of the  
L
impedance. The GIS and IMF filter loops operate at 2 MHz and 64 kHz  
rate respectively.  
By programming the filters AGIS, GIS and IMF, the AC impedance of  
the chipset can be set to any value inside the shadowed area in Figure -  
10.  
300  
600  
900  
1200  
0
Re ZL  
-200  
-400  
Possible impedance values  
-600  
Im ZL  
Figure - 10 Nyquist Diagram  
21  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
The analog gain for impedance scaling (AGIS) can be 600 or 900  
, as selected by the IM_629 bit in register LREG7. The option of  
AGIS=600 is only applicable to loops with 600 equivalent  
impedance, while the option of AGIS=900 is applicable to all loops  
including those with 600 equivalent impedance. The AGIS value is set  
to 600 by default.  
The coefficient for the GIS filter is programmed by Gain for  
Impedance Scaling in the Coe-RAM. It is programmable from 128 to  
+127 at increment of 1. The default value is 0.  
If the IMF bit in LREG4 is set to 1, the IMF filter is disabled. If the IMF  
bit is set to 0, the Impedance Matching Filter Coefficient in the Coe-RAM  
is used by the IMF filter. Refer to Table - 23 on page 62 for the  
Coefficient RAM Mapping.  
chipset provides two frequency response correction filters per channel:  
one is in the transmit path (FRX), the other is in the receive path (FRR).  
The FRX bit in LREG4 determines whether the FRX filter is disabled  
or programmed by the Coe-RAM. If the FRX bit is set to 1, the FRX filter  
is disabled. If the FRX bit is set to 0, the Coefficient for Frequency  
Response Correction in the Transmit Path in the Coe-RAM is used.  
The FRR bit in LREG4 determines whether the FRR filter is disabled  
or programmed by the Coe-RAM. If the FRR bit is set to 1, the FRR filter  
is disabled. If the FRR bit is set to 0, the Coefficient for Frequency  
Response Correction in the Receive Path in the Coe-RAM is used.  
3.3.2.4  
Gain Adjustment  
For each channel, the gain in the transmit path is adjusted by  
programming the digital filter GTX. The transmit gain can be up to +12  
dB in minimum steps of 0.05 dB. If the GTX bit in LREG4 is set to 1, the  
default transmit gain of 0 dB is selected. If the GTX bit is set to 0, the  
transmit gain is programmed via the Coe-RAM.  
For each channel, the gain in the receive path consists of analog  
gain and digital gain (GRX). The analog gain is fixed at 0 dB. The digital  
gain is programmable from 12 dB to +3 dB in minimum steps of 0.05  
dB. If the GRX bit in LREG4 is set to 1, the digital gain in the receive  
path will be 0 dB (default value), otherwise, it is programmed via the  
Coe-RAM.  
3.3.2.2  
Transhybrid Balance  
The RSLIC-CODEC chipset provides a traditional transhybrid  
balance filter (ECF) for each channel to improve 4-wire return loss  
performance. The ECF coefficient is programmable. If the ECF bit in  
register LREG4 is set to 1, the ECF filter is disabled. If the ECF bit is set  
to 0, the Transhybrid Balance Filter Coefficient in the Coe-RAM is used.  
3.3.2.3  
Frequency Response Correction  
The frequency response correction filters are used to compensate for  
the frequency distortion caused by the impedance matching filter. The  
22  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
DCN pins and further fed to the subscriber line by the RSLIC. Refer to  
Figure - 49 on page 104 for an application circuit using internal ringing.  
To generate a ringing signal, users should first set the operating  
mode to Internal Ringing (the CODEC is set to the RING mode and the  
RSLIC is set to Internal Ringing mode, refer to Table - 3 for details).  
Next, calculate the coefficients of the ringing frequency, amplitude and  
DC offset and load the coefficients to the Coe-RAM (the calculation is  
performed by a software (Cal74) provided by IDT. When users input the  
frequency, amplitude and offset values, Cal74 will calculate the  
coefficients automatically). Then, the ringing generation will be  
controlled by the RING_EN bit in LREG7. In order to reduce noise and  
crosstalk on adjacent lines, the ringing signal will automatically start at a  
zero-crossing after the RING_EN bit is set to 1 and stop at zero-crossing  
after the RING_EN bit is set to 0.  
3.4  
RING AND RING TRIP  
The RSLIC-CODEC chipset supports both internal and external  
ringing modes to meet different requirements.  
3.4.1  
INTERNAL RINGING MODE  
Internal Ringing Generation  
3.4.1.1  
The chipset provides a built-in ring generator per channel that can  
generate balanced sinusoidal ringing signal without external  
components. The frequency, amplitude and DC offset of the ringing  
signal are programmable. In addition, the ring trip detection can be  
performed internally by programming the ring trip threshold.  
If internal ringing mode is selected, the RSLIC will be automatically  
switched to the higher battery (VBH) for ringing generation. The ringing  
signal generated by the CODEC is sent to the RSLIC via the DCP and  
Figure - 11 shows a balanced ringing signal generated by the  
chipset.  
RSLIC  
Tip Line  
BGND  
VDROP.T  
VRING.PP = VTp - VRp  
VT  
VTp  
VDC.RING  
VRp  
VR  
VDROP.R  
VBH  
Ring Line  
Figure - 11 Internal Balanced Ringing  
Ring Trip Detection In Internal Ringing Mode  
3.4.1.2  
simultaneously if the corresponding mask bit HK_M[n] is set to 0.  
Most of the applications use DC ring trip detection because it is very  
reliable. Even with very long and noisy lines the off-hook condition can  
reliably be detected within two ringing period by the DC ring trip. The DC  
ring trip method is selected by setting the RT_SEL bit in LREG7 to 1.  
The DC offset voltage is programmed by the RingOffset in the coefficient  
RAM. See Table - 2 for detailed information.  
In DC ring trip mode, when an off-hook event is detected, the ringing  
signal will stop immediately at zero-crossing. But the RING_EN bit will  
not be cleared to 0 automatically; it should eventually be cleared by  
software. This automatic ring trip function speeds up the response to off-  
hook for time critical applications.  
Once the subscriber has switched from on-hook state to off-hook  
state during ringing, the ringing signal must be removed from the  
subscriber line before normal speech begins. The recognition of an off-  
hook state during ringing, together with the removal of the ringing signal,  
is commonly referred to as ring trip. Depending on the application  
requirements, the RSLIC-CODEC chipset offers two different ring trip  
methods for internal ringing mode, they are DC ring trip detection and  
AC ring trip detection, as selected by the RT_SEL bit in LREG7.  
DC Ring Trip Detection  
Most applications use DC ring trip detection. By applying a DC offset  
voltage together with the ringing signal, a transversal DC loop current  
starts to flow when the subscriber goes off-hook. The RSLIC senses the  
DC current and supplies the corresponding sensed voltage to the  
CODEC via the VTAC pin. The CODEC continuously integrates this  
voltage over one ringing period without rectifying. The result represents  
the DC component of the ring current. If the DC component exceeds the  
programmed DC ring trip threshold, the corresponding HK[n] bit (n = 0 to  
3 are for Channel 1 to 4 respectively) in register GREG26 will be set to 1  
to indicate that the loop has been off-hook. An interrupt will be generated  
AC Ring Trip Detection  
For short loop applications, the DC offset can be removed from the  
ringing signal to increase the achievable voltage amplitude for a given  
supply voltage. The AC ring trip detection without DC offset is realized  
by rectifying sensed ring current signal, integrating it over one ringing  
signal period and comparing the result with the programmed AC ring trip  
threshold. If the threshold is exceeded, the corresponding bit HK[n] (n =  
0 to 3 are for Channel 1 to 4 respectively) in register GREG26 will be set  
23  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
to 1 to indicate off-hook detected. An interrupt will be generated if the  
HK[n] bit is not masked.  
and Ring lines, the on-hook AC current will increase. If the AC load is  
too large, the on-hook current of short loop will be larger than the off-  
hook current of long loop - this will possibly cause a false indication of  
the off-hook condition. Consequently, the AC ring trip detection method  
should only be used in short loops (loop impedance < 1 k) and low-  
power applications.  
Note that during a ring pause period, the off-hook condition can not  
be detected by the AC ring trip. When the off-hook condition is detected  
during a ring burst period, the ringing signal will be removed  
automatically at zero-crossing. As the RING_EN bit remains unchanged,  
users should clear it to 0 by software.  
Table - 2 lists the programmable parameters used for internal ringing  
generation and ring trip detection.  
If several telephones are in parallel with each other between the Tip  
Table - 2 Registers and Coe-RAM Locations Used for Internal Ringing Mode  
Parameter  
Register Bits/Coe-RAM Words  
Notes  
MPI mode: bit RING in LREG7, bits  
SCAN_EN and SM[2:0] in LREG6;  
Internal Ringing Mode Selection GCI mode: bit RING in LREG7, bits  
SCAN_EN and SM[2:0] in downstream C/I  
channel byte.  
RING = 1: the CODEC is set to Ring mode  
SCAN_EN = 1 and SM[2:0] = 010: the RLSIC is set to Internal Ringing mode.  
RING_EN = 0: ring pause;  
RING_EN = 1: ring burst.  
Internal Ringing Enable  
Bit RING_EN in LREG7  
RG = 0: ringing parameters in the Coe-RAM are selected.  
RG = 1: ringing parameters (frequency, amplitude and offset) in the ROM are  
selected (default);  
Internal Ringing Parameters  
Selection  
Bit RG in LREG5  
Programmable via the Coe-RAM. Programmable range: 20 to 200 Hz with ±3%  
tolerance. Default value (in the ROM): 30 Hz.  
Internal Ringing Frequency  
Internal Ringing Amplitude  
Word RingFreq in the Coe-RAM  
Word RingAmp in the Coe-RAM  
Programmable via the Coe-RAM. Programmable range: 0 to 70 Vp with ±1%  
tolerance. Default value (in the ROM): 40 Vp.  
Programmable via the Coe-RAM. Programmable range: 0 to 20 V with ±1%  
tolerance. Default value (in the ROM): 7 V.  
Internal Ringing Offset Voltage Word RingOffset in the Coe-RAM  
RT_SEL = 0: AC ring trip is selected;  
RT_SEL = 1: DC ring trip is selected.  
Signaling = 0: The AC and DC ring trip thresholds in the Coe-RAM are selected;  
Signaling = 1: The AC and DC ring trip thresholds in the ROM are selected (default);  
Ring Trip Method Selection  
Ring Trip Threshold Selection  
AC Ring Trip Threshold  
Bit RT_SEL in LREG7  
Bit Signaling in LREG5  
Programmable via the Coe-RAM. Programmable range: 0 to 20 mA with ±5%  
tolerance. Default value (in the ROM): 5 mA.  
Word RTthld_AC in the Coe-RAM  
Word RTthld_DC in the Coe-RAM  
Bits HK[n] in GREG26  
Programmable via the Coe-RAM. Programmable range: 0 to 20 mA with ±5%  
tolerance. Default value (in the ROM): 5 mA.  
Indicating the ring trip detection result, ‘0’ means Channel n+1 is on-hook while ‘1’  
means Channel n+1 is off-hook (n = 0 to 3)  
DC Ring Trip Threshold  
Ring Trip Detection Result  
Indication  
3.4.2  
EXTERNAL RINGING MODE  
IO_C[0] = 1), the external ringing signal will be switched on the RSYNC  
edge (rising or falling) next to the change of the IO1 pin, as illustrated in  
Figure - 12. The logic level of the IO1 pin is set by the IO[0] bit in  
LREG20:  
The chipset can generate internal ringing signals of up to 70 Vp. In  
applications of requiring higher ring amplitudes, external ringing signals  
can be used. Figure - 50 on page 105 shows an application circuit that  
use an external ringing signal.  
If the RSLIC is set to External Ringing mode (see Table - 3 for  
details), the ringing signal from an external ring generator will be  
switched to the Tip/Ring lines through an external relay during ring burst  
period, and will be removed during ring pause period.  
The CODEC provides two programmable IO pins (IO1 and IO2) with  
relay-driving capability for each channel. They can be used to control the  
external ring relay without additional components. The external ringing  
can be switched on/off in two different modes as described below:  
• Synchronous mode (this mode is available when the IO1 pin is  
selected to control the external ring relay). In this mode, the external  
ringer provides a synchronous signal for the CODEC via the RSYNC pin  
to ensure switching the ringing signal at zero-crossing. This  
synchronous mode is enabled by setting the SYNC_EN bit in LREG19 to  
1. When the IO1 pin of the CODEC is configured as an output (LREG20:  
IO[0] = 0: IO1 pin is set to logic low;  
IO[0] = 1: IO1 pin is set logic high.  
In synchronous mode, the CODEC provides a hardware ring trip  
function to speed up the response of off-hook event. For example, if a  
logic low on the IO1 pin starts the ringing while a logic high on this pin  
stops the ringing, once an off-hook event is detected during ring burst  
period, the IO1 pin will be set to logic high automatically to remove the  
ringing signal although the IO[0] bit remains 0. Users should set the  
IO[0] bit to 1 by software.  
• Asynchronous mode. If no synchronous signal is applied to the  
RSYNC pin of the CODEC, or some applications need to switch the  
ringing signal without any delay caused by zero-crossing  
synchronization, the SYNC_EN bit in LREG19 should be set to 0. In this  
case, the external ringing signal will be switched immediately after the  
corresponding IO pin control bit (IO[0] for the IO1 pin and IO[1] for the  
24  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
IO2 pin) in LREG20 is changed, irrespective of whether the ringing  
signal is at a zero-crossing or not. In this mode, even if the IO1 pin is  
used to control the ring relay, it will act as a normal IO pin. In other  
words, the hardware ring trip function is no longer available and the IO1  
pin is controlled completely by software through the CODEC.  
External Ringing Voltage  
t
t
VRSYNC  
IO[0] bit in LREG20  
t
t
t
VIO1  
VRING  
Suppose a logic low on the  
IO1 pin starts the ringing.  
Figure - 12 External Ringing Synchronization  
3.4.2.1  
Ring Trip Detection In External Ringing Mode  
1, indicating that off-hook is detected.  
When detecting a ring trip, an offset voltage (about 10 to 30 mV) may  
be introduced by the operational amplifier mentioned above. This offset  
can be measured by the DC level meter and compensated by writing the  
corresponding compensation value to DC Offset in the Coe-RAM.  
Before measuring this offset voltage, make sure that no external  
ringing signal is applied to the Tip/Ring lines. The measuring procedure  
is as follows (to understand the following descriptions, users should  
understand the level meter first):  
In external ringing mode, the sensed ring current signal is processed  
by an operational amplifier in the RSLIC and supplied to the CODEC via  
the RTIN pin for ring trip detection. In external ringing mode, the level  
meter will be involved when detecting the ring trip. For detailed  
information about the level meter, please refer to “3.9.4 Level Meter” on  
page 40.  
To detect ring trip, the steps below should be followed:  
1. Select the RTIN as the input source to the DC path (LREG9:  
LM_SEL[3:0] = 1100);  
2. Write the external ring trip threshold to HKthld in the Coe-RAM;  
3. Set the CODEC to ACTIVE mode and set the RSLIC to External  
Ringing mode (the chipset operating mode control bits are  
different in MPI interface and GCI interface, refer to Table - 3 for  
details);  
4. The CODEC processes the RTIN signal and compares the result  
with the external ring trip threshold written in HKthld in the Coe-  
RAM. If the threshold is exceeded, the corresponding HK[n] bit in  
GREG26 (n = 0 to 3 corresponds to Channel 1 to 4) will be set to  
1. Set the CODEC to ACTIVE mode and set the RSLIC to External  
Ringing mode (see Table - 3 for details);  
2. Select the RTIN as the input to the DC path of the CODEC  
(LREG9: LM_SEL[3:0] = 1100);  
3. In LREG8, set DC_SRC = 1 and LM_SRC = 0;  
4. Select the channel to be measured by setting the LM_CS[1:0] bits  
in GREG16 accordingly;  
5. Set the integrating time to 001H (GREG15 & GREG16:  
LM_CN[10:0] = 001H);  
6. Set the shift factor (K[3:0] in LREG9);  
25  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
DC Offset in the Coe-RAM.  
7. Disable the rectifier (LREG10: LM_RECT = 0);  
8. Set the gain factor as required (LREG10: LM_GF);  
9. Set the level meter measurement mode to ONCE and start the  
measurement (GREG16: LM_ONCE = 1, LM_EN = 1);  
10.Read the measurement result from GREG17 & GREG18 (16-bit);  
11.Right shift the 16-bit result for two bits, then the result is the offset  
value in the form of a 14-bit two’s complement;  
13.Select this offset compensation value to be used (LREG4:  
DC_OFT = 0);  
14.Restore the modified registers with original contents;  
Then, the four steps mentioned above follow and off-hook event will  
be more reliably detected.  
Table - 3 shows the registers and Coe-RAM locations used for  
external ringing mode.  
12.Invert each bit of the offset value and add 1 to it, write this result to  
Table - 3 Registers and Coe-RAM Locations Used for External Ringing Mode  
Parameter  
Register Bits  
Notes  
MPI mode: bits ACTIVE, SCAN_EN and SM[2:0]  
CODEC and RSLIC Operating Mode in LREG6;  
ACTIVE = 1: the CODEC is set to Active mode  
SCAN_EN = 1 and SM[2:0] = 001: the RLSIC is set to External Ringing  
mode.  
Configuration  
GCI mode: bit ACTIVE in LREG6, bits SCAN_EN  
and SM[2:0] in downstream C/I channel byte.  
IO_C[0] = 1: the IO1 pin is configured as an output  
IO[0] = 0: the IO1 pin is set to logic low  
IO[0] = 1: the IO1 pin is set to logic high  
External Ring Relay Control  
(recommended)  
Bit IO_C[0] in LREG20  
Bit IO[0] in LREG20  
SYNC_EN = 0: asynchronous mode is selected  
SYNC_EN = 1: synchronous mode is selected  
Synchronous Mode Enable Bit  
Bit SYNC_EN in LREG19  
External Ring Trip Detection Source Bit LM_SEL[3:0] in LREG9  
LM_SEL[3:0] = 1100: RTIN is selected to the DC path for ring trip detection  
If the Signaling bit in LREG5 is set to 1, the external ring trip threshold in  
the ROM is selected, otherwise the threshold written in HKthld in the Coe-  
RAM is selected.  
The HKthld in the Coe-RAM is programmable from 0 to 20 mA with ±5%  
tolerance. The default value (in the ROM) is 7 mA.  
External Ring Trip Threshold  
Word HKthld in the Coe-RAM  
Note that both the off-hook detection threshold in active mode and the  
external ring trip threshold are written in HKthld in the Coe-RAM. Users  
should change the threshold according to different conditions.  
External Ring Trip Detection Result  
Indication  
Indicating the ring trip detection result, ‘0’ means Channel n+1 is on-hook  
while ‘1’ means Channel n+1 is off-hook (n = 0 to 3).  
Bits HK[n] in GREG26  
LREG8: LM_SRC, DC_SRC  
LREG9: K[3:0]  
LREG10: LM_GF, LM_RECT  
GREG15 & GREG16  
GREG17 & GREG18  
Level Meter Configuration and Result  
Registers  
Refer to Table - 17 on page 44 for details.  
DC_OFT = 0: compensation value in word DC Offset in the Coe-RAM is  
Bit DC_OFT in LREG4  
Word DC Offset in the Coe-RAM  
selected;  
DC Offset Compensation  
DC_OFT = 1: compensation value (which is 0) in the ROM is selected  
(default).  
26  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
OFF-HOOK DETECTION  
3.5.1  
3.5  
SUPERVISION  
Loop start signaling is the most common type of signaling. The  
subscriber loop is closed by the hook switch inside the subscriber  
equipment. For the RSLIC-CODEC chipset, the off-hook detection can  
be operated in two different modes as shown in Table - 4.  
Supervision is performed internally by the RSLIC-CODEC chipset.  
The RSLIC senses the longitudinal and transversal line currents on the  
Ring and Tip lines, and feeds the corresponding voltages to the CODEC  
via the VL, VTAC and VTDC pins for further process. In this way, the  
signaling in the subscriber loop is monitored.  
Table - 4 Off-hook Detection in Different Modes  
Chipset Mode  
CODEC Mode  
RSLIC Mode  
Mode Control Register Setting  
MPI mode:  
GCI mode:  
LREG6: ACTIVE = 1, SCAN_EN = 1, SM[2:0] = 000  
LREG6: ACTIVE = 1; downstream C/I channel byte: SCAN_EN = 1, SM[2:0] = 000  
Active  
Active  
Active  
MPI mode:  
GCI mode:  
LREG6: STANDBY = 1, SCAN_EN = 1, SM[2:0] = 110  
LREG6: STANDBY = 1; downstream C/I channel byte: SCAN_EN = 1, SM[2:0] = 110  
Sleep  
Standby  
Standby  
Note: The operating mode of the CODEC is set by register LREG6. The operating mode of the RSLIC is set by register LREG6 (for MPI mode) or downstream C/I  
channel byte. Refer to “6.1 Operating Modes” on page 87 for further details.  
• Active mode  
An interrupt will be generated at the same time if the off-hook mask bit  
HK_M in register LREG18 is disabled (‘0’).  
In this mode, both the RSLIC and the CODEC are active. The RSLIC  
senses the transversal current on the Ring and Tip lines, and feeds the  
corresponding voltage to the CODEC via VTDC pin. Inside the CODEC,  
this voltage is A-to-D converted and filtered. The result is compared with  
the programmed off-hook threshold (word HKthld in the Coe-RAM). If  
the result exceeds the threshold, the bit HK[n] (n = 0, 1, 2 or 3) in  
register GREG26 will be set to 1, indicating that Channel n+1 is off-hook.  
In active mode, to detect the loop transition from off-hook to on-hook,  
the on-hook threshold should be used. The off-hook threshold minus a  
programmable hysteresis value is the on-hook threshold (as shown in  
Figure - 13). The hysteresis value is programmed by HKHyst in the Coe-  
RAM. The default value is 2 mA.  
Hook State  
Indication  
Hysteresis  
I
On-hook  
Off-hook  
Threshold  
Threshold  
Figure - 13 Hysteresis for Off-Hook Detection  
• Sleep mode  
will be ignored. As shown in Figure - 14, a four-bit debounce counter  
allows the debounce interval programmable from 0.125 ms to 2 ms. A  
16-state up/down counter follows, resulting in the minimal debounce  
time ranging from 2 ms to 32 ms. The debounce interval is programmed  
by the DB[3:0] bits in LREG11.  
(Note: When the RSLIC operating mode is switching from other  
mode to the active mode, there might be a narrow pulse of about 15 ms  
occurring on VTDC, resulting in a false off-hook interrupt to be  
generated. If this happens, please set the debounce time for off-hook  
detection to 15 ms or above (i.e., DB[3:0] 0111B) to filter the noise  
pulse.)  
In this mode, both the CODEC and the RSLIC are in standby mode.  
All of the function blocks except off-hook detection stop working. The  
transversal current on the Ring and Tip lines is sensed by a simple  
sense circuit and the corresponding sensed voltage is fed to an analog  
comparator in the CODEC via the VTAC pin. By comparing this sensed  
voltage with a fixed off-hook threshold of 2 mA, the off-hook event can  
be detected. Once the loop goes off-hook, the whole chipset should be  
set to active mode by the master processor.  
The CODEC integrates a programmable debounce filter in the off-  
hook detection circuit to eliminate disturbance. The transversal DC  
signal (which is taken as the off-hook criterion) will be filtered by this  
debounce filter. The DC signal with duration less than the debounce time  
Table - 5 shows the registers and Coe-RAM locations used for off-  
hook detection.  
27  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Off-hook/  
Ground-key  
0
1
Debounced  
Off-hook/  
Ground-key  
MUX  
DB[3:0]  
Debounce Interval  
(0.125 ms 2 ms)  
Q
Q
D
En  
Up/down  
DB[0]  
DB[1]  
DB[2]  
DB[3]  
En  
FS  
MCLK  
16 states  
Up/down Counter  
4 bit Debounce  
Counter  
Figure - 14 Debounce Filter for Off-hook/Ground-key Detection  
Table - 5 Registers and Coe-RAM Locations Used for Off-hook Detection  
Parameter  
Off-hook Indication  
Register Bits/Coe-RAM Words  
Notes  
HK[n] = 0: Channel n+1 is on-hook (n = 0 to 3);  
HK[n] = 1: Channel n+1 is off-hook.  
Bits HK[3:0] in GREG26  
HK_M = 0: each change of HK[3:0] bits generates an interrupt;  
HK_M = 1: changes of HK[3:0] bits do not generate interrupts.  
Mask bit for HK[3:0] bits  
Bit HK_M in LREG18  
Bit Signaling in LREG5  
Signaling = 0: the off-hook threshold in the Coe-RAM is selected.  
Signaling = 1: the off-hook threshold in the ROM is selected (default).  
Off-hook Threshold Selection  
If the Signaling bit in LREG5 is set to 0, the off-hook threshold for active mode is  
programmed by word HKthld in the Coe-RAM. It is programmable from 0 to 20 mA with  
±5% tolerance.  
Off-hook Threshold for Active Mode  
Word HKthld in the Coe-RAM  
If the Signaling bit in LREG5 is set to 1, the default value of 7 mA (stored in the ROM) is  
selected.  
If the Signaling bit in LREG5 is set to 0, the hysteresis for off-hook detection is  
programmed by word HKhyst in the Coe-RAM. It is programmable from 0 to 20 mA with  
Hysteresis for Off-hook Detection  
Debounce Interval Selection  
Word HKHyst in the Coe-RAM ±5% tolerance.  
If the Signaling bit in LREG5 is set to 1, the default value of 2 mA (stored in the ROM) is  
selected.  
The interval is programmable from 0.125 ms to 2 ms in steps of 0.125 ms. The default  
value of DB[3:0] is ‘0000’, corresponding to the minimum debounce interval of 0.125 ms.  
Bits DB[3:0] in LREG11  
28  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
3.5.2 GROUND-KEY DETECTION  
INDUSTRIAL TEMPERATURE RANGE  
An application example is shown in the following:  
• Tip open or Ring open mode  
In applications of using ground-key signaling, the longitudinal current  
of the loop is used as ground-key criterion. The RSLIC senses the  
longitudinal current and transfers the scaled longitudinal voltage  
information to the CODEC via VL pin. An analog comparator for ground-  
key detection compares this voltage with a fixed threshold (11.8 mA). If  
the threshold is exceeded, the bit GK[n] (n = 0, 1, 2 or 3) in register  
GREG26 will be set to 1 to indicate that ground-key is detected in  
Channel n+1. An interrupt will occur if any bit of GK[3:0] changing from 0  
to 1. The GK[3:0] bits can be masked by the GK_M bit in register  
LREG18.  
In this case, the Tip line or the Ring line is switched to high  
impedance, the longitudinal current on the Ring or Tip line is sensed by  
the RSLIC and fed to the CODEC through the VL pin for testing.  
The longitudinal DC signal (which is taken as the ground-key  
criterion) is also filtered by the programmable debounce filter used in off-  
hook detection. The DC signal with duration less than the denounce time  
will be ignored. The debounce interval is programmable by the DB[3:0]  
bits in register LREG11. Refer to Figure - 14 for details.  
Table - 6 shows the registers used for ground-key detection.  
The polarity of the longitudinal current is indicated by the GK_POL bit  
in register LREG21. Each change of the GK_POL bit generates an  
interrupt. The GK_POL bit can be masked by the GKP_M bit in register  
LREG18.  
Table - 6 Registers Used for Ground-key Detection  
Parameter  
Ground-key Indication  
Register Bits  
Notes  
GK[n] = 0: no longitudinal current detected in Channel n+1 (n = 0 to 3);  
GK[n] = 1: longitudinal current detected in Channel n+1.  
Bits GK[3:0] in GREG26  
GK_M = 0: each change of the GK[3:0] bits generates an interrupt;  
GK_M = 1: changes of the GK[3:0] bit do not generate interrupts.  
Mask bit for GK[3:0] bits  
Ground-key Polarity  
Bit GK_M in LREG18  
Bit GK_P in LREG21  
GK_P = 0: negative ground-key threshold level active;  
GK_P = 1: positive ground-key threshold level active.  
GKP_M = 0: each change of the GK_P bit generates an interrupt;  
GKP_M = 1: changes of the GK_P bit do not generate interrupt.  
Mask bit for GK_P bit  
Bit GKP_M in LREG18  
Bits DB[3:0] in LREG11  
Debounce Interval Selection  
The interval is programmable from 0.125 ms to 2 ms in steps of 0.125 ms.  
The voltage polarity is reversed in a smooth way to avoid generating  
non-required ringing. Users can control the transition time (time from  
start to end of polarity reversal) by programming the built-in ramp  
generator. Refer to "Ramp Generator" on page 47 for further details.  
3.6  
METERING BY POLARITY REVERSAL  
The RSLIC-CODEC supports metering by reversing the polarity of  
the voltage on the Tip and Ring lines. The actual polarity of this voltage  
is reversed by setting the REV_POL bit in register LREG19 to 1.  
29  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
coefficients can be calculated, respectively, by the following formulas:  
f<2000 Hz, Frequency coefficient = 8191cos(f/8000∗2∗π)  
f>2000 Hz, Frequency coefficient = 16384 - 8191cos(f/8000∗2∗π)  
Amplitude coefficient = A8191sin(f/8000∗2∗π)  
Herein, 'f' is the desired frequency of the tone. 'A' is the scaling  
parameter for the tone amplitude. The range of 'A' is from 0 to 1.  
A = 1, corresponding to the maximum amplitude, 1.57 (V);  
A = 0, corresponding to minimum amplitude, 0 (V).  
It is a linear relationship between 'A' and the amplitude, which means  
if A = β (0< β< 1), the amplitude will be 1.57 ∗ β (V).  
The frequency is programmable from 25 Hz to 3400 Hz. The  
tolerance is as follows:  
3.7  
ENHANCED SIGNAL PROCESSING  
Besides the fundamental BORSCHT functions, the RSLIC-CODEC  
chipset also provides several additional functions such as Tone  
Generation, FSK generation for Caller-ID and Universal Tone Detection.  
These additional functions can be individually enabled or disabled  
according to the requirements of applications.  
3.7.1  
TONE GENERATOR  
The CODEC provides two tone generators for each channel: Tone  
Generator 1 (TG1) and Tone Generator 2 (TG2). They can be used to  
generate signals such as a test tone, DTMF, dial tone, busy tone,  
congestion tone and Caller-ID alerting tone etc., and output them to the  
RSLIC via the ACP and ACN pins.  
f < 200 Hz, tolerance < ± 3%;  
f > 200 Hz, tolerance < ± 1.5%.  
The TG1 and TG2 of each channel can be enabled by setting bits  
TG1_EN and TG2_EN in register LREG7 to 1, respectively.  
The amplitude and frequency coefficients of the tone signal can be  
calculated by the Cal74 software automatically. Refer to Table - 7 for  
more information about registers and Coe-RAM used for tone  
generators.  
Note that when using the dual tone generators, users must write  
2000H (high byte: 20H; low byte: 00H) to block2 word4 of the Coe-  
RAM to ensure proper operation.  
If the TG bit in register LREG4 is set to 1, the default frequency and  
amplitude values in the ROM are selected for tone generators (default:  
TG1Amp = 0.94 V, TG1Freq = 852 Hz, TG2Amp = 0.94 V, TG2Freq =  
1447 Hz). Otherwise, the frequency and amplitude values of TG1 and  
TG2 are programmed by the Coe-RAM. The frequency and amplitude  
Table - 7 Registers and Coe-RAM Locations Used for Tone Generation  
Parameter  
Register Bits/Coe-RAM Words  
Notes  
TG = 0: The frequency and amplitude coefficients in the Coe-RAM are selected for the tone  
TG Frequency and Amplitude  
Coefficients Selection  
generators;  
Bit TG in LREG4  
TG = 1: The frequency and amplitude coefficients in the ROM are selected for the tone  
generators (default);  
TG1_EN = 0: TG1 is disabled.  
TG1_EN = 1: TG1 is enabled.  
TG1 Enable/Disable Bit  
TG1 Amplitude Coefficient  
TG1 Frequency Coefficient  
TG2 Enable/Disable Bit  
TG2 Amplitude Coefficient  
TG2 Frequency Coefficient  
Bit TG1_EN in LREG7  
The amplitude is programmable from 0 V to 1.57 V with ±1% tolerance. The default amplitude  
(in the ROM) is 0.94 V.  
Word TG1Amp in the Coe-RAM  
Word TG1Freq in the Coe-RAM  
Bit TG2_EN in LREG7  
The frequency is programmable from 25 to 3400 Hz. The tolerance is ±3% (f<200 Hz) or  
±1.5% (f>200 Hz). The default frequency (in the ROM) is 852 Hz.  
TG2_EN = 0: TG2 is disabled  
TG2_EN = 1: TG2 is enabled  
The amplitude is programmable from 0 V to 1.57 V with ±1% tolerance. The default amplitude  
(in the ROM) is 0.94 V.  
Word TG2Amp in the Coe-RAM  
Word TG2Freq in the Coe-RAM  
The frequency is programmable from 25 to 3400 Hz. The tolerance is ±3% (f<200 Hz) or  
±1.5% (f>200 Hz). The default frequency (in the ROM) is 1447 Hz.  
3.7.1.1  
DTMF Generation  
programming the amplitude and frequency of the tone generators  
through MPI or GCI interface, the 16 standard DTMF pairs can be  
generated independently in each channel. The generated DTMF tone  
signals meet the frequency variation tolerances specified in the ITU-T  
Q.23 recommendation.  
Dual Tone Multi-Frequency (DTMF) is a signaling scheme using  
voice frequency tones to signal dialing information. A DTMF signal is the  
sum of two tones, one from the low frequency group (697 - 941 Hz) and  
one from the high frequency group (1209 - 1633 Hz), with each group  
containing four individual tones. This scheme allows 16 unique  
combinations. Ten of these codes represent the numbers from zero  
through nine on the telephone keypad, the rest six codes (, #, A, B, C,  
D) are reserved for special signaling. The buttons are arranged in a  
matrix, with the rows determining the low group tones, and the columns  
determining the high group tone for each button.  
3.7.2  
FSK GENERATION FOR CALLER ID  
The RSLIC-CODEC chipset provides an optimized FSK generator for  
sending Caller ID information. Different countries use different standards  
to send Caller ID information by FSK codes. The FSK modulation of the  
RSLIC-CODEC chipset is compatible with the most common standards:  
BELL 202 and ITU-T V.23. Table - 8 shows the modulation  
characteristics of these two standards.  
Based on the scheme described in the preceding paragraph, a  
DTMF signal can be generated by the two tone generators. By  
30  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Table - 8 FSK Modulation Characteristics  
Characteristic  
ITU-T V.23  
BELL 202  
Mark (Logic 1)  
Space (Logic 0)  
Modulation  
1300 ± 3 Hz  
2100 ± 3 Hz  
1200 ± 3 Hz  
2200 ± 3 Hz  
FSK  
Transmission Rate  
Data Format  
1200 ± 6 baud  
Serial binary asynchronous  
Generally, the transmission of the FSK signal starts with a Seizure  
Signal, which is a string of '01' pairs. Then a Mark Signal which is a  
string of ‘1’ follows. The Caller ID information comes after the Mark  
Signal. Between two bytes of the Caller ID information, a Flag Signal  
which is a string of '1' is inserted so that the receiver can have enough  
time to process the received bytes. The transmission sequence of the  
FSK signal is shown in Figure - 15.  
FSK_TS  
Start Bit Stop Bit Start Bit Stop Bit Start Bit Stop Bit Start Bit Stop Bit  
Data  
Byte  
Flag  
Signal  
Data  
Byte  
Flag  
Signal  
Data  
Byte  
Flag  
Signal  
Data  
Byte  
Flag  
Signal  
Seizure Signal  
Mark Signal  
Transmit  
Signal  
In this example, Seizure Length = 32(d) (FSK_SL[7:0] = 16(d));  
Flag Length = 8(d) (FSK_FL[7:0] = 8(d));  
Mark Length = 32(d) (FSK_ML[7:0] = 32(d));  
Data Length = 4(d) (FSK_DL[7:0] = 4(d)).  
Figure - 15 FSK Signal Transmission Sequence  
The lengths of the Seizure Signal, Mark Signal, Flag Signal and  
Caller ID data are programmable by register GREG21, GREG22,  
GREG19 and GREG20, respectively.  
written in the FSK-RAM automatically, following the procedure shown  
below:  
Step 1: Start, send Seizure Signal;  
The CODEC provides total 64 bytes RAM (called FSK-RAM) to store  
the Caller ID information. If the length of the information is less than 64  
bytes, all information bytes can be written to the FSK-RAM at one time.  
If the length of the information is longer than 64 bytes, the information  
should be divided into two or more segments according to its actual  
length (each segment 64 bytes). Write one segment to the FSK-RAM  
at one time. When this segment has been sent out, the FSK-RAM can  
be updated with the next segment. Repeat the same operation until all  
segments have been sent out. Refer to “5.2.4 Addressing the FSK-  
RAM” on page 60 for further details on accessing the FSK-RAM via MPI  
or GCI interface.  
Step 2: Send Mark Signal;  
Step 3: Send one start bit (0), one byte of data in the FSK-RAM,  
one stop bit (1), then send Flag Signal;  
Step 4: Check whether all data in the FSK-RAM has been sent out.  
If it has, set the FSK_TS bit to 0 and stop, otherwise return  
to step 3.  
- Bit FSK_MAS. This bit determines whether the FSK generator will  
output a mark-after-send signal (a string of ‘1’) after the data in the FSK-  
RAM has been sent out. If total Caller ID information is longer than 64  
bytes, the FSK_MAS bit should be set to 1. After sending out one  
segment, the FSK generator will keep sending out a mark-after-send  
signal to hold the established communication channel for sending the  
remaining segment(s). After all segments have been sent out, the  
FSK_MAS bit should be set to 0 so that the output of the FSK generator  
will be muted. Once the FSK_MAS bit is 0, changing it from 0 to 1 will  
not make the mark-after-send signal active until a new transmission  
starts (FSK_TS = 1).  
If total Caller ID information is less than 64 bytes, the FSK_MAS bit  
should be set to 0 so that the output will be muted after all information  
has been sent out.  
Note that the Caller ID information is read from or written to the FSK-  
RAM via MPI or GCI interface with MSB first; but the FSK codes are  
sent out by the FSK generator through the selected channel with LSB  
first.  
The FSK generator is controlled by register GREG23, as described  
in the following:  
- Bit FSK_EN. This bit is used to enable or disable the FSK  
generator. The FSK_EN bit must be set to 1 to enable the FSK  
generator before FSK transmission starts. When the transmission is  
finished, the FSK_EN bit should be set to 0 to disable the FSK  
generator.  
- Bits FSK_CS[1:0]. These two bits are used to select a channel to  
send FSK signal (the FSK generator is shared by four channels).  
- Bit FSK_BS. This bit is used to select one of the two FSK  
modulation standards BELL 202 and ITU-T V.23.  
- Bit FSK_TS. This bit is used to start the FSK transmission. Once  
the FSK_TS bit is set to 1, the FSK generator begins to send the data  
31  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Table - 9 shows the configuration and control registers used for the  
FSK generator. Refer to Figure - 16 on page 33 for a recommended  
programming flow chart for FSK generation.  
Table - 9 Registers and FSK-RAM Used for the FSK Generator  
Parameter  
Register Bits/FSK-RAM  
Notes  
Flag Length  
Bits FSK_FL[7:0] (GREG19)  
The length of the Flag Signal is programmable from 0 to 255 (bits).  
Data Length is the number of the Caller ID data bytes written in the FSK-RAM. The valid data  
length is 0 to 64 (bytes).  
Seizure Length is the number of ‘01’ pairs that represent the seizure signal. The length of the  
Seizure Signal is two times of the value specified in GREG21. That means, Seizure Length can  
be up to 510 pairs.  
Data Length  
Bits FSK_DL[7:0] (GREG20)  
Bits FSK_SL[7:0] (GREG21)  
Seizure Length  
Mark Length  
Bits FSK_ML[7:0] (GREG22)  
Bit FSK_TS in GREG23  
The length of the Mark Signal is programmable from 0 to 255 (bits).  
FSK_TS = 1: FSK transmit start. The FSK_TS bit will be cleared to 0 automatically after the  
data in the FSK-RAM is completely sent out.  
Transmit Start  
After the data in the FSK-RAM is sent out, if FSK_MAS = 1, the FSK generator sends out a  
mark-after-send signal (a string of ‘1’), otherwise, the output of the FSK generator is muted.  
Mark After Send  
Bit FSK_MAS in GREG23  
Bit FSK_BS in GREG23  
Bit FSK_EN in GREG23  
FSK Modulation Standard  
Selection  
FSK_BS = 0: BELL 202 is selected;  
FSK_BS = 1: ITU-T V.23 is selected.  
FSK_EN = 0: FSK generator is disabled;  
FSK_EN = 1: FSK generator is enabled.  
FSK Generator Enable  
FSK Channel Selection  
FSK Data RAM  
Bits FSK_CS[1:0] in GREG23  
FSK-RAM  
Select one of the four channels to send the Caller ID data.  
Total 64 bytes  
32  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Start  
Read GREG23  
N
FSK_EN = 1 ?  
Y
FSK_EN = 1  
N
FSK_TS = 0 ?  
Y
Set Seizure Length (GREG21)  
Set Mark Length (GREG22)  
Set Flag Length (GREG19)  
Y
N
Total Caller ID data =< 64 bytes ?  
Set the length of the Caller ID data to be  
sent at this time (GREG20)  
Set Data Length (GREG20)  
Write CID data into FSK-RAM  
Write the Caller ID data to be sent at this  
time to the FSK-RAM  
In GREG23:  
In GREG23:  
Mark Length = 0  
- Select a channel by setting bits FSK_CS[1:0];  
- Select a standard by setting bit FSK_BS;  
- FSK_MAS = 1;  
- Select a channel by setting bits FSK_CS[1:0];  
- Select a standard by setting bit FSK_BS;  
- FSK_MAS = 0;  
- FSK_TS = 1  
Seizure Length = 0  
- FSK_TS = 1  
N
N
FSK_TS = 0 ?  
FSK_TS = 0 ?  
Y
Y
FSK_EN = 0  
N
Finish sending all Caller ID data ?  
Y
End  
FSK_MAS = 0  
FSK_EN = 0  
End  
Figure - 16 Recommended Programming Flow Chart for FSK Generation  
33  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
3.7.3  
UNIVERSAL TONE DETECTION (UTD)  
transmission. With this mechanism implemented in the chipset, the  
optimum modem transmission rate can always be achieved.  
The characteristic of the lowpass filter can be changed by software. If  
the V90 bit in register LREG5 is set to 1, this filter will be configured for  
V90 connections (modem-optimized), otherwise it will be configured for  
V34 connections (voice-optimized).  
3.7.3.1  
Introduction  
The RSLIC-CODEC chipset provides optimized solution not only for  
voice transmission, but for modem data transmission. The performance  
of the latter is becoming a key performance for the increasing internet  
access and other data applications. The chipset’s universal tone (fax/  
modem tone) detection allows the use of modem-optimized filter for V.34  
and V.90 connections.  
The CODEC provides an integrated Universal Tone Detection (UTD)  
unit per channel to detect fax and modem tones from the transmit or  
receive path. The UTD unit can detect tone signals whose frequencies  
are between 1500 Hz and 2600 Hz.  
If a fax or modem tone is detected, which means that a modem  
connection is about to be established, the lowpass filter (see Figure - 9  
on page 20) characteristic is changed to a modem-optimized one. If the  
modem data transmission is completed, the lowpass filter characteristic  
will be switched back to the voice-optimized one for voice data  
3.7.3.2  
UTD Principle  
As shown in Figure - 17 (UTD Functional Block Diagram), the input  
signal from transmit or receive path is first filtered by a programmable  
bandpass filter and a programmable bandstop filter separately. The in-  
band (upper path) and out-of-band (lower path) signals are then  
separated from each other and the corresponding absolute values are  
calculated. The two calculated results are sent to two integrators,  
respectively. Finally, the evaluation logic block determines whether a  
tone is detected by comparing the in-band level with the out-of-band  
level.  
Programmable Bandpass Filter  
|X|  
Integrator  
Signal In  
Detection Result  
Evaluation Logic  
Programmable Bandstop Filter  
|X|  
Integrator  
Figure - 17 UTD Functional Diagram  
If a tone has been detected in the receive or transmit path, the  
UTD_OK bit in LREG21 will be set to 1 and an interrupt will be  
generated.  
The UTD_OK bit will be set to 1 if all the following conditions hold for  
a time span of at least a Recognition Time (RTime, programmable by  
LREG14) without occurring breaks longer than a Recognition Break  
Time (RBRKTime, programmable by LREG15):  
• The in-band signal level is lower than the ceiling threshold  
(programmable by word UTDthld_Ceiling in the Coe-RAM).  
Figure - 18 shows an example of UTD recognition timing.  
The UTD_OK bit will be reset to 0 if one of the preceding conditions  
is violated for at least a time span of an End Detection Time (ETime,  
programmable by LREG16) during which the violation does not cease  
for at least an End Detection Break Time (EBRKTime, programmable by  
LREG17). Refer to Figure - 19 for an example of UTD tone end  
detection timing.  
• The in-band signal level is higher than out-band signal level.  
• The in-band signal level is higher than the floor threshold  
(programmable by word UTDthld_Floor in the Coe-RAM).  
34  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Tone  
t
RBRKTime  
UTD-OK  
RTime  
t
RBRKTime  
UTD-OK  
RTime  
t
Figure - 18 Example of UTD Recognition Timing  
Tone  
t
EBRKTime  
ETime  
UTD-OK  
t
EBRKTime  
UTD-OK  
ETime  
t
Figure - 19 Example of UTD Tone End Detection Timing  
35  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
3.7.3.3  
Table - 10 shows the registers and Coe-RAM locations used for the  
UTD unit.  
The UTD unit can be enabled or disabled individually for each  
channel by the UTD_EN in register LREG8. The UTD_SRC bit in  
LREG8 determines whether the signal from transmit or receive path is  
detected. The RTime, RBRKTime, ETime and EBRKTime of the UTD  
are programmed by LREG14, LREG15, LREG16 and LREG17,  
respectively.  
If the UTD bit in LREG5 is set to 0, the coefficients of the bandpass  
and the bandstop filters and the thresholds of the signal are  
programmable via the Coe-RAM. The center frequencies of the two  
filters should be the same. The center frequency can be programmed  
UTD Programming  
from 1500 Hz to 2600 Hz. The bandwidths of the two filters are also  
programmable. The ceiling and floor thresholds of the signal can be  
programmed from 30 dBm to 0 dBm in minimum steps of 0.2 dBm.  
IDT provides a software (Cal74) to calculate the filter and threshold  
coefficients. When users input the desired center frequency, bandwidth  
for the two filters and ceiling threshold, floor threshold for the signal, the  
software will automatically calculate all the coefficients for the UTD unit.  
After loading these coefficients to the Coe-RAM, the performance of the  
UTD unit will meet the users’ requirements. Refer to Table - 23 on page  
62 for the Coe-RAM mapping.  
If the UTD bit is set to 1, the filter coefficients and the thresholds in  
the ROM are used. These values are used by default. See Table - 10 for  
details.  
Table - 10 Registers and Coe-RAM Locations Used for UTD  
Parameter  
UTD Unit Enable  
Register Bits/Coe-RAM Words  
Bit UTD_EN in LREG8  
Notes  
UTD_EN = 0: the UTD unit is disabled;  
UTD_EN = 1: the UTD unit is enabled.  
UTD_SRC = 0: signal from receive path is detected;  
UTD_SRC = 1: signal from transmit path is detected.  
UTD_OK = 0: no fax/modem tone has been detected;  
UTD_OK = 1: fax/modem tone has been detected.  
Recognition time, programmable from 0 to 4000 ms. The default value is  
304 ms.  
Recognition break time, programmable from 0 to 1000 ms. The default  
value is 100 ms.  
End detection time, programmable from 0 to 1000 ms. The default value is  
256 ms.  
End detection break time, programmable from 0 to 255 ms. The default  
value is 100 ms.  
UTD Source Selection  
UTD Result Indication  
UTD RTime  
Bit UTD_SRC in LREG8  
Bit UTD_OK in LREG21  
Bits UTD_RT[7:0] (LREG14)  
Bits UTD_RBK[7:0] (LREG15)  
Bits UTD_ET[7:0] (LREG16)  
Bits UTD_EBRK[7:0] (LREG17)  
UTD RBRKTime  
UTD ETime  
UTD EBRKTime  
UTD = 0: The signal thresholds and filter coefficients written in the Coe-  
RAM are selected.  
UTD = 1: The signal thresholds and filter coefficients in the ROM are  
selected (default);  
UTD Filter Coefficients and Signal  
Thresholds Selection  
Bit UTD in LREG5  
The center frequency is programmable from 1500 Hz to 2600 Hz. The  
UTD Bandpass Filter Coefficient  
UTD Bandstop Filter Coefficient  
UTD Bandpass Filter Coefficient in the Coe-RAM default center frequency and bandwidth (in the ROM) are 2100 Hz and 60  
Hz respectively.  
The center frequency is programmable from 1500 Hz to 2600 Hz. The  
UTD Bandstop Filter Coefficient in the Coe-RAM default center frequency and bandwidth (in the ROM) are 2100 Hz and  
230 Hz respectively.  
Programmable from 30 dBm to 0 dBm in minimum steps of 0.2 dBm. The  
default value (in the ROM) is 6 dBm.  
Programmable from 30 dBm to 0 dBm in minimum steps of 0.2 dBm. The  
default value (in the ROM) is 18 dBm.  
UTD Signal Ceiling Threshold  
UTD Signal Floor Threshold  
UTDthld_Ceiling in the Coe-RAM  
UTDthld_Floor in the Coe-RAM  
36  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
as a server for three external calling partners (B, C and D) to hold a  
conference with each other. When an internal conference mode is  
selected (GREG7: CONF_EN=1), a conference can be held between an  
internal calling partner (S) and two external calling partners (B and C).  
The internal calling partner is a subscriber connected to one of the four  
channels of the local CODEC. The external calling partners do not need  
any conference facility, for the chipset performs all the functions required  
by a conference for them.  
3.8  
THREE-PARTY CONFERENCE  
3.8.1  
INTRODUCTION  
The RSLIC-CODEC chipset provides a three-party conference  
facility on the PCM interface in MPI mode only. With this facility, either an  
external three-party conference or an internal three-party conference  
can be held without additional hardware.  
Figure - 20 shows the conference block diagram. When an external  
conference mode is selected (GREG7: CONFX_EN=1), the chipset acts  
PCM Highway1  
PCM Highway2  
C
B
D
D
C
B
A
A
X4  
R1  
X2  
X3  
R4  
R3  
R2  
X1  
+
G
G
+
+
-
+
-
-
G
+
+
1
CONF_EN=0  
0
0
CONF_EN=0  
1
Subscriber S  
G:  
Gain Stage (Gain Factor) programmed by GREG8  
4 time slots in transmit PCM highway  
4 time slots in receive PCM highway  
External calling partners  
X1 - X4:  
R1 - R4:  
A, B, C, D:  
S:  
Internal calling partner, which is connected to one of the four channels of the local CODEC.  
Figure - 20 Conference Block Diagram  
The three-party conference facility consists of adders, gain stages,  
PCM configuration registers and a conference control register. The voice  
data in the receive time slots of any two partners is added by the adder  
and sent to the transmit time slot of the third partner. The registers  
GREG9, GREG11 and GREG13 are used to select transmit PCM  
highway and time slot for the three partners. The registers GREG10,  
GREG12 and GREG14 are used to select receive PCM highway and  
time slot for the three partners. To avoid overflow of the sum signals, a  
programmable gain stage (G) is used. The gain is programmed by  
GREG8. The CONF_EN and CONFX_EN bits in GREG7 are used to  
select the internal and external conferences respectively. If internal  
conference is selected, the CONF_CS[1:0] bits in GREG7 are used to  
select one of the four channels of the local CODEC to attend the  
conference.  
voice data can be transferred in a three-party conference. If compressed  
data format is selected, at least 7 time slots are needed in the transmit/  
receive PCM highway to perform a three-party conference and use the  
four local channels at the same time (three time slots for partners B, C  
and D, four time slots for local Channel 1 to 4). So the lowest BCLK  
frequency should be 512 kHz, corresponding to 8 time slots available.  
3.8.2  
PCM INTERFACE CONFIGURATION  
The PCM interface can be configured to work in different mode as  
shown in Table - 11. The P_DOWN bit in LREG6 is used to power down  
the specify channel of the CODEC. When all four channels of the  
chipset are powered down, no data is transferred via the PCM highways.  
The P_DOWN bit together with the CONF_EN and CONFX_EN bits  
control the conference behavior and the PCM line drivers.  
Both A/µ-law compressed (8-bit) and linear (16-bit 2’s complement)  
37  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Table - 11 Conference Mode  
Configuration Bits  
Receive Time Slots  
Transmit Time Slots  
P_DOWN CONF_EN CONFX_EN  
(LREG6) (GREG7) (GREG7)  
Mode  
R1  
R2  
R3  
R4  
X1  
X2  
X3  
X4  
Subscriber S  
PCM Off  
PCM Active  
1
0
1
0
0
0
0
0
1
-
A
-
-
-
-
-
-
-
Off  
S
Off  
Off  
Off  
Off  
Off  
Off  
Off  
A
External Conference  
B
C
D
Off  
G(C+D)  
G(B+D)  
G(B+C)  
Off  
ExternalConference  
+ PCM Active  
0
0
0
1
1
0
A
-
B
B
C
C
D
-
S
G(C+D)  
G(C+S)  
G(B+D)  
G(B+S)  
G(B+C)  
Off  
A
Internal Conference  
Off  
G(B+C)  
• PCM Off  
• External Conference + PCM Active  
As in the external conference mode, any external three-party  
conference is supported in this mode. At the same time, if the channels  
of the local CODEC are powered on (active), the subscribers connected  
to the corresponding channels can make normal phones calls.  
• Internal Conference  
When the chipset is just reset, or in the power down state, no data is  
transferred via the PCM highways. Also when selecting new time slots,  
it's recommended to switch off the PCM line drivers by setting the  
corresponding P_DOWN bit to 1, CONF_EN bit and CONFX_EN bit to  
0.  
• PCM Active  
If the subscriber S is one of the conference partners, the internal  
conference mode should be selected. Then, A three-party conference  
can be held between the internal partner S and the external partners B  
and C. In this mode, the CODEC channel which the partner S is  
connected must be powered on.  
This is the normal operating mode without conference. Only time  
slots R1 and X1 are used. Voice data is transferred from an external  
subscriber A to an internal subscriber S.  
• External Conference  
In this mode the chipset acts as a conferencing server for  
subscribers B, C and D. These three partners may be controlled by any  
device connected to the PCM highways. To reduce the power  
consumption, the channels of the local CODEC can be powered down if  
they are not being used.  
3.8.3  
CONTROL THE ACTIVE PCM CHANNELS  
Table - 12 shows the register configuration for the transmit PCM  
channels. For details refer to “4.1.2 PCM Interface” on page 51.  
Table - 12 Active PCM Channel Configuration Bits  
Control Bits  
Transmit PCM Time Slot  
P_DOWN  
(LREG6)  
CONF_EN  
(GREG7)  
CONFX_EN  
(GREG7)  
L_CODE  
(GREG3)  
X1  
X2  
X3  
X4  
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-
-
-
-
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PCM  
-
-
-
-
HB LB  
-
-
-
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
-
-
PCM  
HB LB  
-
-
-
-
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
PCM  
HB LB  
-
PCM  
HB LB  
-
-
PCM  
HB LB  
38  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
NOTES:  
In Table - 11 and Table - 12:  
1. The ‘P_DOWN’ bit (in register LREG6) is used to power down the corresponding channel of the CODEC: P_DOWN = 1, power down; P_DOWN = 0, power on.  
2. The ‘L_CODE’ bit (in register GREG3) is used to select the PCM data format: L_CODE = 1, linear code; L_CODE = 0, A/µ-law compressed code.  
3. 'PCM' means PCM compressed data (A-law/µ-law).  
4. HB and LB represent the high byte and low byte of the linear data respectively.  
5. Modes in rows with gray background are for testing purpose only.  
39  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LEVEL METER  
3.9.4  
3.9  
ITDF  
An on-chip level meter together with the signal generators mentioned  
accomplishes all test and diagnosis functions. Figure - 21 on the  
following page shows the entire level meter block diagram.  
3.9.1  
INTRODUCTION  
Subscriber lines are often affected by many types of failures, e.g.,  
short circuits, broken lines, leakage currents, noise etc. Service  
providers must be able to perform line tests and respond quickly if there  
are any failures.  
Traditional line cards solutions usually need external relays and test  
equipment to accomplish line tests. The RSLIC-CODEC chipset  
provides integrated test and diagnosis functions (ITDF) that can monitor  
and diagnose line faults and line card device failures without test relays  
or test equipment. With the ITDF implemented, the chipset increases the  
test possibilities, reduces the testing time and cost and provides more  
flexibility for system manufacturers and service providers over traditional  
solutions.  
3.9.4.1  
Level Meter Source Selection  
The level meter is shared by all four channels. The LM_CS[1:0] bits  
in register GREG16 select one of the channels for level metering. For  
each channel, there are one AC signal source and ten DC signal  
sources to be selected. The LM_SRC and DC_SRC bits in register  
LREG8 and the LM_SEL[3:0] bits in register LREG9 make the selection.  
See Table - 13 for details.  
Table - 13 Level Meter Source Selection  
LM_SRC DC_SRC LM_SEL[3:0]  
Level Meter Source  
AC signal in transmit path (VTAC)  
Digital DC signal  
1
0
0
0
0
0
0
0
0
0
0
x
0
1
1
1
1
1
1
1
1
1
xxxx  
xxxx  
0000  
0100  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
3.9.2  
DIAGNOSIS AND TEST FUNCTIONS  
A set of signal generators and features are implemented in the  
chipset to accomplish various diagnosis functions. The CODEC  
generates an appropriate test signal, applies it to the loop, measures the  
resulting voltage or current signal level and reports the result to a master  
microprocessor. All the tests can be initiated by the microprocessor and  
results can be read back very easily. By monitoring the subscriber loop,  
the ITDF might prevent any problems caused by the subscriber line or  
line equipment from affecting the service.  
DC voltage on VTDC (default)  
DC output voltage on DCN-DCP  
DC voltage on VL  
Voltage on IO3  
Voltage 0n IO4  
Voltage on RTIN  
The chipset can accomplish the following test and measurement  
functions:  
VDD/2  
Loop resistance  
Leakage current Tip/Ring  
Leakage current Tip/GND  
Leakage current Ring/GND  
Ringer capacitance  
Line capacitance  
Line capacitance Tip/GND  
Line capacitance Ring/GND  
External voltage measurement Tip/GND  
External voltage measurement Ring/GND  
External voltage measurement Tip/Ring  
Measurement of ringing voltage  
Measurement of line feed current  
Measurement of supply voltage VDD of the CODEC  
Measurement of transversal and longitudinal currents  
Offset voltage (VCM is selected)  
Voltage on IO4-IO3  
Attention: The VTDC is selected as the level meter source by  
default. When the CODEC works in active mode, it automatically adjusts  
the DC feeding according to the DC voltage on the VTDC pin. So,  
selecting inputs VL, IO3, IO4, IO3-IO4, DCN-DCP or VDD/2 as the level  
meter source may disturb the DC feeding regulation and cause  
problems in the DC loop. To avoid this, users can freeze the output of  
the DC loop before selecting these inputs as the sources by setting the  
ACTIVE bit in LREG6 to 0.  
• AC Level Meter  
If the LM_SRC bit in register LREG8 is set to 1, the AC signal in the  
transmit path (VTAC) is selected for level metering.  
3.9.3  
INTEGRATED SIGNAL GENERATORS  
The AC level meter can measure the voice signal at 8 kHz while the  
active voice signal is being processed (see Figure - 21). After being pre-  
filtered, A/D converted and decimated, the signal can be filtered by a  
programmable filter. The LM_FILT bit LREG8 determines whether the  
filter is enabled. If the filter is enabled, the LM_NOTCH bit in LREG8  
determines which filter characteristic (notch or bandpass) is selected.  
The signal generators available on the chipset are as follows:  
Constant DC voltage generation (programmable ringing DC offset  
voltages);  
Two independent tone generators (TG1 and TG2) per channel  
(used to generate DTMF signal and various test tones. Please  
refer to “3.7.1 Tone Generator” on page 30 for details);  
Ramp generator (used for capacitance measurement, refer to  
page 47 for details);  
Ring generator (used to generate an internal balanced ringing  
signal. Refer to “3.4.1.1 Internal Ringing Generation” on page 23  
for details).  
LM_FILT = 0:  
LM_FILT = 1:  
the filter is disabled (normal operation);  
the filter is enabled;  
LM_NOTCH = 0: notch filter characteristic is selected;  
LM_NOTCH = 1: bandpass filter characteristic is selected.  
The filter coefficients can be from the Coe-RAM or from the ROM, as  
selected by the LM_N and LM_B bits in LREG5.  
LM_N = 0:  
the coefficient in the Coe-RAM is used for the  
notch filter;  
40  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LM_N = 1:  
LM_B = 0:  
LM_B = 1:  
the coefficient in the ROM is used for the notch  
filter;  
the coefficient in the Coe-RAM is used for the  
bandpass filter;  
the coefficient in the ROM is used for the  
bandpass filter;  
from 300 Hz to 3400 Hz. The default center frequency is 1014 Hz. The  
quality factor (Q) is fixed to 5. The filter coefficients are automatically  
calculated by a software (Cal74) provided by IDT. When users input the  
center frequency, this software will calculate the coefficient for the notch  
or bandpass filter. By loading the coefficients to the Coe-RAM of the  
CODEC, the filter characteristic can meet the requirements. Refer to  
Table - 23 on page 62 for the Coe-RAM mapping.  
The center frequency of the notch/bandpass filter is programmable  
A/D  
2 MHz  
Bandpass/  
Notch Filter  
Filter  
Decimation  
VTAC  
Bits LM_FILT and LM_NOTCH in LREG8  
Bits LM_B and LM_N in LREG5  
LM bandpass filter coefficient  
LM notch filter coefficient  
AC Path  
DC Path  
DCN-DCP  
VTDC  
VL  
Bit DC_OFT in LREG4  
Word DC Offset in the Coe-RAM  
Offset  
Register  
MUX  
IO3  
From Transmit  
A/D  
1 MHz  
IO4  
MUX  
Filter  
Decimation  
Bit LM_SRC in LREG8  
VDD/2  
VCM  
MUX  
From Receive  
VRDC  
RTIN  
Digital DC signal  
IO4-IO3  
Bit DC_SRC in LREG8  
Bits LM_SEL[3:0] in LREG9  
MUX  
CHANNEL1  
CHANNEL2  
CHANNEL3  
CHANNEL4  
Bits LM_CS[1:0]  
in LREG10  
Bits LM_TH[2:0]  
in LREG10  
Threshold  
Register  
Bit OTHRE in LREG10  
Bit LM_OK in LREG21  
Comparator  
Result  
Register  
Shift  
Factor  
16/1  
Rectifier  
Integrator  
Bits LMRL[7:0] in GREG17  
Bits LMRH[7:0] in GREG18  
Bit LM_GF in  
LREG10  
Bit LM_RECT in  
LREG10  
Bits LM_EN and LM_ONCE in GREG16  
Bits LM_CN[10:0] in GREG15 and GREG16  
Bits K[3:0] in LREG9  
Figure - 21 Level Meter Block Diagram  
Measurement” on page 49 for details.  
3.9.4.2 Level Meter Gain Filter and Rectifier  
• DC Level Meter  
If the LM_SRC bit in register LREG8 is set to 0, the DC level meter is  
selected to perform the measurement. The DC signal source can be  
from transmit or receive path depending on the DC_SRC bit in register  
LREG8:  
The selected signal from the AC or DC path is further processed by a  
programmable digital gain filter. The additional gain factor is either 1 or  
16 depending on the LM_GF bit in register LREG10:  
DC_SRC = 0: DC signal (digital) from receive path is selected;  
DC_SRC = 1: DC signal from transmit path is selected.  
There are a total of nine DC signal sources in the transmit path. They  
are specified by the LM_SEL[3:0] bits in register LREG9. Refer to Table  
- 13 for details.  
As Figure - 21 shows, the selected signal from DC transmit path is  
filtered, A/D converted and decimated. The effective sampling rate after  
the decimation stage is 8 kHz. The Offset Register here is used to  
compensate for the current and voltage offset errors. See “3.9.6.1 Offset  
Current Measurement” on page 45 and “3.9.6.7 Voltage Offset  
LM_GF = 0:  
LM_GF = 1:  
No additional gain factor;  
Additional gain factor of 16.  
The LM_GF bit should be set to 0 unless the tested signal is small  
enough.  
A rectifier follows to change the minus signal to plus signal. It can be  
enabled or disabled by the LM_RECT bit in register LREG10:  
LM_RECT = 1: rectifier enabled;  
LM_RECT = 0: rectifier disabled.  
41  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
3.9.4.3 Level Meter Integrator  
INDUSTRIAL TEMPERATURE RANGE  
after the LM_EN bit in register GREG16 is set to 1. When the count  
number is reached, which means that once integration is finished, the  
LM_OK bit in LREG21 will be set to 1 and an interrupt will be generated.  
The next integration starts right after the previous integration is finished,  
and the LM_OK bit will be automatically reset after 125 µs. The  
integrator runs continuously in this way and will not stop unless the  
LM_EN bit is set to 0. Figure - 22 shows the continuous measurement  
sequence.  
An integrator is used to accumulate and sum up the signal values  
over a preset period. The accumulation period (count number) is  
programmable from 0 to 255.875 ms in steps of 0.125 ms, by the bits  
LM_CN[10:0] in registers GREG15 and GREG16. The integrator can be  
configured to run once or continuously by the LM_ONCE bit in GREG16:  
LM_ONCE = 0: integrator runs continuously;  
LM_ONCE = 1: integrator runs once.  
In continuous mode, the integrator starts to accumulate the samples  
GREG16: LM_ONCE = 0  
GREG16: LM_EN  
Int. Period  
Int. Period  
Int. Period  
Int. Period  
125µs  
125µs  
125µs  
LREG21: LM_OK  
Read Result  
Read Result  
Read Result  
GREG17 & GREG18 GREG17 & GREG18 GREG17 & GREG18  
Figure - 22 Continuous Measurement Sequence (AC & DC Level Meter)  
In single mode, the integrator works only once after each initiation  
(LM_EN = 1). Once the integration is finished, the LM_OK bit will be set  
to 1 and will not be reset until the LM_EN bit is set to 0. To start a new  
integration, the LM_EN bit must be changed from 0 to 1. The single  
measurement sequence is illustrated in Figure - 23.  
GREG16: LM_ONCE = 1  
Start New Measurement  
GREG16: LM_EN  
Int. Period  
Int. Period  
LREG21: LM_OK  
Read Result  
(GREG17 & GREG18)  
Figure - 23 Single Measurement Sequence (AC & DC Level Meter)  
42  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Table - 15 Shift Factor Selection  
In both continuous and single modes, the level meter result LM  
Value  
is sent to registers GREG17 & GREG18 after every integration period.  
K[3:0] bits in LREG9  
Shift Factor  
To calculate the measured signal level, a factor LM  
is defined as:  
Result  
KINT = 1  
0000  
0001  
LM  
Value  
LM  
=
----------------------  
KINT = 1/2  
Result  
32768  
KINT = 1/4  
KINT = 1/8  
0010  
The number of samples N  
for the integrator is calculated by:  
Samples  
0011  
N
= LM_CN  
Samples  
KINT = 1/16  
KINT = 1/32  
KINT = 1/64  
KINT = 1/128  
KINT = 1/256  
KINT = 1/512  
KINT = 1/1024  
KINT = 1/2048  
0100  
Where, LM_CN is the level meter count number (set by bits  
LM_CN[10:0] in registers GREG15 & GREG16).  
0101  
0110  
Then the signal level can be calculated by the following formula:  
0111  
π
1000  
----------------------------------------------  
Udbm0 = 20 × log LM  
×
+ 3.14  
Result  
2 × K × N  
INT  
Samples  
1001  
Where, K is the selected shift factor. Refer to “3.9.4.5 Level Meter  
INT  
1010  
Shift Factor” for details.  
1011 to 1111  
3.9.4.4  
Level Meter Result Register  
3.9.4.6  
Level Meter Threshold Setting  
The level meter result is a 16-bit 2's complement. The low byte and  
high byte of it are stored in registers GREG17 and GREG18  
respectively. Table - 14 shows the range of the result value.  
Once the level meter result is latched in the result registers, it will be  
compared with a programmable threshold. If the absolute value of the  
result exceeds the threshold, the OTHRE bit in register LREG10 will be  
set to 1.  
Table - 14 Level Meter Result Value Range  
This threshold is a percentage value of the full scale (see Table - 14).  
It is programmed by the LM_TH[2:0] bits in LREG10. Refer to Table - 16  
for details.  
Negative Value Range  
Full scale  
Positive Value Range  
+ Full scale  
0x8000  
0xFFFF  
0
0
0x7FFF  
+ 32768  
Table - 16 Level Meter Threshold Setting  
32768  
1  
LM_TH[2:0] in LREG10  
Threshold  
LM_TH[2]  
LM_TH[1]  
LM_TH[0]  
3.9.4.5  
Level Meter Shift Factor  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0%  
As the level meter result is a 16-bit 2's complement while the  
integration width is 27 bits, a shift factor is necessary to avoid generating  
an overflow in result registers and make the results with maximum  
12.5%  
25.0%  
37.5%  
50.0%  
62.5%  
75.0%  
87.5%  
accuracy. The shift factor K is programmed by register LREG9. See  
INT  
Table - 15 for details.  
43  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Table - 17 sums up the registers and Coe-RAM locations used for the  
level meter.  
Table - 17 Registers and Coe-RAM Locations Used for the Level Meter  
Parameter  
Register Bits/Coe-RAM Words  
Notes  
The LM_CS[1:0] bits determine the signal from which channel to be level  
metered.  
Level meter channel selection LM_CS[1:0] bits in GREG16  
LM_SRC and DC_SRC bits in LREG8  
LM_SEL[3:0] bits in LREG9  
Level meter source selection  
Refer to Table - 13 for details.  
Refer to Table - 15 for details.  
Level meter shift factor selection K[3:0] bits in LREG9  
Level meter count number  
The LM_CN[10:0] bits is programmable from 0 to 7FFH, corresponding to the  
integration time of 0.125 ms to 255.875 ms.  
LM_CN[10:0] bits in GREG15 & GREG16  
(integration time) selection  
LMRL[7:0] bits in GREG17 (low byte)  
LMRH[7:0] bits in GREG18 (high byte)  
Level meter result  
See Table - 14 for details.  
Threshold selection: LM_TH[2:0] bits in LREG10 Refer to Table - 16 for details on threshold selection. Once the selected threshold  
Over threshold indication: OTHRE bit in LREG10 is exceeded, the OTHRE bit will be set to 1.  
Level meter threshold  
LM_FILT = 0: bandpass/notch filter is disabled;  
Level meter bandpass/notch  
filter configuration  
LM_FILT = 1: bandpass/notch filter is enabled;  
LM_NOTCH = 0: notch filter characteristic is selected;  
LM_FILT and LM_NOTCH bits in LREG8  
LM_NOTCH = 1: bandpass filter characteristic is selected.  
LM_B = 0: The coefficient in the Coe-RAM is selected for the bandpass filter;  
Level meter bandpass/notch  
filter coefficient selection  
LM_B = 1: The coefficient in the ROM is selected for the bandpass filter (default);  
LM_N = 0: The coefficient in the Coe-RAM is selected for the notch filter;  
LM_B and LM_N bits in LREG5  
LM_N = 1: The coefficient in the ROM is selected for the notch filter (default).  
LM Bandpass Filter Coefficient LM Bandpass Filter Coefficient in the Coe-RAM When LM_B = 1, this coefficient will be selected for the bandpass filter.  
LM Notch Filter Coefficient  
Level meter enable  
LM Notch Filter Coefficient in the Coe-RAM  
LM_EN bit in GREG16  
When LM_N = 1, this coefficient will be selected for the notch filter.  
A logic high in this bit starts a level meter measurement while a logic low stops  
the measurement.  
Indication of Level meter  
measurement completed  
LM_OK bit in LREG21  
Once the measurement is finished, the LM_OK bit will be set to 1.  
Level meter gain filter  
configuration  
LM_GF bit in LREG10  
This bit selects a gain factor of 1 or 16 for the level meter gain filter.  
This bit is used to enable or disable the level meter rectifier as required.  
This bit determines whether the integrator works once or continuously.  
Level meter rectifier enable  
LM_RECT bit in LREG10  
LM_ONCE bit in GREG16  
Level meter integrator work  
mode  
DC_OFT = 0: The compensation value in the Coe-RAM is selected for the Offset  
Offset Register in the level  
meter  
DC_OFT bit in LREG4  
word DC Offset in the Coe-RAM  
Register;  
DC_OFT = 1: The default compensation value of 0 is selected for the Offset  
Register.  
44  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
3.9.5  
MEASUREMENT VIA AC LEVEL METER  
Select VTDC and VL to the DC level meter separately (by setting  
bits LM_SEL[3:0] in LREG9 to ‘0000’ and ‘1001’ respectively).  
The value in the Offset Register must be set to 0 (by clearing the  
word/DC Offset in the Coefficient RAM).  
Then the transversal and longitudinal offset currents (ITdc,Off-Err  
and ILdc,Off-Err) can be calculated.  
3.9.5.1  
Current Measurement via VTAC  
In order to measure current via the VTAC pin, all feedback loops  
(impedance matching filters and transhybrid balance filter) should be  
disabled. To simplify the formulas, the programmable receive and  
transmit gain (GTX, FRX, GRR and FRR) are disabled by corresponding  
registers (refer to “3.3.2 Programmable Filters” on page 21 for details).  
Based on this a factor KADAC (gain of analog to digital in AC loop) can be  
defined:  
LMResult  
KADDC × KINT × NSamples  
-----------------------------------------------------------------  
VTdc, Off Err  
VLdc, Off Err  
ITdc, Off Err  
=
=
LMResult  
KADAC = 1  
-----------------------------------------------------------------  
KADDC × KINT × NSamples  
The transversal current IRMS measured at the RSLIC:  
VTdc, Off Err  
--------------------------------  
KITDC  
=
LMResult × π  
IRMS = ------------------------------------------------------------------------------------------------  
KADAC × KINT × NSamples × KITAC × 2 ×  
2
VLdc, Off Err  
LMResult: LMResult = LMValue / 32768  
NSamples: NSamples = LM_CN  
ILdc, Off Err = -------------------------  
KIL  
KINT:  
Value of the shift factor  
KITDC:  
Value of the DC current to voltage converter for  
KITAC:  
Value of the AC current to voltage converter for  
transversal current (RSense is the sense resistance)  
transversal voltage (RSense is the sense resistance)  
2
--  
KITDC  
=
× RSense  
5
KITAC = 8 × RSense  
KIL:  
Value of the current to voltage for longitudinal current  
3.9.5.2  
AC Level Meter Operational State Flow  
KIL = RSense  
The operational state flow for the AC level meter is as the following:  
1. The level meter is in the disable state (LM_EN = 0), the result  
registers (GREG17 & GREG18) are cleared.  
KINT:  
KADDC:  
Value of the shift factor  
Gain of analog to digital conversion in the DC loop  
2. Set the level meter count number (LM_CN[10:0]) in registers  
GREG15 and GREG16.  
1
KADDC = --  
2
3. Enable the level meter (LM_EN =1) and it starts to accumulate  
the samples. When the preset count number is reached, the  
LM_OK bit is set and the accumulation result will be latched into  
the result registers simultaneously. If the result exceeds the  
preset threshold, the OTHRE bit in LREG10 will be set.  
4. If the LM_ONCE bit is 0 (continuous mode), the level meter  
continues to measure the next samples right after one  
measurement is finished, the LM_OK bit is reset after 125 µs.  
5. If the LM_ONCE bit is 1 (single mode), the level meter runs one  
time after the it is initiated and the LM_OK bit will not be reset until  
the LM_EN bit is set to 0.  
3.9.6.2  
Leakage Current Measurement  
The leakage current Tip/Ring, leakage current Tip/GND and leakage  
current Ring/GND can be measured by the DC level meter when the  
RSLIC is in on-hook mode. The following settings are necessary to  
accomplish the leakage current measurement:  
• The RSLIC must be set to Normal Active mode when measuring  
the leakage current Tip/Ring.  
• The RSLIC must be set to Tip Open mode when measuring the  
leakage current Ring/GND.  
• The RSLIC must be set to Ring Open mode when measuring the  
leakage current Tip/GND.  
• Select VTDC to the DC level meter (LREG9: LM_SEL[3:0]= 0000);  
ILeakage can be calculated as shown below:  
3.9.6  
3.9.6.1  
MEASUREMENT VIA DC LEVEL METER  
Offset Current Measurement  
LMResult × 2  
KADDC × KINT × NSamples × KITDC  
ITdc, Off Err ILdc, Off Err  
The current offset error is caused by the current sensor inside the  
RSLIC. The current offset can be measured by the DC level meter. The  
following settings are necessary to accomplish this measurement:  
ILeakage TipIEND = ---------------------------------------------------------------------------- – ---------------------------------------------------------  
2
LMResult × 2  
ITdc, Off Err + ILdc, Off Err  
The RSLIC is set to Normal Active mode (for MPI interface,  
LREG6: SCAN_EN = 1, SM[2:0] = 000; for GCI interface,  
downstream C/I channel: SCAN_EN = 1, SM[2:0] = 000) and the  
loop is on-hook. In this condition, there should be no current  
present, but the current sensor incorrectly indicates a current  
flowing (current offset error).  
ILeakage RingIEND = ---------------------------------------------------------------------------- – ----------------------------------------------------------  
KADDC × KINT × NSamples × KITDC  
2
LMResult × 2  
ILeakage TipIRing = ---------------------------------------------------------------------------- – ITdc, Off Err  
KADDC × KINT × NSamples × KITDC  
45  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
3.9.6.3 Loop Resistance Measurement  
INDUSTRIAL TEMPERATURE RANGE  
Pause mode (for both MPI and GCI interfaces, LREG6: RING = 1,  
RING_EN = 0).  
Select VTDC as the level meter source (LM_SRC = 0; DC_SRC =  
1; LM_SEL[3:0] = 0000);  
Read level meter result registers GREG17 and GREG18.  
Reverse the voltage between Tip and Ring lines by setting the  
REV_POL bit in LREG19 to 1.  
The DC loop resistance can be determined by supplying a constant  
DC voltage (VTRDC) to the Tip/Ring pair and measuring the DC loop  
current via the VTDC pin. The following steps are necessary to  
accomplish the loop resistance measurement:  
Program a certain ring offset voltage (Refer to “3.4.1.1 Internal  
Ringing Generation” on page 23 for details) and apply it to the  
Tip/Ring pair;  
Read level meter result registers GREG17 and GREG18.  
Figure - 25 describes the offset elimination by the differential  
measurement method.  
Set the RSLIC to Normal Active mode (for MPI interface, LREG6:  
SCAN_EN = 1, SM[2:0] = 000; for GCI interface, downstream C/I  
channel: SCAN_EN = 1, SM[2:0] = 000). Set the CODEC to Ring  
Pause mode (for both MPI and GCI interfaces, LREG6: RING = 1,  
RING_EN = 0).  
ITip/Ring  
Select VTDC as the level meter source (LM_SRC = 0; DC_SRC =  
1; LM_SEL[3:0] = 0000);  
Normal Polarity  
The transversal current (ITrans) can be determined by reading the  
level meter result registers (GREG17 and GREG18);  
Based on the known constant output voltage VTRDC and the mea-  
sured ITrans current, the resistance can be calculated. It should be  
noted that the calculated resistance also includes the on board  
sense resistors.  
expected values  
measured values  
dI  
VTip/Ring  
LMResult  
VTRDC  
----------------  
ITrans  
-------------------------------------------------------------------------  
KADDC × KINT × NSamples × KITDC  
RLoop  
=
= VTRDC ⁄  
Offsets  
Uoffset  
Ioffset  
dU  
Figure - 24 shows an example circuit for loop resistance  
measurement.  
Reverse Polarity  
Figure - 25 Differential Resistance Measurement  
Line Card  
line sense signal to be measured  
This differential measurement method eliminates both the current  
offset caused by the RSLIC current sensor and the voltage offset  
caused by the DC voltage output (ring offset voltage). The following  
calculation shows the elimination of both offsets.  
VTDC  
VL  
RPROT RSense  
ILINE  
VTRDC  
RLINE  
RSLIC  
CODEC  
DCP  
VTRDC + VOffset  
IMeasure(normal) = ---------------------------------- + IOffset  
RLoop  
DCN  
RPROT RSense  
VTRDC + VOffset  
IMeasure(reverse) = ------------------------------------- + IOffset  
RLoop  
VTRDC: DC voltage programmed by the Coe-RAM (word RingOffset)  
2 × VTRDC  
IMeasure(normal) IMeasure(reverse) = ----------------------  
RLoop  
Figure - 24 Example for Resistance Measurement  
2 × VTRDC  
RLoop = ------------------------------------------------------------------------ = RLINE + RSense + RPROT  
IMeasure(normal) IMeasure(reverse)  
In order to increase the accuracy of the result, either the current  
offset can be compensated or the measurement can be done  
differentially. The latter eliminates both the current and voltage offsets.  
To measure the loop resistance RLoop differentially, follow the  
sequence below:  
V
offset voltage caused by the DC voltage output;  
offset current caused by the RSLIC current sensor;  
Offset:  
I
Offset:  
3.9.6.4  
Line Resistance Tip/GND and Ring/GND  
Program a certain ring offset voltage and apply it to the Tip/Ring  
pair via the RSLIC;  
Set the RSLIC to Normal Active mode (for MPI interface, LREG6:  
SCAN_EN = 1, SM[2:0] = 000; for GCI interface, downstream C/I  
channel: SCAN_EN = 1, SM[2:0] = 000). Set the CODEC to Ring  
The line resistance Tip/GND and Ring/GND can be measured by  
setting the Ring and Tip lines to high impedance respectively. When one  
line is set to high impedance, the other line is still active and is able to  
supply a known voltage. By measuring the DC transversal current, the  
line impedance can be determined.  
46  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
DC voltage applied to Tip/GND  
Because one line (Tip or Ring) is high impedance, there is only  
current flowing through the other line. This causes the calculated current  
to be half of the actual value. Therefore in either Ring Open or Tip Open  
mode the calculated current must be multiplied by a factor of 2.  
V
V
TGDC:  
RGDC:  
DC voltage applied to Ring/GND.  
3.9.6.5  
Capacitance Measurement  
LMResult × 2  
KADDC × KINT × NSamples × KITDC  
• Ramp Generator  
-------------------------------------------------------------------------  
RTipIGND = VTGDC  
The RSLIC-CODEC chipset integrates a ramp generator to help to  
measure the capacitance. The ramp generator can generate required  
voltage ramps to feed to the Ring and Tip lines. Figure - 26 shows the  
voltage ramp and the voltage levels at the Ring and Tip lines.  
LMResult × 2  
KADDC × KINT × NSamples × KITDC  
-------------------------------------------------------------------------  
RRingIGND = VRGDC  
RSLIC  
GND  
Tip  
Ring  
VDC,END  
VBAT / 2  
VDC,START  
Tip  
Ring  
Programmable Voltage Slope  
VBAT  
Line Current  
LREG8: RAMP_EN  
GREG16: LM_EN  
TRING,DELAY  
Int. Period  
LREG21: LM_OK  
LREG21: RAMP_OK  
Figure - 26 Capacitance Measurement  
The ramp generator is programmable by the Coe-RAM:  
Slope is programmable from 20 to 2000 V/s by word RampSlope;  
Start voltage is programmable from -70 to 70 V by word RingOffset;  
End voltage is programmable from -70 to 70 V by word RampEnd.  
The following settings are necessary to generate a ramp signal:  
1. Set the CODEC operating mode to RAMP (for both MPI and GCI  
interfaces, LREG6: RAMP = 1).  
2. Set the RSLIC operating mode to Internal Ring (for MPI interface,  
LREG6: SCAN_EN = 1, SM[2:0] = 010; for GCI interface,  
downstream C/I channel: SCAN_EN = 1, SM[2:0] = 010).  
3. Select desired ramp start voltage, end voltage and slope  
(LREG5: RG = 1, constant parameters for the ramp are selected;  
LREG5: RG = 0, ramp parameters are programmed by the  
Coefficient RAM, refer to Table - 23 on page 62 for details).  
47  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
4. Enable the ramp generator (LREG8: RAMP_EN = 1).  
ramp generation is finished. An interrupt will be generated  
simultaneously if the ramp mask bit RAMP_M in LREG18 is 0.  
Table - 18 lists the registers and Coe-RAM locations used for ramp  
generation.  
Once the RAMP_EN bit is set to 1, a ramp signal will start from the  
start voltage and increases its voltage following the programmed slope.  
When the voltage of the ramp signal finally reaches the programmed  
end voltage, the RAMP_OK bit in LREG21 will be set to indicate that the  
Table - 18 Registers and Coe-RAM Locations Used for Ramp Generator  
Parameter  
Register Bits/Coe-RAM Words  
Notes  
RG = 0: The ramp slope, start voltage and end voltage in the Coe-RAM are selected.  
RG = 1: The ramp slope, start voltage and end voltage in the ROM are selected (default);  
Ramp Parameters Selection Bit RG in LREG5  
Ramp Start Voltage  
Ramp Slope  
Word RingOffset in the Coe-RAM Programmable from -70 V to 70 V with ±1% tolerance. The default value in the ROM is 7 V.  
Programmable from 20 V/s to 2000 V/s with ±1% tolerance. The default value in the ROM is 300  
Word RampSlope in the Coe-RAM  
V/s.  
Ramp End Voltage  
Word RampEnd in the Coe-RAM  
Bit RAMP in LREG6  
Programmable from -70 V to 70 V with ±1% tolerance. The default value in the ROM is 20 V.  
The ramp signal can only be generated in the RAMP mode (RAMP = 1).  
Ramp Mode Selection  
RAMP_EN = 0: The ramp generator is disabled;  
RAMP_EN = 1: The ramp generator is enabled.  
RAMP_OK = 0: The ramp generation is in progress;  
RAMP_OK = 1: The ramp generation is finished.  
RAMP_M = 0: An interrupt will be generated when the RAMP_OK bit changes from 0 to 1;  
RAMP_M = 1: Interrupts will not be generated when the RAMP_OK bit changes.  
Ramp Generator Enable  
Ramp Over Indication  
Mask bit for RAMP_OK  
Bit RAMP_EN in LREG8  
Bit RAMP_OK in LREG21  
Bit RAMP_M in LREG18  
• Capacitance Measurement  
functionality can be used to measure external voltages. If IO3 and IO4  
pins are connected properly over a voltage divider to the Ring and Tip  
lines, the external voltage supplied to the lines can be measured on  
either IO3 or IO4 pin, or on IO4-IO3 (differential measurement). The  
LM_SEL[3:0] bits in LREG9 select an external voltage to be measured.  
Refer to Table - 13 on page 40 for details.  
The sequence of capacitance measurement is as the following (also  
refer to Figure - 26):  
1. Configure the ramp generator (program the ramp slope, start  
voltage and end voltage);  
2. Select the VTDC voltage to the DC level meter;  
3. Configure the level meter integrator (GREG16: LM_ONCE = 1);  
4. Enable the ramp generator (LREG8: RAMP_EN = 1);  
5. After the current has settled, enable the level meter (GREG16:  
LM_EN = 1).  
Figure - 27 shows the connection and external resistors used for  
external voltage measurements at the Ring and Tip lines.  
VCM  
(Note: The ramp voltage starts at RingOffset and ramps up/down  
until RampEnd is reached. When the integration is finished, the  
result will be stored in registers GREG17 and GREG18).  
6. Read the result in GREG17 and GREG18.  
R2  
R1  
VTDC  
VL  
IO4  
CODEC  
IO3  
RSense  
The actual current can be calculated as: i(t) = CMeasure × dU/dt  
Where, dU/dt is the ramp slope and i(t) is the current measured by  
the level meter. The capacitance then can be calculated as:  
AC  
DC  
External  
Voltage Source  
RSLIC  
Line Card  
DCP  
DCN  
LMResult  
du  
i(t)  
(du) ⁄ (dt)  
RSense  
----------------------------------------------------------------------------  
-----  
------------------------  
CMeasure  
=
=
R3  
R4  
KADDC × KINT × NSamples × KITDC  
dt  
To ensure measurement accuracy, the level meter integrator must be  
enabled after the current has settled to a constant value. The integration  
time is programmed by the LM_CN[10:0] bits in GREG15 and GREG16.  
VCM  
Figure - 27 External Voltage Measurement Principle  
3.9.6.6  
Voltage Measurement  
The DC level meter can measure the following voltages:  
• External voltage Tip/GND (through IO4 pin)  
• External voltage Ring/GND (through IO3 pin)  
• External voltage Tip/Ring (through IO4 -IO3)  
• Ringing voltage (through IO4 -IO3)  
The voltage measured on IO3, IO4 or IO4-IO3 is as follows (with a  
reference to VCM):  
LMResult  
VIO4  
=
+ VCM  
-------------------------------------------------------  
KADDC × KINT × NSamples  
• Supply voltage VDD of the CODEC  
The two programmable IO pins (IO3 and IO4) with analog input  
48  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LMResult  
LMResult × KITDC × RSense  
= ----------------------------------------------------------  
VIO3  
=
+ VCM  
-------------------------------------------------------  
V
mean  
KADDC × KINT × NSamples  
KADDC × KINT × NSamples  
From this result the peak value and the RMS value can be  
calculated.  
LMResult  
VIO4 IO3 = -------------------------------------------------------  
KADDC × KINT × NSamples  
V
mean × π  
2
-------------------------------  
VPeak  
=
In Figure - 27, if R = R , R = R , the external voltage can be  
1
3
2
4
calculated as:  
VPeak  
LMResult × KITDC × RSense × π  
VRMS = ----------- = -----------------------------------------------------------------------------  
R1 + R2  
---------------  
R2  
2
KADDC × KINT × NSamples × 2 × 2  
VTipIGND  
=
× (VIO4 VCM) + VCM  
The power supply of the CODEC (VDD) can be measured by  
selecting the VDD voltage to the DC level meter. When measuring the  
VDD voltage, an internal gain stage (gain = 1/2) is used to divide the  
VDD voltage and provide a limited voltage to the level meter. The VDD is  
measured with a reference to VCM.  
R1 + R2  
---------------  
R2  
VRingIGND  
=
× (VIO3 VCM) + VCM  
R1 + R2  
---------------  
× (VIO4 VIO3)  
VTipIRing  
=
R2  
LMResult  
VDD =  
+ VCM × 2  
-------------------------------------------------------  
KADDC × KINT × NSamples  
When measuring the ringing voltage, the following steps are  
necessary:  
3.9.6.7  
Voltage Offset Measurement  
Set the level meter integration time (LM_CN[10:0] bits in  
The filter, A/D conversion and decimation stages in the DC level  
meter may cause a voltage offset error. When selecting the VCM voltage  
as the source to the DC level meter, the voltage offset can be measured.  
Once the offset value is determined, the offset error can be eliminated  
by writing an appropriate compensation value to the Offset Register  
(word DC Offset in the Coe-RAM).  
GREG15 and GREG16) to be an integer multiple of the period of  
measured ringing signal.  
Clear the Offset Register (word DC Offset in the Coe-RAM).  
Measure the DC content with the rectifier disabled.  
Read the result (LM  
) from the result registers and write the  
Value  
following offset value to the Offset Register:  
3.9.6.8  
Ring Trip Operational Amplifier Offset Measurement  
LMValue  
OFFSET = ----------------------------------  
NSamples × KINT  
In external ringing mode, the sensed ring current signal is fed to an  
operational amplifier integrated in the RSLIC. The amplifier will output a  
signal to the CODEC through the RTIN pin for ring trip detection. But this  
amplifier may introduce an offset and affect the ring trip detection result.  
The offset can be measured by selecting the RTIN as the source to the  
DC level meter. Refer to “3.4.2.1 Ring Trip Detection In External Ringing  
Mode” on page 25 for details.  
Repeat the measurement above should result in LM  
to be  
Value  
zero.  
Perform a new measurement with the rectifier enabled. The result  
is the rectified mean value of the measured signal and can be  
calculated as:  
49  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
CCLK: Serial control interface clock, up to 8.192 MHz  
4
INTERFACE  
CS: Chip select pin. A low level on it enables the serial control  
interface  
The RSLIC-CODEC chipset provides two different types of digital  
CI:  
Serial control data input pin, carrying the data from the  
master microprocessor to the CODEC.  
interfaces to connect the CODEC to the digital network. One is a PCM  
interface combined with a serial Microprocessor Interface (PCM/MPI),  
the other is a General Circuit Interface (GCI). The MPI/GCI pin of the  
CODEC is used to select the interface.  
CO: Serial control data output pin, carrying the data from the  
CODEC to master microprocessor.  
All the data transmitted and received through the MPI interface is  
aligned in an 8-bit byte stream. The data transfer is synchronized to the  
CCLK signal. The contents of CI is latched on the rising edges of CCLK,  
while CO changes on the falling edge of CCLK. Before finish executing a  
command followed by data bytes, the device will not accept any new  
commands from CI. Setting the CS pin to high will terminate the data  
transfer sequence. Figure - 28 and Figure - 29 show the read operation  
timing and write operation timing of the MPI interface.  
MPI/GCI = 0: PCM/MPI interface is selected;  
MPI/GCI = 1: GCI interface is selected.  
4.1  
PCM/MPI INTERFACE  
In PCM/MPI mode, the voice data and control data are separate and  
transmitted via the PCM interface and MPI interface respectively.  
4.1.1  
MPI CONTROL INTERFACE  
The CCLK is the only reference for the CI and CO pins. Its duty and  
frequency may not necessarily be standard.  
In PCM/MPI mode, all the control information including internal  
registers configuring, coefficients programming and RSLIC controlling is  
transferred through the MPI control interface. This interface consists of  
four pins:  
CS  
CCLK  
CI  
7
6
5
4
3
2
1
0
Command  
High "Z"  
CO  
High "Z"  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ID  
Data Byte 1  
Figure - 28 MPI Read Operation Timing  
CS  
CCLK  
CI  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Command  
Data Byte 1  
Data Byte 1  
CO  
High "Z"  
Figure - 29 MPI Write Operation Timing  
50  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
4.1.2 PCM INTERFACE  
INDUSTRIAL TEMPERATURE RANGE  
PCM Clock Configuration  
4.1.2.1  
In PCM/MPI mode, the PCM data (A/µ-law compressed code or  
linear code) is transferred through the PCM interface. The CODEC  
provides two transmit and two receive PCM highways for all four  
channels. The PCM interface consists of eight pins as shown below:  
The PCM interface is flexible with the data rate, clock slope and  
delay period programmable. The data rate can be the same as the  
BCLK (single clock mode) or half of it (double clock mode). This is done  
by setting the DBL_CLK bit in register GREG3 to 0 and 1 respectively.  
The PCM data can be transmitted and received either on the rising edge  
of the BCLK signal or on the falling edge of it. The PCM clock slope is  
selected by the TR_SLOPE[1:0] bits in register GREG3. Refer to Figure  
- 30 for details. The time slots for transmitting and receiving data can be  
offset from the FSC signal by 0 to 7 BCLK period(s). The PCM_OFT[2:0]  
bits in GREG3 are used to set the offset period of the PCM timing.  
FSC:  
BCLK:  
DX1:  
frame synchronization clock  
PCM bit clock  
PCM transmit data highway 1  
PCM receive data highway 1  
PCM data transmit indicator 1, active low  
PCM transmit data highway 2  
PCM receive data highway 2  
PCM data transmit indicator 2, active low  
DR1:  
TSX1:  
DX2:  
DR2:  
TSX2:  
Transmit  
Receive  
FSC  
Programmed by GREG3:  
DBL_CLK = 0  
TR_SLOPE[1:0] = 00  
BCLK  
(Single Clock Mode)  
DBL_CLK = 0  
TR_SLOPE[1:0] = 01  
DBL_CLK = 0  
TR_SLOPE[1:0] = 10  
DBL_CLK = 0  
TR_SLOPE[1:0] = 11  
Bit 7  
Time Slot 0  
DBL_CLK = 1  
TR_SLOPE[1:0] = 00  
BCLK  
(Double Clock Mode)  
DBL_CLK = 1  
TR_SLOPE[1:0] = 01  
DBL_CLK = 1  
TR_SLOPE[1:0] = 10  
DBL_CLK = 1  
TR_SLOPE[1:0] = 11  
Figure - 30 PCM Clock Slope Select Waveform  
51  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
4.1.2.2 Time Slot Assignment  
INDUSTRIAL TEMPERATURE RANGE  
CODEC monitors the input DCL signal to determine which frequency  
(2.048 MHz or 4.096 MHz) is being used. The internal timing will be  
adjusted accordingly so that DU and DD operate at 2.048 MHz rate.  
The CODEC allows both compressed and linear data format coding/  
decoding. The L_CODE bit in GREG3 selects the data format:  
L_CODE = 0: Compressed code (default)  
The PCM data of each channel can be assigned to any time slot of  
the PCM highway. The number of the available time slots is determined  
by the BCLK frequency. If the BCLK frequency is f kHz, the number of  
the time slots that can be used is the result of f (kHz) divided by 64 kHz.  
For example, if the frequency of BCLK is 512 kHz, then a total of eight  
time slots are available. The CODEC accepts any BCLK signals ranging  
from 256 kHz to 8.192 MHz at increment of 64 kHz.  
If the PCM data is A-law or µ-law compressed (8-bit), the voice data  
of one channel occupies one time slot. The TT[6:0] bits in LREG1 select  
the transmit time slot, while the RT[6:0] bits in LREG2 select the receive  
time slot. The THS bit in LREG1 selects the transmit highway (DX1 or  
DX2). The RHS bit in LREG2 selects the receive highway (DR1 or DR2).  
For linear PCM data, which is a 16-bit 2's complement (b13 to b0 are  
data bits, while b15 and b14 are the same as the sign bit b13), one time  
slot group consisting of two successive time slots are needed to contain  
the voice data of one channel. The TT[6:0] bits in LREG1 select the  
transmit time slot group. For example, if the TT[6:0] bits are set to  
‘0000000’, it means that TS0 and TS1 are selected; if the TT[6:0] bits  
are set to ‘0000001’, it means that TS2 and TS3 are selected. The  
RT[6:0] bits in LREG2 select the receive time slot group in the same  
way.  
L_CODE = 1: Linear code  
4.2.1  
COMPRESSED GCI MODE  
In GCI compressed mode, one GCI frame consists of 8 GCI time  
slots. In each GCI time slot, the data upstream interface transmits four  
8-bit bytes. They are:  
Two voice data bytes from the A-law or µ-law compressor of two  
different channels, named channel A and channel B. The compressed  
voice data bytes for channel A and B are 8-bit wide:  
One monitor channel byte, containing the control data/coefficients  
from/to the master device for channel A and B;  
One C/I channel byte, which contains a 6-bit C/I sub-byte together  
with an MX bit and an MR bit. All real time signaling information is  
carried on the C/I sub-byte. The MX (Monitor Transmit) bit and MR  
(Monitor Receive) bit are used for handshaking functions for channel A  
and B. Both MX and MR are active low.  
The transmit logic controls the transmission of data onto the GCI bus.  
The downstream data structure is the same as that of upstream. The  
data downstream interface logic controls the reception of data bytes  
from the GCI bus. The two compressed voice data bytes of the GCI time  
slot are transferred to the A-law or µ-law expansion logic circuit. The  
expanded data is passed through the receive path of the signal  
processor. The Monitor Channel and C/I Channel bytes are transferred  
to the GCI control logic for process.  
Figure - 31 shows the structure of the overall compressed GCI frame.  
In GCI compressed mode, two GCI time slots are required to access  
all four channels of the CODEC. The GCI time slot assignment is  
determined by S1 and S0 pins as shown in Table - 19.  
4.1.2.3  
PCM Highway Selection  
The PCM data of each channel is sent out to the PCM highway on  
the selected edges of the BCLK. The transmit highway (DX1 or DX2) is  
selected by the THS bit in LREG1. The frame sync signal (FSC)  
identifies the beginning (Time Slot 0) of a transmit frame. The PCM data  
is transmitted serially to DX1 or DX2 with MSB first.  
The PCM data from the master processor is received via the PCM  
highway on the selected edges of the BCLK. The receive highway (DR1  
or DR2) is selected by the RHS bit in LREG2. The PCM data is received  
serially from DR1 or DR2 with MSB first. The frame sync signal (FSC)  
identifies the beginning (Time Slot 0) of a receive frame.  
4.2.2  
LINEAR GCI MODE  
4.2  
GCI INTERFACE  
In GCI linear mode, one GCI frame consists of eight GCI time slots  
and each GCI time slot consists of four 8-bit bytes. Four of the eight GCI  
time slots are used as the monitor channel and C/I channel. They have a  
common data structure as follows:  
Two Don’t Care bytes.  
One monitor channel byte, containing the control data/coefficients  
from/to the master device for channel A and B.  
One C/I channel byte, which contains a 6-bit C/I sub-byte together  
with an MX bit and an MR bit. All real time signaling information is  
carried on the C/I sub-byte. The MX (Monitor Transmit) bit and MR  
(Monitor Receive) bit are used for handshaking functions for channel A  
and B. Both MX and MR bits are active low.  
The other four GCI time slots are used to contain the linear voice  
data (a 16-bit 2’s complement number: b13 to b0 are data bits, while b15  
and b14 are the same as the sign bit b13). Each GCI time slot consists  
of four bytes: two bytes for the 16-bit linear voice data of channel A, the  
other two bytes for the 16-bit linear data of channel B.  
The General Circuit Interface (GCI) defines an industry-standard  
serial bus for interconnecting telecommunication ICs for a broad range  
of applications typically ISDN-based applications. The GCI bus  
provides a symmetrical full-duplex communication link containing data,  
control/programming and status channels. Providing data, control and  
status information via a serial channel simplifies the line card layout and  
reduces the cost.  
The GCI interface consists of two data lines and two clock lines as  
follows:  
DU: Data Upstream carries data from the CODEC to the master  
processor  
DD: Data Downstream carries data from the master processor to  
the CODEC  
FSC: Frame Synchronization signal (8 kHz) supplied to the CODEC  
DCL: Data Clock signal (2.048 MHz or 4.096 MHz) supplied to the  
CODEC  
The CODEC sends upstream data to the DU pin and receives  
downstream data via the DD pin. A complete GCI frame is sent  
upstream and received downstream every 125 µs. The Frame Sync  
signal (FSC) identifies the beginning of the transmit and receive frames  
and all GCI time slots are referenced to it. The internal circuit of the  
The GCI time slot assignment is determined by the S1 and S0 pins.  
When S0 and S1 are both low, the linear GCI frame structure is as  
shown in Figure - 32 on page 54.  
In linear operation, for one chip of the four-channel CODEC occupies  
52  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
four GCI time slots (two for voice data and two for C/I and monitor  
channels), the remaining four GCI time slots can be used by another  
chip if you were to tie their control busses together. Hence, for an 8-  
timeslot GCI bus, there are four time slot locations for one CODEC to  
select. See Table - 20 on page 54 for details.  
125 µs  
FSC  
DCL  
TS0  
TS0  
TS1  
TS1  
TS2  
TS2  
TS3  
Detail  
TS3  
TS4  
TS4  
TS5  
TS5  
TS6  
TS6  
TS7  
TS7  
DD  
DU  
Detail  
M M  
R X  
Voice Channel A  
Voice Channel A  
Voice Channel B  
Voice Channel B  
Monitor Channel C/I Channel  
Monitor Channel C/I Channel  
DD  
DU  
M M  
R X  
Figure - 31 Compressed GCI Frame Structure  
Table - 19 Time Slot Selection For Compressed GCI  
S1 = 0, S0 = 0  
CODEC  
S1 =0, S0 = 1  
S1 = 1, S0 = 0  
S1 = 1, S0 = 1  
Voice  
Voice  
Voice  
Voice  
Channel  
Time Slot  
Time Slot  
Time Slot  
Time Slot  
Channel  
Channel  
Channel  
Channel  
1
2
3
4
Time Slot 0  
Time Slot 0  
Time Slot 1  
Time Slot 1  
A
B
A
B
Time Slot 2  
Time Slot 2  
Time Slot 3  
Time Slot 3  
A
B
A
B
Time Slot 4  
Time Slot 4  
Time Slot 5  
Time Slot 5  
A
B
A
B
Time Slot 6  
Time Slot 6  
Time Slot 7  
Time Slot 7  
A
B
A
B
53  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
125 µs  
FSC  
DCL  
TS0  
Detail A  
TS0  
TS1  
TS1  
TS2  
TS3  
TS4  
TS4  
TS5  
TS5  
TS6  
TS7  
TS7  
DD  
DU  
Detail B  
TS2  
TS3  
TS6  
TS0-1 for Monitor and C/I TS2-3 for Linear Voice Data  
Detail A  
DD  
M M  
R X  
Unused  
Unused  
Unused  
Unused  
Monitor Channel C/I Channel  
Monitor Channel C/I Channel  
M M  
R X  
DU  
Detail B  
DD  
16-bit Linear Voice Data for Channel A  
16-bit Linear Voice Data for Channel A  
16-bit Linear Voice Data for Channel B  
16-bit Linear Voice Data for Channel B  
DU  
Figure - 32 Linear GCI Frame Structure  
Table - 20 Time Slot Selection For Linear GCI  
S1 = 0, S0 = 0  
S1 =0, S0 = 1  
CODEC  
Channel  
Monitor and  
C/I Channel  
Voice  
Channel  
Monitor and  
Voice  
Channel  
Time Slot  
Time Slot  
Time Slot  
Time Slot  
C/I Channel  
1
2
3
4
Time Slot 0  
Time Slot 0  
Time Slot 1  
Time Slot 1  
A
B
A
B
Time Slot 2  
Time Slot 2  
Time Slot 3  
Time Slot 3  
A
B
A
B
Time Slot 2  
Time Slot 2  
Time Slot 3  
Time Slot 3  
A
B
A
B
Time Slot 4  
Time Slot 4  
Time Slot 5  
Time Slot 5  
A
B
A
B
S1 = 1, S0 = 0  
S1 = 1, S0 = 1  
CODEC  
Channel  
Monitor and  
C/I Channel  
Voice  
Channel  
Monitor and  
C/I Channel  
Voice  
Channel  
Time Slot  
Time Slot  
Time Slot  
Time Slot  
1
2
3
4
Time Slot 4  
Time Slot 4  
Time Slot 5  
Time Slot 5  
A
B
A
B
Time Slot 6  
Time Slot 6  
Time Slot 7  
Time Slot 7  
A
B
A
B
Time Slot 6  
Time Slot 6  
Time Slot 7  
Time Slot 7  
A
B
A
B
Time Slot 0  
Time Slot 0  
Time Slot 1  
Time Slot 1  
A
B
A
B
54  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
4.2.3 COMMAND/INDICATION (C/I) CHANNEL  
INDUSTRIAL TEMPERATURE RANGE  
Upstream C/I Channel Byte  
4.2.3.2  
The downstream and upstream command/indication (C/I) channels  
are continuously (every frame) carrying I/O information to and from the  
CODEC. Real-time signaling information for the two channels (A & B)  
are transferred via the six C/I bits. The two least significant bits of the C/  
I bytes (MR and MX) are handshaking bits for the monitor channel. The  
CODEC transmits or receives the C/I channel data with the most  
significant bit first.  
The upstream C/I channel byte quickly transfers the most time-critical  
information from the chipset to the master device. The definition of this  
byte is as follows:  
Upstream C/I Channel Byte  
MSB  
LSB  
MX  
INT_CHA HOOKA GNDKA INT_CHB HOOKB GNDKB  
MR  
4.2.3.1  
Downstream C/I Channel Byte  
The six C/I bits in this byte is illustrated below:  
The downstream C/I channel byte is used to control the operating  
mode of the RSLIC. This byte is defined as:  
HOOKA:  
hook state of channel A  
HOOKA = 0: channel A is on-hook  
HOOKA = 1: channel A is off-hook  
Downstream C/I Channel Byte  
MSB  
CA  
LSB  
MX  
HOOKB:  
hook state of channel B  
CB SCAN_EN SM[2] SM[1]  
SM[0]  
MR  
HOOKB = 0: channel B is on-hook  
HOOKB = 1: channel B is off-hook  
This byte is shared by two channels (A & B) to transfer information.  
The CA and CB bits indicate whether the current C/I byte is for Channel A  
or Channel B respectively:  
GNDKA:  
ground-key information of channel A  
GNDKA = 0: no longitudinal current is detected in channel A  
GNDKA = 1: longitudinal current is detected in channel A  
CA = 1: the control information carrying by the SCAN_EN and  
SM[2:0] bits is for Channel A.  
CB = 1: the control information carrying by the SCAN_EN and  
SM[2:0] bits is for Channel B.  
GNDKB:  
ground-key information of channel B  
GNDKB = 0: no longitudinal current is detected in channel B  
GNDKB = 1: longitudinal current is detected in channel B  
The SM[2:0] bits are used to configure the operating mode of the  
respective RSLIC. The SCAN_EN bit in this byte determines whether  
the corresponding RSLIC will be accessed. Refer to “6.1.2 RSLIC  
Operating Modes” on page 89 for detailed information. By properly  
program the downstream C/I channel byte, users can configure the  
operating mode of every channel as required.  
INT_CHA:  
INT_CHB:  
interrupt information of channel A  
interrupt information of channel B  
The valid polarity of INT_CHA and INT_CHB depends on the  
INT_POL bit in GREG24:  
INT_POL = 0: active low (default)  
INT_POL = 1: active high  
55  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
4.2.4  
GCI MONITOR TRANSFER PROTOCOL  
and MX per direction (the MR and MX bits are contained in the C/I  
channel bytes), data is transferred between the upstream and  
downstream devices in a complete handshake procedure. Figure - 33  
shows the monitor channel operating diagram.  
4.2.4.1  
Monitor Channel Operation  
In GCI mode, upstream processors access the registers and RAM of  
the chipset via the monitor channel. Using two monitor control bits MR  
Master Device  
CODEC  
MX  
MX  
Monitor  
Receiver  
Monitor  
Transmitter  
MR  
MR  
DD  
DU  
MR  
MX  
MR  
Monitor  
Transmitter  
Monitor  
Receiver  
MX  
Figure - 33 Monitor Channel Operation  
The transmission of the monitor channel is operated on a pseudo-  
asynchronous basis:  
sending out an active MR bit (‘0’). The data transmission is repeated  
each 125 µs frame (minimum is one repetition). During this time the  
Monitor Transmitter keeps detecting the MR bit.  
Flow control, means in the form of transmission delay, can only take  
place when the transmitter’s MX bit and the receiver’s MR bit are in  
active state.  
On the receiver side, since the monitor data can be received at least  
twice (in two consecutive frames), a last look function is able to check for  
data errors. If two different bytes are received the receiver will wait for  
the receipt of two identical successive bytes.  
On the transmitter side, a collision resolution mechanism is  
implemented to avoid two or more devices are trying to send data at the  
same time. The mechanism is realized by looking for the inactive (‘1’)  
phase of the MX bit and making a per bit collision check on the  
transmitted monitor data (check whether transmitted ‘1’s are on the DU/  
DD line. The DU/DD line are open drain).  
Any abort leads to a reset of the CODEC command stack, and the  
device is ready to receive new commands.  
To obtain a maximum speed data transfer, the transmitter anticipates  
the falling edge of the receivers acknowledgment.  
Due to the inherent programming structure, duplex operation is not  
possible. It is not allowed to send any data to the CODEC while  
transmission is active.  
Note that each byte on the monitor channel must be sent twice at  
least according to the GCI monitor handshake procedure.  
Refer to Figure - 34 and Figure - 35 for details about monitor  
handshake procedure.  
Data transfer (bits) on the bus is synchronized to FSC;  
Data flow (bytes) are asynchronously controlled by the  
handshake procedure.  
For example: Data is placed onto the DD Monitor Channel by the  
Monitor Transmitter of the master device (DD MX bit is activated and set  
to 0). This data transfer will be repeated within each frame (125 µs rate)  
until it is acknowledged by the CODEC Monitor Receiver by setting the  
DU MR bit to 0. Because of the handshaking protocol required for  
successful communication, the data transfer rate using the monitor  
channel is less than 8 kbit/s.  
4.2.4.2  
Monitor Handshake Procedure  
The monitor channel works in three states:  
I. Idle state: Both the MR and MX bits are inactive (‘1’) during two or  
more consecutive frames signals an idle state on the monitor channel or  
an end of message (EOM);  
II. Sending state: The MX bit is activated ('0') by the Monitor  
Transmitter, together with a data byte (can be changed) on the monitor  
channel;  
III. Acknowledging: The MR bit is set to active state ('0') by the  
Monitor Receiver, together with a data byte remaining in the monitor  
channel.  
A start of transmission is initiated by a monitor transmitter by sending  
out an active MX bit (‘0’) together with the first byte of data to be  
transmitted in the monitor channel. This state remains until the  
addressed monitor receiver acknowledges the receipt of data by  
56  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
MR or MXR  
MXR  
MR and MXR  
Idle  
MX = 1  
Wait  
MX = 1  
Abort  
MX = 1  
Initial  
State  
MR and MXR  
MR and RQT  
MR  
MR and RQT  
MR  
1st Byte  
MX = 0  
EOM  
MX = 1  
MR and RQT  
MR  
nth Byte ACK  
MX = 1  
MR  
MR and RQT  
MR and RQT  
Wait for ACK  
MX = 0  
CLS/ABT  
Any State  
MR:  
MR bit received on DD line  
MX:  
MX bit calculated and expected on DU line  
MX bit sampled on DU line  
Collision within the monitor data byte on DU line  
Request for transmission from internal source  
Abort request/indication  
MXR:  
CLS:  
RQT:  
ABT:  
Figure - 34 State Diagram of the Monitor Transmitter  
57  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Idle  
MR = 1  
MX  
MX and LL  
Initial  
State  
MX  
MX  
1st Byte REC  
MR = 0  
Abort  
MR = 1  
ABT  
MX  
Any  
State  
MX  
MX  
MX  
MX and LL  
Byte Valid  
MR = 0  
Wait for LL  
MR = 0  
MX and LL  
MX and LL  
MX  
MX and LL  
MX  
MX and LL  
New Byte  
MR = 1  
nth Byte REC  
MR = 1  
Wait for LL  
MR = 0  
MR:  
MX:  
LL:  
MR bit calculated and transmitted on DU line  
MX bit received data downstream (DD line)  
Last look of monitor byte received on DD line  
Abort indication to internal source  
ABT:  
Figure - 35 State Diagram of the Monitor Receiver  
By implementing proper register/RAM commands through the GCI  
monitor channel, users can flexibly control the RSLIC-CODEC chipset.  
The format and the addressing method of the register/RAM in both GCI  
mode and MPI mode are similar. Refer to “5.2 Register/RAM  
Commands” on page 59 for details.  
directly. Only two external resistors are needed to connect TIS to TIP  
and connect RIS to RING respectively, no other components are  
required in the POTS interface.  
4.4  
RSLIC AND CODEC INTERFACE  
As Figure - 49 shows, the RSLIC can be connected directly to the  
CODEC.  
4.3  
ANALOG POTS INTERFACE  
The interface between an analog Plain Old Telephone Service  
(POTS) and a RSLIC is shown in Figure - 49 on page 104. The RSLIC  
connects to the POTS interface through the TIP and RING pins. Over  
voltage and over current protectors connect to the TIP and RING pins  
The RSLIC can work in different modes that are determined by the  
CODEC through the SLIC mode control pins CSn and M1 to M3. Refer  
to “6 Operational Description” on page 87 for details.  
58  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
5.1.2.2  
Identification Command for GCI Programming  
5
PROGRAMMING  
In order to distinguish different devices unambiguously by software, a  
two byte identification command of 8000H is defined for analog line GCI  
devices:  
5.1  
OVERVIEW  
Programming the chipset is realized via the serial microprocessor  
interface (MPI mode) or GCI monitor channel (GCI mode). In MPI mode,  
the command or data is transferred via the CI/CO pin. In GCI mode, the  
command or data is transferred via the DD/DU pin.  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Each device will respond with its specific identification code. For the  
IDT82V1074, this two-byte identification code will be 8082H.  
5.1.1  
MPI PROGRAMMING  
5.1.1.1  
Broadcast Mode for MPI Programming  
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
A broadcast mode is provided for MPI write-operation (not allowed  
for read-operation). Each channel has its own Channel Enable bit  
(CH_EN[0] to CH_EN[3] in GREG4 for Channel 1 to Channel 4,  
respectively) to allow individual channel programming. If two or more  
CH_EN bits are set to 1 (enable), the corresponding channels are  
enabled and can receive the programming information simultaneously.  
Therefore, a broadcast mode can be implemented by simply enabling all  
of the channels in the device. The broadcast mode is very useful when  
initializing a large system, because the registers and RAM locations of  
four channels can be configured by one operation.  
5.2  
REGISTER/RAM COMMANDS  
5.2.1  
REGISTER/RAM COMMAND FORMAT  
For both MPI and GCI modes, the command format is as the  
following:  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
5.1.1.2  
Identification Code for MPI Programming  
R/W  
CT  
Address  
In MPI mode, an identification code is used to distinguish the  
CODEC from other devices in the system. In read operations, before  
outputting other data bytes, the CODEC will first output an identification  
code of 81H indicating that the following data is from the CODEC.  
R/W:  
Read/Write Command bit  
b7 = 0:  
b7 = 1:  
Read Command  
Write Command  
5.1.2  
GCI PROGRAMMING  
CT:  
Command Type  
b6 b5 = 00: Local Register Command  
b6 b5 = 01: Global Register Command  
5.1.2.1  
Program Start Byte for GCI Programming  
b6 b5 = 10: FSK-RAM Command (one word operation)  
b6 b5 = 11: Coe-RAM Command (eight words operation)  
Address: b[4:0] specify the register(s) or the location(s) of RAM to  
be addressed.  
In GCI mode, the CODEC exchanges status and control information  
with the master processor through the monitor channel. The messages  
transferred in the monitor channel have different data structures. Since  
one monitor channel is shared by two voice data channels (channel A  
and channel B) to transfer status or control information, a Program Start  
(PS) byte is necessary to indicate the source (upstream) channel or the  
destination (downstream) channel during data transferring. For a  
complete GCI command operation, messages transferred via the  
monitor channel always start with a PS byte as follows:  
5.2.2  
ADDRESSING THE LOCAL REGISTERS  
In both MPI and GCI modes, the local registers are used to configure  
each individual channel. Up to 32 local registers are provided for each  
channel. The local registers are accessed by corresponding local  
commands.  
b7  
1
b6  
0
b5  
0
b4  
b3  
0
b2  
0
b1  
0
b0  
1
• MPI Mode  
A/B  
In MPI mode, when addressing a local register, the Channel Enable  
Register (GREG5) must be first set to specify one or more channels to  
be addressed. For example, if the CH_EN[0] bit in GREG4 is set to 1,  
the local register(s) of channel 1 will be addressed. The CH_EN[1] to  
CH_EN[3] bits enable/disable the local registers of channel 2 to channel  
4, respectively, in the same way.  
In MPI mode, the CODEC provides an automatic countdown  
mechanism for addressing the local registers. When executing a local  
command, the CODEC will automatically count down from the address  
specified in b[4:0] to the address of 0. For example, if b[4:0] = 00001, the  
local register with the address of ‘00001' will be accessed first, then the  
address will be counted down to ‘00000’ automatically and the  
corresponding local register will be accessed. Since the address is  
Where, the A/B bit is used to identify the two channels:  
A/B = 0: 81H. channel A is the source (upstream) or destination  
(downstream).  
A/B = 1: 91H. channel B is the source (upstream) or destination  
(downstream).  
The Program Start byte will be followed by a register command  
(global/local register command) or a RAM command (FSK-RAM or Coe-  
RAM command). For global register commands, the A/B bit in the PS  
byte is ignored.  
59  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
'00000' now, the CODEC will stop counting down and the addressing  
operation is finished.  
location of the time slot (determined by the S0 and S1 pin), specifies the  
local registers to be addressed.  
The number of the local registers addressed by a local command is  
b[4:0]+1. Hence, up to 32(d) local registers can be addressed by one  
local command. To apply a write local command, total b[4:0]+1 bytes of  
data should follow to ensure proper operation. See Table - 21 for details.  
In GCI mode, the CODEC provides a consecutive adjacent  
addressing method for reading and writing local registers. According to  
the value of b[1:0] specified in the local command, there will be one to  
four adjacent local registers to be addressed automatically with the  
highest order one first. For example, if the address bits b[4:0] are set to  
'XXX11' in a local command, the CODEC will count down from the  
address 'XXX11' to the address 'XXX00' automatically. The number of  
local registers to be addressed by one local command is b[1:0]+1.  
Therefore, up to four local registers can be addressed by one local  
command in GCI mode. Refer to Table - 22 for details.  
Table - 21 Local Register Addressing in MPI Mode  
Address Specified in  
a Local Command  
Address of the Local  
Registers to be accessed  
In/Out Data Bytes  
b[4:0] = 11111  
b[4:0] = 11110  
b[4:0] = 11101  
...  
32 bytes  
31 bytes  
30 bytes  
...  
from ‘11111’ to ‘00000’  
from ‘11110’ to ‘00000’  
from ‘11101’ to ‘00000’  
...  
Table - 22 Local Register Addressing in GCI Mode  
Address Specified in  
a Local Command  
Address of the Local  
Registers to be accessed  
In/Out Data Bytes  
b[4:0] = 11000  
b[4:0] = 10111  
b[4:0] = 10110  
b[4:0] = 10101  
...  
25 bytes  
24 bytes  
23 bytes  
22 bytes  
...  
from ‘11000’ to ‘00000’  
from ‘10111’ to ‘00000’  
from ‘10110’ to ‘00000’  
from ‘10101’ to ‘00000’  
...  
byte 1  
byte 2  
byte 3  
byte 4  
byte 1  
byte 2  
byte 3  
byte 1  
byte 2  
XXX11  
XXX10  
XXX01  
XXX00  
XXX10  
XXX01  
XXX00  
XXX01  
XXX00  
b[4:0] = XXX11  
b[4:0] = XXX10  
b[4:0] = 10000  
b[4:0] = 01111  
b[4:0] = 01110  
b[4:0] = 01101  
...  
17 bytes  
16 bytes  
15 bytes  
14 bytes  
...  
from ‘10000’ to ‘00000’  
from ‘01111’ to ‘00000’  
from ‘01110’ to ‘00000’  
from ‘01101’ to ‘00000’  
...  
b[4:0] = XXX01  
b[4:0] = XXX00  
byte 1  
XXX00  
In GCI mode, the procedure of the consecutive adjacent addressing  
can not be stopped once a command is initiated. For a write operation,  
the number of the data bytes that follow the command byte must be the  
same as the number of the registers to be written.  
Refer to “5.4.2.1 Example of Programming the Local Registers via  
GCI” on page 85 for details.  
b[4:0] = 01000  
b[4:0] = 00111  
b[4:0] = 00110  
b[4:0] = 00101  
...  
9 bytes  
8 bytes  
7 bytes  
6 bytes  
...  
from ‘01000’ to ‘00000’  
from ‘00111’ to ‘00000’  
from ‘00110’ to ‘00000’  
from ‘00101’ to ‘00000’  
...  
5.2.3  
ADDRESSING THE GLOBAL REGISTERS  
b[4:0] = 00000  
1 byte  
‘00000’  
In both MPI and GCI modes, the global registers are used to  
configure all four channels. The CODEC provides 32 global registers for  
all channels. The global registers are accessed by the corresponding  
global commands.  
In MPI mode, when the CS pin is pulled low, the CODEC treats the  
first byte present on the CI pin as command and the following byte(s) as  
data. To execute other commands, the CS pin must be changed from  
low to high to finish the previous command and then be changed from  
high to low to start the next command.  
The automatic count-down procedure can be stopped by the CS pin  
at any time. If the CS pin changes from low to high during a addressing  
process, the operation for current local register and the rest local  
registers will be aborted. But the operations accomplished before the CS  
pin goes high will have already been executed.  
• MPI Mode  
In MPI mode, the global registers are shared by all four channels,  
and there is no need to specify a channel or channels before addressing  
global registers. Except for this, the global registers are addressed in a  
similar manner as the local registers. See “5.4.1.2 Example of  
Programming the Global Registers via MPI” on page 84 for details.  
• GCI Mode  
In GCI mode, the global command can be transferred during any of  
the GCI time slots and all four channel will receive it. Except for this, the  
global registers are addressed in a similar manner as the local registers.  
See “5.4.2.2 Example of Programming the Global Registers via GCI” on  
page 85 for details.  
To complete an automatic countdown procedure, the CS pin  
must remain low for more than one data byte period after the last  
data byte is transmitted.  
Refer to “5.4.1.1 Example of Programming the Local Registers via  
MPI” on page 83 for more information.  
• GCI Mode  
5.2.4  
ADDRESSING THE FSK-RAM  
In GCI mode, the b4 bit in the Program Start byte, together with the  
When sending a Caller ID message via FSK signal, the message  
60  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
data is stored in the FSK-RAM that is shared by all four channels. The  
FSK-RAM consists of 32 words, 16 bits (two bytes) per word. They are  
addressed by the FSK-RAM commands.  
The b[4:0] bits in a FSK-RAM command specify a location in the  
FSK-RAM to be accessed. In both MPI and GCI modes, when  
addressing a FSK-RAM word, 16 bits will be written to or read out from  
this word with MSB first.  
Each word in Coe-RAM is 14-bit wide. To write a Coe-RAM word, 16  
bits (or two 8-bit bytes) are needed to fill one word with MSB first, but the  
first two bits (MSB) will be ignored. When being read, each Coe-RAM  
word will output 16 bits with MSB first, but the first two bits are  
meaningless.  
• MPI Mode  
In MPI mode, the Coe-RAM commands always follow the Channel  
Enable command that specifies which channel(s) to be accessed.  
The address (b[4:0]) in the Coe-RAM commands indicates which  
block of the Coe-RAM for the specified channel(s) will be addressed.  
The CODEC automatically counts down from the highest address to the  
lowest address of the specified block. So one block (consists of eight  
words) can be addressed by one Coe-RAM Command.  
In MPI mode, the procedure of reading/writing words from/to the  
Coe-RAM can be stopped by the CS pin at any time. When the CS pin  
changes from low to high, the operation on the current word and the next  
adjacent words will be aborted. But the operations that are  
accomplished before the CS pin goes high have been executed.  
See “5.4.1.3 Example of Programming the Coefficient-RAM via MPI”  
on page 84 for detailed information.  
• MPI Mode  
In MPI mode, the FSK-RAM is addressed in a similar manner as the  
local registers except the data is twice as long. When executing a FSK-  
RAM command, the CODEC automatically counts down from the  
address specified in the command (b[4:0]) to the address of '00000',  
resulting in total b[4:0]+1 words of FSK-RAM being addressed. As the  
data written to or read out from the FSK-RAM is 16-bit (two-byte) wide,  
total (b[4:0]+1)2 bytes of data will follow a FSK-RAM command. Refer  
to “5.4.1.4 Example of Programming the FSK-RAM via MPI” on page 84  
for more information.  
• GCI Mode  
In GCI mode, the FSK-RAM is addressed in a similar manner as the  
local registers except the data is twice as long (the data for the FSK-  
RAM is 16-bit wide while the data for local registers is 8-bit wide). Refer  
to “5.4.2.4 Example of Programming the FSK-RAM via GCI” on page 86  
for more information.  
• GCI Mode  
In GCI mode, both the location of time slot (determined by S1 and S0  
pin) and the b4 bit in Program Start byte specify a channel of which the  
Coe-RAM will be addressed. The address (b[4:0]) in the Coe-RAM  
Command locates a block of the Coe-RAM. When executing a Coe-  
RAM Command, all eight words in the block will be read/written  
automatically, with the highest order word first.  
In GCI mode, the procedure of the consecutive adjacent addressing  
can not be stopped once a Coe-RAM command is initiated.  
See “5.4.2.3 Example of Programming the Coefficient-RAM via GCI”  
on page 85 for details.  
5.2.5  
ADDRESSING THE COE-RAM  
The Coe-RAM (Coefficient RAM) consists of 12 blocks per channel,  
and each block consists of 8 words. So, there are total 96 words per  
channel. The coefficient RAM mapping is shown in Table - 23.  
61  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Table - 23 Coefficient RAM Mapping  
Offset/  
Address  
Word 7  
Word 6  
Word 5  
Word 4  
Word 3  
Word 2  
Word 1  
Word 0  
Notes  
DC Offset  
(default value: 0)  
Impedance Matching Filter (IMF) Coefficient  
(default: the IMF is disabled)  
Reserved  
Reserved  
00H  
Block 0  
Block 1  
Transhybrid Balance Filter (ECF) Coefficient  
(default: the ECF is disabled)  
Should be  
Reserved  
01H  
02H  
2000H when  
Gain for  
Impedance  
Scaling (GIS)  
(default value: 0)  
TG2Freq  
(default: 1447  
Hz)  
using the dual  
tone genera-  
tors. (default:  
0000H)(1)  
TG2Amp  
TG1Freq  
TG1Amp  
Block 2  
(default: 0.94 V) (default: 852 Hz) (default: 0.94 V)  
Digital Gain in  
Transmit Path  
(GTX)  
Coefficient for Frequency Response Correction in Transmit Path (FRX)  
(default: the FRX is disabled)  
03H  
04H  
Block 3  
Block 4  
(default: 0 dB)  
Digital Gain in  
Receive Path  
(GRX)  
Coefficient for Frequency Response Correction in Receive Path (FRR)  
(default: the FRR is disabled)  
(default: 0 dB)  
RampEnd  
RampSlope  
RingOffset  
RingFreq  
RingAmp  
Reserved  
Reserved  
05H  
06H  
07H  
Block 5  
Block 6  
Block 7  
(default: 20 V) (default:300V/S) (default: 7 V) (default: 30 Hz) (default: 40 V)  
DC Feeding Coefficient  
HKHyst  
RTthld_AC  
RTthld_DC  
HKthld  
(default: 7 mA)  
Reserved  
(default: 2 mA) (default: 5 mA) (default: 5 mA)  
UTD Integrator  
Coefficient  
UTD Bandstop Filter Coefficient(2)  
UTDthld_Floor UTDthld_Ceiling  
UTD Bandpass Filter Coefficient(2)  
08H  
09H  
Block 8  
Block 9  
UTD Integrator  
Coefficient  
Reserved  
(default: 18  
(default: 6  
Reserved  
dBm)  
dBm)  
LM Notch Filter Coefficient(3)  
Reserved  
Reserved  
0AH  
0BH  
Block 10  
Block 11  
LM Bandpass Filter Coefficient(3)  
Notes:  
1. The default value of this word is 0000H. When using the dual tone generators, users should write 2000H (i.e. high byte: 20H, low byte: 00H) to this word to ensure proper operation.  
2. When the gains in the transmit and receive paths are 0 dB, the default parameters of the UTD filters are as follows:  
bandpass filter: center frequency is 2100 Hz and bandwidth is 60 Hz.  
bandstop filter: center frequency is 2100 Hz and bandwidth is 230 Hz.  
3. When the gains in the transmit and receive paths are 0 dB, the default parameters of the level meter filter are as follows:  
bandpass/notch filter: center frequency is 1014 Hz and quality factor (Q) is 5.  
62  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
5.3  
REGISTERS DESCRIPTION  
5.3.1  
REGISTERS OVERVIEW  
Table - 24 Global Registers Mapping  
Register Byte  
Read  
Write  
Default  
Name  
Function Description  
Command Command Value  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
GREG1 PLL power down  
PLL_PD  
Reserved  
20H  
-
A0H  
-
00H  
-
GREG2 Reserved for future use  
GREG3 PCM configuration  
Reserved  
TR_SLOPE[1:0]  
L_CODE  
A/µ  
DBL_CLK  
PCM_OFT[2:0]  
22H  
A2H  
40H  
MCLK selection and  
GREG4  
CH_EN[3:0]  
HW_RST Reserved SW_RST Reserved  
Reserved ALB_64K ALB_8K ALB_DI  
Reserved  
MCLK_SEL[3:0]  
RCH_SEL[3:0]  
23H  
A3H  
02H  
channel enable  
Hardware/software reset  
GREG5  
24H  
25H  
26H  
A4H  
A5H  
A6H  
00H  
00H  
00H  
and version information  
GREG6 Loopback control  
Reserved DLB_64K  
CONF_EN CONFX_EN  
G_CONF[7:0]  
DLB_8K  
DLB_DI  
Three-party conference  
control  
GREG7  
CONF_CS[1:0]  
Gain of three-party  
GREG8  
27H  
28H  
29H  
2AH  
2BH  
2CH  
2DH  
A7H  
A8H  
A9H  
AAH  
ABH  
ACH  
ADH  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
conference  
Transmit highway and time  
GREG9  
THS_B  
RHS_B  
THS_C  
RHS_C  
THS_D  
RHS_D  
TT_B[6:0]  
RT_B[6:0]  
TT_C[6:0]  
RT_C[6:0]  
TT_D[6:0]  
RT_D[6:0]  
slot selection for Part B  
Receive highway and time  
GREG10  
slot selection for Part B  
Transmit highway and time  
GREG11  
slot selection for Part C  
Receive highway and time  
GREG12  
slot selection for Part C  
Transmit highway and time  
GREG13  
slot selection for Part D  
Receive highway and time  
GREG14  
slot selection for Part D  
GREG15 Level meter configuration 1  
LM_CN[7:0]  
Reserved  
LMRL[7:0]  
2EH  
2FH  
30H  
31H  
32H  
33H  
34H  
35H  
36H  
37H  
-
AEH  
AFH  
-
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
00H  
-
GREG16 Level meter configuration 2 LM_ONCE  
GREG17 Level meter result (low)  
GREG18 Level meter result (high)  
GREG19 FSK flag length  
LM_EN  
LM_CS[1:0]  
LM_CN[10:8]  
LMRH[7:0]  
FSK_FL[7:0]  
FSK_DL[7:0]  
FSK_SL[7:0]  
FSK_ML[7:0]  
-
B2H  
B3H  
B4H  
B5H  
B6H  
B7H  
-
GREG20 FSK data length  
GREG21 FSK seizure length  
GREG22 FSK mark length  
GREG23 FSK control  
Reserved  
FSK_CS[1:0]  
INT_POL  
Reserved  
FSK_EN  
FSK_BS FSK_MAS FSK_TS  
Reserved  
GREG24 Interrupt polarity  
GREG25 Reserved for future use  
Reserved  
Off-hook, ground-key  
GREG26  
GK[3]  
HK[3]  
GK[2]  
HK[2]  
GK[1]  
HK[1]  
GK[0]  
HK[0]  
39H  
B9H  
00H  
status and interrupt clear  
63  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Table - 25 Local Registers Mapping  
Register Byte  
b4 b3  
Read  
Write  
Default  
Value  
Name  
Function Description  
Command Command  
b7  
b6  
b5  
b2  
b1  
b0  
00H for CH1  
01H for CH2  
02H for CH3  
03H for CH4  
Transmit highway and time  
slot selection  
LREG1  
THS  
TT[6:0]  
RT[6:0]  
00H  
01H  
80H  
81H  
00H for CH1  
01H for CH2  
02H for CH3  
03H for CH4  
Receive highway and time  
slot selection  
LREG2  
RHS  
LREG3 Loopback control  
LREG4 Coefficient selection  
LREG5 Coefficient selection  
Reserved  
FRR  
DLB_2M DLB_PCM Reserved ALB_1MDC ALB_2M ALB_PCM CUTOFF  
02H  
03H  
04H  
82H  
83H  
84H  
00H  
FFH  
BFH  
GRX  
HPF  
FRX  
GTX  
TG  
ECF  
IMF  
DC_OFT  
RG  
V90  
LM_B  
LM_N  
UTD  
Signaling DC_FEED  
SM[2:0]  
CODEC and RSLIC mode  
LREG6  
P_DOWN STANDBY  
ACTIVE  
RAMP  
SCAN_EN  
05H  
85H  
80H  
control  
Analog Gain Selection, AC/  
DC Ring Trip Selection,  
Ring Generator and Tone  
LREG7  
Reserved  
IM_629  
RING  
RT_SEL  
RING_EN TG2_EN  
TG1_EN  
06H  
86H  
00H  
Generators Enable  
Ramp Generator Enable,  
Level Meter Path Selection  
and Notch/Bandpass Filter  
Characteristic  
Configuration, UTD Source  
Selection and UTD Enable  
LREG8  
RAMP_EN Reserved LM_NOTCH LM_FILT  
LM_SRC  
DC_SRC UTD_SRC UTD_EN  
LM_SEL[3:0]  
07H  
87H  
00H  
level meter source and  
LREG9  
K[3:0]  
LM_RECT  
DB[3:0]  
08H  
09H  
88H  
89H  
00H  
00H  
shift factor selection  
level meter threshold,  
LREG10  
OTHRE  
LM_GF  
Reserved  
LM_TH[2:0]  
DB_IO[3:0]  
rectifier on/off, gain factor  
LREG11 Debounce filter  
LREG12 PCM data low byte  
LREG13 PCM data high byte  
LREG14 UTD RTIME  
0AH  
0BH  
0CH  
0DH  
0EH  
0FH  
10H  
11H  
8AH  
-
00H  
00H  
00H  
13H  
19H  
40H  
64H  
1FH  
PCM[7:0]  
PCM[15:8]  
-
UTD_RT[7:0]  
UTD_RBK[7:0]  
UTD_ET[7:0]  
UTD_EBRK[7:0]  
8DH  
8EH  
8FH  
90H  
91H  
LREG15 UTD RBKTime  
LREG16 UTD ETIME  
LREG17 UTD EBRKTime  
LREG18 Interrupt mask  
Reserved  
Reserved  
GK_M  
HK_M  
OTMP_M RAMP_M  
IO_M[3:0]  
GKP_M  
IO interrupt mask, polarity  
LREG19 reverse, external ringing  
sync enable  
REV_POL SYNC_EN  
12H  
13H  
14H  
92H  
93H  
-
0FH  
00H  
01H  
IO pin direction select and  
IO data  
LREG20  
IO_C[3:0]  
IO[3:0]  
Interrupt source and DC  
LREG21 feeding characteristic  
indication  
FEED_I  
FEED_V  
FEED_R  
LM_OK  
UTD_OK  
OTMP  
RAMP_OK GK_POL  
64  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
In the following global registers and local registers lists, it should be noted that:  
1. R/W = 0, Read command. R/W = 1, Write command.  
2. The reserved bit(s) in the register must be filled in ‘0’ in write operation and will be ignored in read operation.  
3. The global or local registers described below are available for both MPI and GCI modes except for those with special statement.  
5.3.2  
GLOBAL REGISTERS LIST  
GREG1: PLL Power Down, Read/Write (20H/A0H)  
b7  
b6  
b5  
b4  
b3  
0
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
0
0
0
PLL_PD  
Reserved  
PLL_PD  
Power down the internal PLL block (refer to “6.2 PLL Power Down” on page 90 for details).  
PLL_PD = 0:  
PLL_PD = 1:  
the internal PLL block is powered up (default);  
the internal PLL block is powered down.  
Other bits in this register are reserved for future use.  
GREG2: Reserved.  
This register is reserved for future use.  
GREG3: PCM Configuration, Read/Write (22H/A2H)  
b7  
b6  
0
b5  
1
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
0
0
1
0
L_CODE  
DBL_CLK  
TR_SLOPE[1:0]  
PCM_OFT[2:0]  
A/µ  
L_CODE  
Voice data code (8-bit, A/µ-law compressed code or 16-bit linear code) selection  
L_CODE = 0:  
L_CODE = 1:  
compressed code is selected (default);  
linear code is selected.  
A/µ  
Select the PCM law  
A/µ = 0:  
A/µ = 1:  
µ-law is selected;  
A-law is selected (default).  
DBL_CLK  
Clock mode (single or double) selection. This bit is used for MPI mode only.  
DBL_CLK = 0: single clock is selected (default);  
DBL_CLK = 1: double clock is selected.  
TR_SLOPE[1:0] Transmit and receive slope selection. The TR_SLOPE[1:0] bits are used for MPI mode only.  
TR_SLOPE[1:0]=00: transmits data on the rising edges of BCLK, receives data on the falling edges of BCLK (default);  
TR_SLOPE[1:0]=01: transmits data on the rising edges of BCLK, receives data on the rising edges of BCLK;  
TR_SLOPE[1:0]=10: transmits data on the falling edges of BCLK, receives data on the falling edges of BCLK;  
TR_SLOPE[1:0]=11: transmits data on the falling edges of BCLK, receives data on the rising edges of BCLK;  
PCM_OFT[2:0] PCM timing offset selection. The PCM transmit/receive time slot can be offset from FSC by 0 to 7 BCLK periods. The  
PCM_OFT[2:0] bits are used for MPI mode only.  
PCM_OFT[2:0]=000: offset from FSC by 0 BCLK period (default);  
PCM_OFT[2:0]=001: offset from FSC by 1 BCLK period;  
PCM_OFT[2:0]=010: offset from FSC by 2 BCLK periods;  
PCM_OFT[2:0]=011: offset from FSC by 3 BCLK periods;  
PCM_OFT[2:0]=100: offset from FSC by 4 BCLK periods;  
PCM_OFT[2:0]=101: offset from FSC by 5 BCLK periods;  
PCM_OFT[2:0]=110: offset from FSC by 6 BCLK periods;  
PCM_OFT[2:0]=111: offset from FSC by 7 BCLK periods.  
65  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
GREG4: Master Clock Selection and Channel Program Enable, Read/Write (23H/A3H)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
0
0
1
1
CH_EN[3:0]  
MCLK_SEL[3:0]  
CH_EN[3:0]  
Channel programming enable. In MPI mode, the channel programming enable command is used to specify the  
channel(s) to which the subsequent local command or Coe-RAM command will be applied. The CH_EN[3:0] bits  
enable Channel 4 to Channel 1 for programming, respectively. The CH_EN[3:0] bits are used for MPI mode only.  
CH_EN[3] = 0: Disabled, Channel 4 can not receive Local Commands and Coe-RAM Commands (default);  
CH_EN[3] = 1: Enabled, Channel 4 can receive Local Commands and Coe-RAM Commands;  
CH_EN[2] = 0: Disabled, Channel 3 can not receive Local Commands and Coe-RAM Commands (default);  
CH_EN[2] = 1: Enabled, Channel 3 can receive Local Commands and Coe-RAM Commands;  
CH_EN[1] = 0: Disabled, Channel 2 can not receive Local Commands and Coe-RAM Commands (default);  
CH_EN[1] = 1: Enabled, Channel 2 can receive Local Commands and Coe-RAM Commands;  
CH_EN[0] = 0: Disabled, Channel 1 can not receive Local Commands and Coe-RAM Commands (default);  
CH_EN[0] = 1: Enabled, Channel 1 can receive Local Commands and Coe-RAM Commands;  
MCLK_SEL[3:0] Select the frequency of the master clock. In MPI mode, there are nine frequencies can be selected as the master  
clock. The MCLK_SEL[3:0] bits are used for MPI mode only.  
(In GCI mode, the frequency of the master clock is either 2.048 MHz or 4.096 MHz, the same as the frequency of Data  
Clock (DCL). The internal circuit of the CODEC monitors the DCL input to determine which frequency is being used.)  
MCLK_SEL[3:0] = 0000: 8.192 MHz  
MCLK_SEL[3:0] = 0001: 4.096 MHz  
MCLK_SEL[3:0] = 0010: 2.048 MHz (default)  
MCLK_SEL[3:0] = 0110: 1.536 MHz  
MCLK_SEL[3:0] = 1110: 1.544 MHz  
MCLK_SEL[3:0] = 0101: 3.072 MHz  
MCLK_SEL[3:0] = 1101: 3.088 MHz  
MCLK_SEL[3:0] = 0100: 6.144 MHz  
MCLK_SEL[3:0] = 1100: 6.176 MHz  
GREG5: Hardware and Software Reset, Write (A4H); Version Number, Read (24H)  
b7  
R/W  
b6  
0
b5  
1
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
0
0
1
0
0
Reserved  
SW_RST  
Reserved RCH_SEL[3] RCH_SEL[2] RCH_SEL[1] RCH_SEL[0]  
HW_RST  
When write this register, a hardware or a software reset will be applied as described below:  
HW_RST  
Hardware reset of the CODEC. The action of this hardware reset is equivalent to pulling the RESET pin of the CODEC  
low.  
HW_RST = 0:  
HW_RST = 1:  
No hardware reset signal will be generated (default);  
A hardware reset signal will be generated.  
SW_RST  
Software reset of the CODEC. This software reset operation resets those local registers specified by the RCH_SEL[3:0]  
bits, but the Coe-RAM is not affected.  
SW_RST = 0:  
SW_RST = 1:  
No software reset signal will be generated (default);  
A software reset signal will be generated. If the SW_RST bit is set to 1, those local registers specified  
by the RCH_SEL[3:0] bits will be reset, but other local registers and all the global registers as well as  
the Coe-RAM will not be affected.  
RCH_SEL[3:0] Select channel(s) for software reset. The RCH_SEL[3:0] bits select the local registers of Channel 4 to Channel 1,  
respectively, to be reset.  
RCH_SEL[3] = 0: The local registers of Channel 4 will not be reset after executing a software reset command (default));  
RCH_SEL[3] = 1: The local registers of Channel 4 will be reset after executing a software reset command;  
66  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
RCH_SEL[2] = 0: The local registers of Channel 3 will not be reset after executing a software reset command (default));  
RCH_SEL[2] = 1: The local registers of Channel 3 will be reset after executing a software reset command;  
RCH_SEL[1] = 0: The local registers of Channel 2 will not be reset after executing a software reset command (default);  
RCH_SEL[1] = 1: The local registers of Channel 2 will be reset after executing a software reset command;  
RCH_SEL[0] = 0: The local registers of Channel 1 will not be reset after executing a software reset command (default);  
RCH_SEL[0] = 1: The local registers of Channel 1 will be reset after executing a software reset command;  
When read this register, the CODEC version number of 5AH will be read out.  
GREG6: Test Loopback Control, Read/Write (25H/A5H)  
b7  
R/W  
b6  
0
b5  
1
b4  
0
b3  
0
b2  
1
b1  
0
b0  
1
Command  
I/O data  
Reserved  
ALB_64K  
ALB_8K  
ALB_DI  
Reserved  
DLB_64K  
DLB_8K  
DLB_DI  
This register is used to enable the analog and digital loopbacks for testing.  
ALB_64K  
ALB_8K  
ALB_DI  
Analog loopback via 64 KHz  
ALB_64K = 0:  
ALB_64K = 1:  
ALB_64K loopback is disabled (normal operation) (default);  
ALB_64K loopback is enabled.  
Analog loopback via 8 KHz  
ALB_8K = 0:  
ALB_8K = 1:  
ALB_8K loopback is disabled (normal operation) (default);  
ALB_8K loopback is enabled.  
Analog loopback via DX to DR (This loopback is available for MPI mode only)  
ALB_DI = 0:  
ALB_DI = 1:  
ALB_DI loopback is disabled (normal operation) (default);  
ALB_DI loopback is enabled.  
DLB_64K  
DLB_8K  
DLB_DI  
Digital loopback via 64 KHz  
DLB_64K = 0:  
DLB_64K = 1:  
DLB_64K loopback is disabled (normal operation) (default);  
DLB_64K loopback is enabled.  
Digital loopback via 8 KHz  
DLB_8K = 0:  
DLB_8K = 1:  
DLB_8K loopback is disabled (normal operation) (default);  
DLB_8K loopback is enabled.  
Digital loopback via DR to DX (This loopback is available for MPI mode only)  
DLB_DI = 0:  
DLB_DI = 1:  
DLB_DI loopback is disabled (normal operation) (default);  
DLB_DI loopback is enabled.  
GREG7: Three-Party Conference Configuration, Read/Write (26H/A6H)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
0
1
1
0
CONF_EN CONFX_EN  
CONF_CS[1:0]  
Reserved  
CONF_EN  
Enable internal three-party conference  
CONF_EN = 0:  
CONF_EN = 1:  
Internal conference is disabled (default);  
Internal conference is enabled.  
CONFX_EN  
Enable external three-party conference  
CONFX_EN = 0: External conference is disabled (default);  
CONFX_EN = 1: External conference is enabled.  
CONF_CS[1:0] Select a channel for three-party conference  
CONF_CS[1:0] = 00: Channel 1 is selected (default);  
67  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
CONF_CS[1:0] = 01: Channel 2 is selected;  
CONF_CS[1:0] = 10: Channel 3 is selected;  
CONF_CS[1:0] = 11: Channel 4 is selected.  
GREG8: Three-Party Conference Gain Setting, Read/Write (27H/A7H)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
0
1
1
1
G_CONF[7:0]  
G_CONF[7:0] Gain of three-party conference. The gain is calculated by the following formula:  
Gain = G_CONF[7:0] / 256  
The default value of G_CONG[7:0] bits is 0(d).  
GREG9: Transmit Time Slot and Highway Selection for Part B in Three-Party Conference, Read/Write (28H/A8H)  
b7  
b6  
b5  
b4  
b3  
1
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
0
0
0
THS_B  
TT_B[6:0]  
THS_B  
Transmit PCM highway selection for part B in three-party conference  
THS_B = 0:  
THS_B = 1:  
transmit PCM highway one (DX1) is selected (default);  
transmit PCM highway two (DX2) is selected.  
TT_B[6:0]  
Transmit time slot selection for part B in three-party conference.  
The valid value of the TT_B[6:0] bits is from 0(d) to 127(d), corresponding to Time Slot 0 to Time Slot 127.  
The default value of TT_B[6:0] is 0(d).  
GREG10: Receive Time Slot and Highway Selection for Part B in Three Party Conference, Read/Write (29H/A9H)  
b7  
b6  
b5  
b4  
b3  
1
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
0
0
1
RT_B[6:0]  
RHS_B  
RHS_B  
Receive PCM highway selection for part B in three-party conference  
RHS_B = 0:  
RHS_B = 1:  
receive PCM highway one (DR1) is selected (default);  
receive PCM highway two (DR2) is selected.  
RT_B[6:0]  
Receive PCM time slot selection for part B in three-party conference.  
The valid value of the RT_B[6:0] bits is from 0(d) to 127(d), corresponding to Time Slot 0 to Time Slot 127.  
The default value of RT_B[6:0] is 0(d).  
GREG11: Transmit Time Slot and Highway Selection for Part C in Three-Party Conference, Read/Write (2AH/AAH)  
b7  
b6  
b5  
b4  
b3  
1
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
0
1
0
TT_C[6:0]  
THS_C  
THS_C  
Transmit PCM highway selection for part C in three-party conference  
THS_C = 0:  
THS_C = 1:  
transmit PCM highway one (DX1) is selected (default);  
transmit PCM highway two (DX2) is selected.  
TT_C[6:0]  
Transmit time slot selection for part C in three-party conference.  
The valid value of the TT_C[6:0] bits is from 0(d) to 127(d), corresponding to Time Slot 0 to Time Slot 127.  
The default value of TT_C[6:0] is 0(d).  
68  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
GREG12: Receive Time Slot and Highway Selection for Part C in Three-Party Conference, Read/Write (2BH/ABH)  
b7  
b6  
b5  
b4  
b3  
1
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
0
1
1
RHS_C  
RT_C[6:0]  
RHS_C  
Receive PCM highway selection for part C in three-party conference  
RHS_C = 0:  
RHS_C = 1:  
receive PCM highway one (DR1) is selected (default);  
receive PCM highway two (DR2) is selected.  
RT_C[6:0]  
Receive time slot selection for part C in three-party conference.  
The valid value of the RT_C[6:0] bits is from 0(d) to 127(d), corresponding to Time Slot 0 to Time Slot 127.  
The default value of RT_C[6:0] is 0(d).  
GREG13: Transmit Time Slot and Highway Selection for Part D in Three-Party Conference, Read/Write (2CH/ACH)  
b7  
b6  
b5  
b4  
b3  
1
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
1
0
0
THS_D  
TT_D[6:0]  
THS_D  
Transmit PCM highway selection for part D in three-party conference  
THS_D = 0:  
THS_D = 1:  
transmit PCM highway one (DX1) is selected (default);  
transmit PCM highway two (DX2) is selected.  
TT_D[6:0]  
Transmit time slot selection for part D in three-party conference.  
The valid value of the TT_D[6:0] bits is from 0(d) to 127(d), corresponding to Time Slot 0 to Time Slot 127.  
The default value of TT_D[6:0] is 0(d).  
GREG14: Receive Time Slot and Highway Selection for Part D in Three-Party Conference, Read/Write (2DH/ADH)  
b7  
b6  
b5  
b4  
b3  
1
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
1
0
1
RT_D[6:0]  
RHS_D  
RHS_D  
Receive PCM highway selection for part D in three-party conference  
RHS_D = 0:  
RHS_D = 1:  
receive PCM highway one (DR1) is selected (default);  
receive PCM highway two (DR2) is selected.  
RT_D[6:0]  
Receive time slot selection for part D in three-party conference.  
The valid value of the RT_D[6:0] bits is from 0(d) to 127(d), corresponding to Time Slot 0 to Time Slot 127.  
The default value of RT_D[6:0] is 0(d).  
GREG15: Level Meter Count_Number Low 8 bits, Read/Write (2EH/AEH)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
0
1
1
1
0
LM_CN[7:0]  
The LM_CN[7:0] bits in this register together with the LM_CN[10:8] bits in GREG16 form an 11-bit counter register, which is used for the  
level meter to set the time period for PCM data sampling.  
The maximum number of time cycles set by the LM_CN[10:0] bits is 7FFH, corresponding to 255.875 ms. The time period for sampling  
can be programmed from 0 ms to 255.875 ms in steps of 0.125 ms (8k). If the LM_CN[10:0] bits are set to be 000H (corresponding to 0  
ms), the PCM data will be transmitted transparently to the level meter result registers without being sampled.  
LM_CN[10:0] = 0 (d):The PCM data is transmitted to level meter result registers GREG17 and GREG18 directly (default);  
LM_CN[10:0] = N (d):The PCM data is sampled for N 125 µs (N from 1 to 2047).  
69  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
GREG16: Level Meter Count_Number High 3 bits; Level Meter On/Off, Channel Selection and Once/Continuous Measurement, Read/Write  
(2FH/AFH)  
b7  
R/W  
b6  
0
b5  
1
b4  
0
b3  
1
b2  
b1  
b0  
Command  
I/O data  
1
1
1
LM_ONCE  
LM_EN  
LM_CS  
LM_CS[0]  
Reserved  
LM_CN[10:8]  
LM_ONCE  
Execution mode of the integrator in level meter. The integration can be executed continuously or once after every initia-  
tion.  
LM_ONCE = 0:  
LM_ONCE = 1:  
The integrator runs continuously (default);  
The integrator runs only once. To start again, the LM_EN bit must be set from 0 to 1 again.  
LM_EN  
LM_CS  
Level meter function enable. This bit starts or stops level metering.  
LM_EN = 0:  
LM_EN = 1:  
disabled, level metering stops (default);  
enabled, level metering starts.  
Level meter channel selection. The LM_CS[1:0] bits determine the data on which channel will be level metered.  
LM_CS[1:0] = 00: The data on Channel 1 will be input to the level meter (default);  
LM_CS[1:0] = 01: The data on Channel 2 will be input to the level meter;  
LM_CS[1:0] = 10: The data on Channel 3 will be input to the level meter;  
LM_CS[1:0] = 11: The data on Channel 4 will be input to the level meter.  
LM_CN  
Level meter count number high 3 bits LM_CN[10:8]. Refer to the description of GREG15 for details.  
GREG17: Level Meter Result Register (Low), Read Only (30H)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
0
0
1
1
0
0
0
0
LMRL[7:0]  
This register contains the low byte of the level meter result. The default value of LMRL[7:0] bits is 0.  
GREG18: Level Meter Result Register (High), Read Only (31H)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
0
0
1
1
0
0
0
1
LMRH[7:0]  
This register contains the high byte of the level meter result. The default value of the LMRH[7:0] is 0.  
GREG19: FSK Flag Length Register, Read/Write (32H/B2H)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
1
0
0
1
0
FSK_FL[7:0]  
The flag signal is a stream of '1'. It is transmitted between two message bytes during the Caller ID data transmission.  
This register is used to set the number of the flag bits '1'. The value of FSK_FL[7:0] bits is valid from 0 to 255(d).  
The default value of 0(d) means that no flag signal will be sent out.  
GREG20: FSK Data Length Register, Read/Write (33H/B3H)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
1
0
0
1
1
FSK_DL[7:0]  
This register is used to set the length of the data bytes that will be transmitted except the flag signal.  
The value of the FSK_DL[7:0] bits is valid from 0 to 64(d). Any value larger than 64(d) will be taken as 64(d) by the DSP.  
70  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
The default value of 0 means that no data bytes will be sent out.  
GREG21: FSK Seizure Length Register, Read/Write (34H/B4H)  
INDUSTRIAL TEMPERATURE RANGE  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
1
0
1
0
0
FSK_SL[7:0]  
The seizure length is the number of '01' pairs that represent the seizure phase.  
The seizure length is two times of the value of the FSK_SL[7:0] bits. The value of the FSK_SL[7:0] bits is valid from 0 to 255(d), corre-  
sponding to the seizure length from 0 to 510 (d).  
The default value of this register is 0, that means no seizure signal will be sent out.  
GREG22: FSK Mark Length Register, Read/Write (35H/B5H)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
1
1
0
1
0
1
FSK_ML[7:0]  
The mark signal is a stream of '1' that will be transmitted in initial flag phase.  
This register is used to set the number of the mark bits ‘1’. The value of the FSK_ML[7:0] bits is valid from 0 to 255(d).  
The default value of 0 means that no mark signal will be sent out.  
GREG23: FSK Transmit Start, Mark_after_send, Modulation Standard, FSK Channel Selection, FSK enable, Read/Write (36H/B6H)  
b7  
b6  
b5  
b4  
b3  
0
b2  
1
b1  
1
b0  
0
Command  
I/O data  
R/W  
0
1
1
FSK_CS[1:0]  
FSK_EN  
FSK_BS  
FSK_MAS  
FSK_TS  
Reserved  
FSK_CS  
FSK channel selection. The FSK_CS[1:0] bits select a channel on which the FSK signal is generated.  
FSK_CS[1:0] = 00: Channel 1 is selected (default);  
FSK_CS[1:0] = 01: Channel 2 is selected;  
FSK_CS[1:0] = 10: Channel 3 is selected;  
FSK_CS[1:0] = 11: Channel 4 is selected.  
FSK_EN  
FSK_BS  
FSK_MAS  
FSK function block enable.  
FSK_EN = 0:  
FSK_EN = 1:  
FSK function block is disabled (default);  
FSK function block is enabled.  
FSK modulation standard selection  
FSK_BS = 0:  
FSK_BS = 1:  
BELL 202 standard is selected (default);  
ITU-T V.23 standard is selected.  
Mark After Send. The FSK_MAS bit determines whether the FSK generator will keep on sending a mark-after-send sig-  
nal (a string of ‘1’) after finish sending the data in the FSK-RAM.  
FSK_MAS = 0:  
FSK_MAS = 1:  
The FSK output will be muted after sending out the data in the FSK-RAM (default);  
The FSK generator sends out a mark-after-send signal after finish sending out the data in the FSK-  
RAM. This signal will be stopped if the FSK_MAS bit is set to 0.  
FSK_TS  
FSK transmission starts.  
FSK_TS = 0:  
FSK_TS = 1:  
FSK transmission is disabled (default);  
FSK transmission starts.  
The FSK_TS bit will be reset automatically after the data in the FSK-RAM is finished sending. If the  
seizure length, the mark length and the data length are set to 0, the FSK_TS bit will be reset to 0  
immediately after it is set to 1.  
71  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
GREG24: Interrupt Polarity Selection Register, Read/Write (37H/B7H)  
b7  
b6  
0
b5  
b4  
1
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
1
0
1
1
1
Reserved  
INT_POL  
Reserved  
INT_POL  
Interrupt polarity selection. The INT_POL bit determines the valid polarity of all the interrupt signals including the  
INT_CHA and INT_CHB bits in GCI C/I channel.  
INT_POL = 0:  
INT_POL = 1:  
Active low (default);  
Active high.  
GREG25: Reserved  
This register is reserved for future use.  
GREG26: RSLIC Status, Read (39H); Interrupt Clear, Write (B9H)  
b7  
b6  
0
b5  
1
b4  
1
b3  
1
b2  
0
b1  
0
b0  
1
Command  
I/O data  
R/W  
GK[3]  
HK[3]  
GK[2]  
HK[2]  
GK[1]  
HK[1]  
GK[0]  
HK[0]  
In MPI mode, when applying a read operation to this register, the off-hook and ground-key status of all four channels will be read out. If  
an interrupt caused by off-hook or ground-key detection is pending, reading this register will clear the interrupt.  
HK[3:0]  
Off-hook status.  
HK[0] = 0:  
Channel 1 is on-hook (default);  
Channel 1 is off-hook.  
HK[0] = 1:  
HK[1] = 0:  
HK[1] = 1:  
Channel 2 is on-hook (default);  
Channel 2 is off-hook.  
HK[2] = 0:  
HK[2] = 1:  
Channel 3 is on-hook (default);  
Channel 3 is off-hook.  
HK[3] = 0:  
HK[3] = 1:  
Channel 4 is on-hook (default);  
Channel 4 is off-hook.  
GK[3:0]  
ground-key status.  
GK[0] = 0:  
No longitudinal current detected on Channel 1 (default);  
GK[0] = 1:  
Longitudinal current detected (ground-key or ground start) on Channel 1;  
GK[1] = 0:  
GK[1] = 1:  
No longitudinal current detected on Channel 2 (default);  
Longitudinal current detected (ground-key or ground start) on Channel 2;  
GK[2] = 0:  
GK[2] = 1:  
No longitudinal current detected on Channel 3 (default);  
Longitudinal current detected (ground-key or ground start) on Channel 3;  
GK[3] = 0:  
GK[3] = 1:  
No longitudinal current detected on Channel 4 (default);  
Longitudinal current detected (ground-key or ground start) on Channel 4;  
In GCI mode, the off-hook and ground-key status are reported via the upstream C/I channel only. Reading this register will always get a  
result of 00H. If an interrupt caused by off-hook or ground-key detection is pending, applying a read command to this register will clear  
the interrupt.  
In both MPI and GCI modes, when applying a write operation to this register, all the interrupts will be cleared.  
72  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
5.3.3 LOCAL REGISTERS LIST  
LREG1: Transmit Time Slot and Transmit Highway Selection, Read/Write (00H/80H). This register is used for MPI mode only.  
INDUSTRIAL TEMPERATURE RANGE  
b7  
b6  
b5  
b4  
b3  
0
b2  
b1  
b0  
Command  
I/O data  
R/W  
THS  
0
0
0
0
0
0
TT[6:0]  
THS  
Transmit PCM highway selection for the specified channel.  
THS = 0:  
THS = 1:  
transmit PCM highway one (DX1) is selected (default);  
transmit PCM highway two (DX2) is selected.  
TT[6:0]  
Transmit time slot selection for the specified channel.  
The valid value of the TT[6:0] bits is from 0(d) to 127(d), corresponding to Time Slot 0 to Time Slot 127.  
The default value of TT[6:0] is 00H for Channel 1, 01H for Channel 2, 02H for Channel 3 and 03H for Channel 4.  
LREG2: Receive Time Slot and Receive Highway Selection, Read/Write (01H/81H). This register is used for MPI mode only.  
b7  
b6  
b5  
b4  
b3  
0
b2  
b1  
b0  
Command  
I/O data  
R/W  
RHS  
0
0
0
0
0
1
RT[6:0]  
RHS  
Receive PCM highway selection for the specified channel.  
RHS = 0:  
RHS = 1:  
receive PCM highway one (DR1) is selected (default);  
receive PCM highway two (DR2) is selected.  
RT[6:0]  
Receive time slot selection for the specified channel.  
The valid value of the RT[6:0] bits is from 0(d) to 127(d), corresponding to Time Slot 0 to Time Slot 127.  
The default value of RT[6:0] is 00H for Channel 1, 01H for Channel 2, 02H for Channel 3 and 03H for Channel 4.  
LREG3: Loopback Control, Read/Write (02H/82H)  
b7  
R/W  
b6  
0
b5  
0
b4  
0
b3  
0
b2  
0
b1  
1
b0  
0
Command  
I/O data  
DLB_2M  
DLB_PCM  
Reserved  
ALB_1MDC  
ALB_2M  
ALB_PCM  
CUTOFF  
Reserved  
The register is used to enable the digital and analog loopbacks on the specified channel(s) for testing.  
DLB_2M  
Digital loopback via 2M  
DLB_2M = 0:  
DLB_2M = 1:  
disabled (normal operation) (default);  
enabled (closed);  
DLB_PCM  
ALB_1MDC  
ALB_2M  
Digital loopback via the PCM interface (This loopback is available for MPI mode only)  
DLB_PCM = 0:  
DLB_PCM = 1:  
disabled (normal operation) (default);  
enabled (closed);  
Analog loopback via 1M in the DC loop  
ALB_1MDC = 0: disabled (normal operation) (default);  
ALB_1MDC = 1: enabled (closed);  
Analog loopback via 2M  
ALB_2M = 0:  
ALB_2M = 1:  
disabled (normal operation) (default);  
enabled (closed);  
ALB_PCM  
CUTOFF  
Analog loopback via the PCM interface (This loopback is available for MPI mode only)  
ALB_PCM = 0:  
ALB_PCM = 1:  
disabled (normal operation) (default);  
enabled (closed);  
Cut off PCM receive path  
73  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
CUTOFF = 0:  
CUTOFF = 1:  
disabled, the PCM receive path is in normal operation (default);  
enabled, the PCM receive path is cut off.  
LREG4: Coefficient Selection, Read/Write (03H/83H)  
b7  
b6  
0
b5  
0
b4  
0
b3  
0
b2  
0
b1  
1
b0  
1
Command  
I/O data  
R/W  
FRR  
GRX  
FRX  
GTX  
TG  
ECF  
IMF  
DC_OFT  
This register determines whether the default values or the coefficients in Coe-RAM is selected for the programmable filters, tone genera-  
tors and DC offset compensation.  
FRR  
GRX  
FRX  
GTX  
TG  
Coefficient selection for the Frequency Response correction in the Receive path  
FRR = 0:  
FRR = 1:  
coefficient in the Coe-RAM is selected;  
the frequency response correction in the receive path is disabled (default).  
Coefficient selection for the digital Gain filter in the Receive path  
GRX = 0:  
GRX = 1:  
coefficient in the Coe-RAM is selected;  
the digital gain in the receive path is 0 dB (default).  
Coefficient selection for the Frequency Response correction in the Transmit path  
FRX = 0:  
FRX = 1:  
coefficient in the Coe-RAM is selected;  
the frequency response correction in the transmit path is disabled (default).  
Coefficient selection for the digital Gain filter in the Transmit path  
GTX = 0:  
GTX = 1:  
coefficient in the Coe-RAM is selected;  
the digital gain in the transmit path is 0 dB (default).  
Coefficient selection for the Tone Generators (TG1 and TG2)  
TG = 0:  
TG = 1:  
coefficient in the Coe-RAM is selected;  
coefficient in the ROM is selected (default)  
(The default values are: TG1Amp = 0.94 V, TG1Freq = 852 Hz, TG2Amp = 0.94 V, TG2Freq = 1447  
Hz).  
ECF  
Coefficient selection for the Echo Cancellation filter  
ECF = 0:  
ECF = 1:  
coefficient in the Coe-RAM is selected;  
the echo cancellation filter is disabled (default).  
IMF  
Coefficient selection for the Impedance Matching filter  
IMF = 0:  
IMF = 1:  
coefficient in the Coe-RAM is selected;  
the impedance matching filter is disabled (default).  
DC_OFT  
Compensation value selection for the Offset Register  
DC_OFT = 0:  
DC_OFT = 1:  
the compensation value in the Coe-RAM is used;  
the DC offset compensation value in the ROM (which is 0) is used (default).  
LREG5: Coefficient Selection and Filter Control Register, Read/Write (04H/84H)  
b7  
b6  
0
b5  
0
b4  
0
b3  
0
b2  
1
b1  
0
b0  
0
Command  
I/O data  
R/W  
V90  
HPF  
LM_B  
LM_N  
UTD  
Signaling  
DC_FEED  
RG  
V90  
V90 filter characteristic enable. The bit is used to select the filter characteristic of the lowpass filter in voice signal path.  
The V90 filter characteristic may be selected for a modem transmission to improve the transmission rate and  
performance.  
V90 = 0:  
V90 = 1:  
The V90 filter is enabled;  
The V90 filter is disabled (default);.  
HPF  
Enable/disable the highpass filter  
74  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
HPF = 0:  
HPF = 1:  
The highpass filter is enabled (default);  
The highpass filter is disabled.  
LM_B  
Coefficient selection for the level meter bandpass filter  
LM_B = 0:  
LM_B = 1:  
coefficient in the Coe-RAM is used for the level meter bandpass filter;  
coefficient in the ROM is used for the level meter bandpass filter (default).  
LM_N  
Coefficient selection for the level meter notch filter  
LM_N = 0:  
LM_N = 1:  
coefficient in the Coe-RAM is used for the level meter notch filter;  
coefficient in the ROM is used for the level meter notch filter (default).  
UTD  
Coefficient and threshold selection for the UTD  
UTD = 0:  
UTD = 1:  
coefficient and threshold in the Coe-RAM are used for UTD;  
coefficient and threshold in the ROM are used for UTD (default).  
Signaling  
DC_FEED  
RG  
Coefficient selection for signaling (thresholds for off-hook, ground-key and ring trip detection)  
Signaling = 0:  
Signaling = 1:  
coefficients in the Coe-RAM are used;  
coefficients in the ROM are used (refer to Table - 23 on page 62 for details) (default).  
Coefficient selection for DC feeding characteristic  
DC_FEED = 0:  
DC_FEED = 1:  
coefficient in the Coe-RAM is used;  
coefficient in the ROM is used (default).  
Coefficients selection for Ring Generator and Ramp Generator  
RG = 0:  
RG = 1:  
coefficient in the Coe-RAM is used;  
coefficient in the ROM is used (default).  
LREG6: CODEC and RSLIC Mode Control Register, Read/Write (05H/85H)  
b7  
R/W  
b6  
0
b5  
0
b4  
0
b3  
0
b2  
b1  
0
b0  
Command  
I/O data  
1
1
STANDBY  
ACTIVE  
RAMP  
SCAN_EN  
SM[2:0]  
P_DOWN  
All eight bits in this register and the RING bit in LREG7 are used to control the operating mode of the chipset.  
The higher four bits in this register and the RING bit in LREG7 are used to control the operating mode of the CODEC.  
P_DOWN = 0:  
P_DOWN = 1:  
power down mode is disabled;  
power down mode is enabled (default).  
STANDBY = 0:  
STANDBY = 1:  
standby mode is disabled (default);  
standby mode is enabled.  
ACTIVE = 0:  
ACTIVE = 1:  
active mode is disabled (default);  
active mode is enabled.  
RAMP = 0:  
RAMP = 1:  
ramp mode is disabled (default);  
ramp mode is enabled;  
The lower four bits in this register are used to control the operating mode of the RSLIC. These four bits are used for MPI mode only.  
(In GCI mode, the SCAN_EN and SM[2:0] bits in the downstream C/I channel byte control the operating mode of the RSLIC. Refer to  
“4.2.3.1 Downstream C/I Channel Byte” on page 55 for details)  
SCAN_EN = 0:  
SCAN_EN = 1:  
the corresponding RSLIC will not be accessed (default);  
the corresponding RSLIC will be accessed.  
The SM[2:0] bits determine the operating mode of the RSLIC as shown in the following:  
SM[2:0] = '000':  
SM[2:0] = '001':  
SM[2:0] = '010':  
Normal Active mode (default);  
External Ring;  
Internal Ring;  
75  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
SM[2:0] = '011':  
SM[2:0] = '100':  
SM[2:0] = '101':  
SM[2:0] = '110':  
SM[2:0] = '111':  
Ring Open;  
Tip Open;  
Internal Test;  
Low Power Standby;  
Power Down.  
LREG7: Analog Gain Selection, AC/DC Ring Trip Selection, Ring Generator and Tone Generators Enable, Read/Write (06H/86H)  
b7  
b6  
b5  
0
b4  
0
b3  
0
b2  
1
b1  
1
b0  
0
Command  
I/O data  
R/W  
0
Reserved  
IM_629  
RING  
RT_SEL  
RING_EN  
TG2_EN  
TG1_EN  
IM_629  
Analog Gain for Impedance Scaling (AGIS)  
IM_629 = 0:  
IM_629 = 1:  
600 (only for loops with 600 equivalent impedance) (default);  
900 (for all loops including those with 600 equivalent impedance).  
RING  
CODEC operating mode control bit  
RING = 0:  
RING = 1:  
Ring mode is disabled (default);  
Ring mode is enabled.  
RT_SEL  
RING_EN  
TG2_EN  
TG1_EN  
AC/DC ring trip selection  
RT_SEL = 0:  
RT_SEL = 1:  
AC Ring Trip is selected (default);  
DC Ring Trip is selected.  
Enable the internal ring generator  
RING_EN = 0:  
RING_EN = 1:  
internal ringing stops (default);  
internal ringing starts.  
Enable Tone Generator 2 (TG2)  
TG2_EN = 0:  
TG2_EN = 1:  
TG2 is disabled (default);  
TG2 is enabled.  
Enable Tone Generator 1 (TG1)  
TG1_EN = 0:  
TG1_EN = 1:  
TG1 is disabled (default);  
TG1 is enabled.  
LREG8: Ramp Generator Enable, Level Meter Path Selection and Notch/Bandpass Filter Characteristic Configuration, UTD Source  
Selection and UTD Enable, Read/Write (07H/87H)  
b7  
R/W  
b6  
b5  
b4  
0
b3  
0
b2  
1
b1  
1
b0  
1
Command  
I/O data  
0
0
Reserved LM_NOTCH  
LM_FILT  
LM_SRC  
DC_SRC  
UTD_SRC  
UTD_EN  
RAMP_EN  
RAMP_EN  
Enable Ramp Generator  
RAMP_EN = 0:  
RAMP_EN = 1:  
ramp generator is disabled (default);  
ramp generator is enabled.  
LM_NOTCH Level meter notch/bandpass filter characteristic selection  
LM_NOTCH = 0: notch filter characteristic is selected (default);  
LM_NOTCH = 1: bandpass filter characteristic is selected.  
LM_FILT  
Level meter filter (bandpass/notch) enable  
LM_FILT = 0:  
LM_FILT = 1:  
level meter filter (bandpass/notch) is disabled (default);  
level meter filter (bandpass/notch) is enabled.  
LM_SRC  
Level meter AC/DC source selection  
LM_SRC = 0:  
LM_SRC = 1:  
signal from DC path is selected for level metering (default);  
signal from AC path is selected for level metering.  
76  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
DC_SRC  
UTD_SRC  
UTD_EN  
DC transmit/receive path selection for level meter  
DC_SRC = 0:  
DC_SRC = 1:  
signal from DC receive path is selected for level metering (default);  
signal from DC transmit path is selected for level metering.  
UTD source selection  
UTD_SRC = 0:  
UTD_SRC = 1:  
signal from receive path is detected by the UTD unit (default);  
signal from transmit path is detected by the UTD unit.  
Enable the universal tone detection unit  
UTD_EN = 0:  
UTD_EN = 1:  
the UTD unit is disabled (default);  
the UTD unit is enabled.  
LREG9: Level Meter Source and Shift Factor Selection, Read/Write (08H/88H)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
0
0
1
0
0
0
K[3:0]  
LM_SEL[3:0]  
K[3:0]  
Shift factor selection for the level meter.  
K[3:0] = 0000:  
K[3:0] = 0001:  
K[3:0] = 0010:  
K[3:0] = 0011:  
K[3:0] = 0100:  
K[3:0] = 0101:  
K[3:0] = 0110:  
K[3:0] = 0111:  
K[3:0] = 1000:  
K[3:0] = 1001:  
K[3:0] = 1010:  
KINT = 1 (default);  
KINT = 1/2;  
KINT = 1/4;  
KINT = 1/8;  
KINT = 1/16;  
KINT = 1/32;  
KINT = 1/64;  
KINT = 1/128;  
KINT = 1/256;  
KINT = 1/512;  
KINT = 1/1024;  
K[3:0] = 1011 to 1111: KINT = 1/2048;  
LM_SEL[3:0] Source selection for DC Level Meter  
LM_SEL[3:0] = 0000: DC voltage on VTDC is selected (default);  
LM_SEL[3:0] = 0100: DC out voltage on DCN-DCP is selected;  
LM_SEL[3:0] = 1001: DC voltage on VL is selected;  
LM_SEL[3:0] = 1010: Voltage on IO3 is selected;  
LM_SEL[3:0] = 1011: Voltage on IO4 is selected;  
LM_SEL[3:0] = 1100: Voltage on RTIN is selected;  
LM_SEL[3:0] = 1101: VDD/2 is selected;  
LM_SEL[3:0] = 1110: VCM (offset of encoding) is selected;  
LM_SEL[3:0] = 1111: Voltage on IO4-IO3 is selected;  
LREG10: Level Meter Threshold, Rectifier On/Off, Gain Factor, Read/Write (09H/89H)  
b7  
b6  
0
b5  
0
b4  
b3  
b2  
b1  
0
b0  
Command  
I/O data  
R/W  
0
1
0
1
LM_GF  
LM_RECT  
Reserved  
LM_TH[2:0]  
OTHRE  
OTHRE  
Over threshold indication for level meter. This bit is read only.  
OTHRE = 0:  
OTHRE = 1:  
The level meter result is below the threshold (default);  
The level meter result is over the threshold.  
LM_GF  
Additional Gain Factor for level meter  
LM_GF = 0:  
LM_GF = 1:  
No additional gain factor is selected (default);  
Additional gain factor of 16 is selected.  
77  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LM_RECT  
Enable the rectifier in the level meter.  
LM_RECT = 0:  
LM_RECT = 1:  
The rectifier is disabled (default);  
The rectifier is enabled.  
LM_TH[2:0]  
Level meter threshold selection. If the absolute value of the level meter result exceeds the selected threshold, the  
OTHRE bit will be set to 1.  
LM_TH[2:0] = 000: Threshold is 0.0% (default);  
LM_TH[2:0] = 001: Threshold is 12.5%;  
LM_TH[2:0] = 010: Threshold is 25.0%;  
LM_TH[2:0] = 011: Threshold is 37.5%;  
LM_TH[2:0] = 100: Threshold is 50.0%;  
LM_TH[2:0] = 101: Threshold is 62.5%;  
LM_TH[2:0] = 110: Threshold is 75.0%;  
LM_TH[2:0] = 111: Threshold is 87.5%.  
LREG11: Debounce Filter Configuration, Read/Write (0AH/8AH)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
0
0
1
0
1
0
DB[3:0]  
DB_IO[3:0]  
DB[3:0]  
Debounce interval selection for off-hook and ground-key detection. The debounce interval is programmable from 0.125  
ms to 2 ms in steps of 0.125 ms, corresponding to the minimal debounce time of from 2 ms to 30 ms.  
DB[3:0] = 0000: the debounce interval is 0.125 ms, the minimal debounce time is 2 ms (default);  
DB[3:0] = 0001: the debounce interval is 0.250 ms, the minimal debounce time is 4 ms;  
DB[3:0] = 0010: the debounce interval is 0.375 ms, the minimal debounce time is 6 ms;  
...  
...  
...  
...  
...  
...  
DB[3:0] = 1110:  
DB[3:0] = 1111:  
the debounce interval is 1.875 ms, the minimal debounce time is 30 ms;  
the debounce interval is 2 ms, the minimal debounce time is 32 ms.  
(Note: During operating mode switching, there might be a narrow pulse of about 15 ms occurring on VTDC, resulting in  
a false interrupt to be generated. If this happens, please set DB[3:0] to 0111B or above to filter this noise pulse.)  
DB_IO[3:0]  
IO Pins debounce time selection (only effective for those IO pins used as digital inputs).The IO pins debounce time is  
programmable from 2.5 ms to 32.5 ms in steps of 2 ms.  
DB_IO[3:0] = 0000: the minimal debounce time is 2.5 ms (default);  
DB_IO[3:0] = 0001: the minimal debounce time is 4.5 ms;  
DB_IO[3:0] = 0010: the minimal debounce time is 6.5 ms;  
...  
...  
...  
...  
DB_IO[3:0] = 1110: the minimal debounce time is 30.5 ms;  
DB_IO[3:0] = 1111: the minimal debounce time is 32.5 ms.  
LREG12: PCM Data Low Byte Register, Read Only (0BH). This register is used for MPI mode only.  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
0
0
0
0
1
0
1
1
PCM[7:0]  
This register is used for the master processor to monitor the transmit (A to D) PCM data. For linear code, the low byte of PCM data is  
sent to this register before it is transmitted to the PCM Encoder in the transmit path. For compressed code, the total PCM data is sent to  
this register before it is transmitted to the PCM Encoder in the transmit path.  
78  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LREG13: PCM Data High Byte Register, Read Only (0CH). This register is used for MPI mode only.  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
0
0
0
0
1
1
0
0
PCM[15:8]  
This register is used for the master processor to monitor the transmit (A to D) PCM data. For linear code, the high byte of PCM data is  
sent to this register before it is transmitted to the PCM Encoder in the transmit path. For compressed code, this register is not used (in  
this case, when read, a data byte of 00H will be read out).  
LREG14: UTD RTIME Register, Read/Write (0DH/8DH)  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
R/W  
0
0
0
1
1
0
1
UTD_RT[7:0]  
This register is used to set the UTD Recognition Time (RTIME):  
UTD_RT[7:0] = RTIME (ms)/16  
The default value of UTD_RT[7:0] is 13H.  
RTIME must be multiples of 16 ms. The range of it is: 0 ms RTIME 4000 ms.  
LREG15: UTD RBKTime Register, Read/Write (0EH/8EH)  
b7 b6 b5  
R/W  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
0
0
0
1
1
1
0
UTD_RBK[7:0]  
This register is used to set the UTD Recognition Break Time (RBKTime):  
UTD_RBK[7:0] = RBKTime (ms)/4  
The default value of UTD_RBK[7:0] is 19H.  
RBKTime must be multiples of 4 ms. The range of it is: 0 ms RBKTime 1000 ms.  
LREG16: UTD ETIME Register, Read/Write (0FH/8FH)  
b7 b6  
R/W  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
0
0
0
1
1
1
1
UTD_ET[7:0]  
This register is used to set the UTD End Detection Time (ETIME):  
UTD_ET[7:0] = ETIME (ms)/4  
The default value of UTD_ET[7:0] is 40H.  
ETIME must be multiples of 4 ms. The range of it is: 0 ms ETIME 1000 ms.  
LREG17: UTD EBRKTime, Read/Write (10H/90H)  
b7 b6  
R/W  
b5  
b4  
b3  
b2  
b1  
b0  
Command  
I/O data  
0
0
1
0
0
0
0
UTD_EBRK[7:0]  
This register is used to set the UTD End Detection Break Time (EBRKTime):  
UTD_EBRK[7:0] = EBRKTime (ms)  
The default value of UTD_EBRK[7:0] is 64H.  
The range of the EBRKTime is: 0 ms EBRKTime 255 ms.  
79  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LREG18: Interrupt Mask Register, Read/Write (11H/91H)  
b7  
b6  
0
b5  
b4  
1
b3  
0
b2  
0
b1  
0
b0  
1
Command  
I/O data  
R/W  
0
Reserved  
GK_M  
HK_M  
OTMP_M  
RAMP_M  
GKP_M  
GK_M  
Mask bit for the ground-key status bits GK[3:0] in GREG26  
GK_M = 0:  
GK_M = 1:  
Each change of the GK[3:0] bits generates an interrupt;  
Changes of the GK[3:0] bits do not generate interrupts (default).  
HK_M  
Mask bit for the off-hook status bits HK[3:0] in GREG26  
HK_M = 0:  
HK_M = 1:  
Each change of the HK[3:0] bits generates an interrupt;  
Changes of the HK[3:0] bits do not generate interrupts (default).  
OTMP_M  
RAMP_M  
GKP_M  
Mask bit for the over temperature status bit OTMP in LREG21  
OTMP_M = 0:  
OTMP_M = 1:  
Changes of the OTMP bit from 0 to 1 generate interrupts;  
Changes of the OTMP bit from 0 to 1 do not generate interrupts (default).  
Mask bit for the RAMP_OK bit in LREG21  
RAMP_M = 0:  
RAMP_M = 1:  
Changes of the RAMP_OK bit from 0 to 1 generate interrupts;  
Changes of the RAMP_OK bit from 0 to 1 do not generate interrupt (default).  
Mask bit for the GK_POL bit in LREG21  
GKP_M = 0:  
GKP_M = 1:  
Each change of the GK_POL bit generates an interrupt;  
Changes of the GK_POL bit do not generate interrupts (default).  
LREG19: IO Interrupt Mask Register, Read/Write (12H/92H)  
b7  
b6  
b5  
0
b4  
1
b3  
0
b2  
0
b1  
1
b0  
0
Command  
I/O data  
R/W  
0
REV_POL  
SYNC_EN  
IO_M[3]  
IO_M[2]  
IO_M[1]  
IO_M[0]  
Reserved  
REV_POL  
SYNC_EN  
IO_M[3:0]  
Reverse the polarity of DC feeding  
REV_POL = 0:  
REV_POL = 1:  
Normal polarity (default);  
Reverse polarity.  
Enable synchronous ringing for external ringing mode.  
SYNC_EN = 0:  
SYNC_EN = 1:  
Asynchronous external ringing is selected (default);  
External ringing with zero-crossing is selected;  
Mask bits for the IO status bits IO[3:0] in register LREG19 when the IO pins are configured as inputs.  
IO_M[3] = 0:  
IO_M[3] = 1:  
Each change of the IO[3] bit generates an interrupt;  
Changes of the IO[3] bit do not generate interrupts (default).  
IO_M[2] = 0:  
IO_M[2] = 1:  
Each change of the IO[2] bit generates an interrupt;  
Changes of the IO[2] bit do not generate interrupts (default).  
IO_M[1] = 0:  
IO_M[1] = 1:  
Each change of the IO[1] bit generates an interrupt;  
Changes of the IO[1] bit do not generate interrupts (default).  
IO_M[0] = 0:  
IO_M[0] = 1:  
Each change of the IO[0] bit generates an interrupt;  
Changes of the IO[0] bit do not generate interrupts (default).  
80  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LREG20: RSLIC IO Direction Configuration and IO Status Register, Read/Write (13H/93H)  
b7  
b6  
0
b5  
0
b4  
1
b3  
0
b2  
0
b1  
1
b0  
1
Command  
I/O data  
R/W  
IO_C[3]  
IO_C[2]  
IO_C[1]  
IO_C[0]  
IO[3]  
IO[2]  
IO[1]  
IO[0]  
IO_C[3:0]  
RSLIC IO direction configuration. The IO_C[3:0] bits determine the directions of the IO4 to IO1 pins, respectively.  
IO_C[3] = 0:  
IO_C[3] = 1:  
The IO4 pin of the specified channel is configured as an input (default);  
The IO4 pin of the specified channel is configured as an output.  
IO_C[2] = 0:  
IO_C[2] = 1:  
The IO3 pin of the specified channel is configured as an input (default);  
The IO3 pin of the specified channel is configured as an output.  
IO_C[1] = 0:  
IO_C[1] = 1:  
The IO2 pin of the specified channel is configured as an input (default);  
The IO2 pin of the specified channel is configured as an output.  
IO_C[0] = 0:  
IO_C[0] = 1:  
The IO1 pin of the specified channel is configured as an input (default);  
The IO1 pin of the specified channel is configured as an output.  
IO[3:0]  
IO pin status (when the corresponding IO pin is configured as an input) or IO control data (when the corresponding IO  
pin is configured as an output)  
IO[3] = 0:  
The IO4 pin of the specified channel is in logic low state (when configured as an input) or it is set to  
logic low (when configured as an output);  
IO[3] = 1:  
The IO4 pin of the specified channel is in logic high state (when configured as an input) or it is set to  
logic high (when configured as an output);  
IO[2] = 0:  
IO[2] = 1:  
The IO3 pin of the specified channel is in logic low state (when configured as an input) or it is set to  
logic low (when configured as an output);  
The IO3 pin of the specified channel is in logic high state (when configured as an input) or it is set to  
logic high (when configured as an output);  
IO[1] = 0:  
IO[1] = 1:  
The IO2 pin of the specified channel is in logic low state (when configured as an input) or it is set to  
logic low (when configured as an output);  
The IO2 pin of the specified channel is in logic high state (when configured as an input) or it is set to  
logic high (when configured as an output);  
IO[0] = 0:  
IO[0] = 1:  
The IO1 pin of the specified channel is in logic low state (when configured as an input) or it is set to  
logic low (when configured as an output);  
The IO1 pin of the specified channel is in logic high state (when configured as an input) or it is set to  
logic high (when configured as an output);  
Once the IOn pin is configured as an input, each change of the corresponding IO[n] bit will generate an interrupt if the mask bit IO_M[n]  
in LREG19 is set to 0. A read command to this register will clear the interrupt caused by changes of the IO[3:0] bits.  
LREG21: Interrupt Source Register, Read Only (14H)  
b7  
0
b6  
0
b5  
0
b4  
1
b3  
0
b2  
1
b1  
0
b0  
0
Command  
I/O data  
FEED_V  
FEED_R  
LM_OK  
UTD_OK  
OTMP  
RAMP_OK  
GK_POL  
FEED_I  
FEED_I  
DC feeding characteristic indication bit for the constant current zone.  
Whenever the DC feeding is operated at the constant zone, the FEED_I is set to 1, otherwise it is set to 0.  
FEED_V  
FEED_R  
DC feeding characteristic indication bit for the constant voltage zone.  
Whenever the DC feeding is operated at the constant voltage zone, the FEED_V bit it is set to 1, otherwise it is set to 0.  
DC feeding characteristic indication bit for the resistive zone.  
Whenever the DC feeding is operated at the resistive zone, the FEED_R bit is set to 1, otherwise it is set to 0.  
81  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
LM_OK  
Indicating whether the level metering is finished. Changes of this bit from 0 to 1 generate interrupts (the LM_OK bit has  
no mask bit).  
LM_OK = 0:  
LM_OK = 1:  
Level meter result is not ready (default);  
Level meter result is ready.  
UTD_OK  
OTMP  
UTD result indication. Changes of this bit from 0 to 1 generate interrupts (the UTD_OK bit has no mask bit).  
UTD_OK = 0:  
UTD_OK = 1:  
No special tone signal (e.g., fax/modem) is detected (default);  
Special tone signal (e.g., fax/modem) is detected  
Over temperature detection result. Changes of this bit from 0 to 1 generate interrupts if the mask bit OTMP_M in register  
LREG18 is set to 0.  
OTMP = 0:  
OTMP = 1:  
Temperature at the RSLIC is below the limit (default);  
Temperature at the RSLIC is above the limit;  
RAMP_OK  
GK_POL  
Indicating whether ramp generation is completed. Changes of this bit from 0 to 1 generate interrupts if the mask bit  
RAMP_M in register LREG18 is set to 0. When the ramp generator starts a new generation, the RAMP_OK bit will be  
reset to 0.  
RAMP_OK = 0:  
RAMP_OK = 1:  
Ramp generation is not completed (default);  
Ramp generation is completed;  
ground-key polarity, indicating the active ground-key threshold (positive or negative). Changes of this bit generate inter-  
rupts if the mask bit GKP_M in register LREG18 is set to 0.  
GK_POL = 0:  
GK_POL = 1:  
Negative ground-key threshold is active;  
Positive ground-key threshold is active (default);  
Applying a read command to this register will clear the interrupt caused by the valid change of the LM_OK, UTD_OK, OTMP, RAMP_OK  
or GK_POL bit.  
82  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
5.4  
PROGRAMMING EXAMPLES  
5.4.1  
PROGRAMMING EXAMPLES FOR MPI MODE  
5.4.1.1  
Example of Programming the Local Registers via MPI  
Writing to LREG2 and LREG1 of Channel 1:  
1010,0011  
0001,0010  
1000,0001  
0000,0001  
0000,0000  
Channel Enable command  
Data for GREG4 (Channel 1 is enabled for programming)  
Local register write command (The address is '00001', means that data will be written to LREG2 and LREG1.)  
Data for LREG2  
Data for LREG1  
C hannel E nable  
C om m and  
D ata for LR E G 2  
D ata for LR E G 1  
Local C om m and  
C hannel E nable D ata  
C I  
C C LK  
CS  
Figure - 36 Waveform of Programming Example: Writing to Local Registers  
Reading LREG2 and LREG1 of Channel 1:  
1010,0011  
0001,0010  
0000,0001  
Channel Enable command  
Data for GREG4 (Channel 1 is enabled for programming)  
Local register read command (The address is '00001', means that LREG2 and LREG1 will be read.)  
After the preceding commands are executed, data will be sent out as follows:  
1000,0001  
0000,0001  
0000,0000  
Identification code  
Data read out from LREG2  
Data read out from LREG1  
Channel Enable  
Command  
Channel Enable Data  
Local Command  
CI  
Data read out from  
LREG2  
Data read out from  
LREG1  
Identification Code  
High 'Z'  
High 'Z'  
CO  
CCLK  
CS  
Figure - 37 Waveform of Programming Example: Reading Local Registers  
83  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
5.4.1.2 Example of Programming the Global Registers via MPI  
INDUSTRIAL TEMPERATURE RANGE  
Since the global registers are shared by all four channels, it is no need to specify the channel(s) before addressing global registers. Except for this,  
programming global registers are the same as programming local registers. Refer to “5.4.1.1 Example of Programming the Local Registers via MPI”  
on page 83 for more information.  
5.4.1.3  
Example of Programming the Coefficient-RAM via MPI  
Writing to the Coe-RAM of Channel 1:  
1010,0011  
0001,0010  
1110,0000  
byte 1  
Channel Enable command  
Data for GREG4 (Channel 1 is enabled for programming)  
Coe-RAM write command (The address of '00000' is located in block 1, means that data will be written to block 1.)  
data for high byte of word 8 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 8 in block 1  
byte 2  
byte 3  
byte 4  
data for high byte of word 7 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 7 in block 1  
byte 5  
byte 6  
data for high byte of word 6 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 6 in block 1  
byte 7  
byte 8  
data for high byte of word 5 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 5 in block 1  
byte 9  
data for high byte of word 4 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 4 in block 1  
data for high byte of word 3 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 3 in block 1  
data for high byte of word 2 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 2 in block 1  
data for high byte of word 1 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 1 in block 1  
byte 10  
byte 11  
byte 12  
byte 13  
byte 14  
byte 15  
byte 16  
Reading from the Coe-RAM of Channel 1:  
1010,0011  
0001,0010  
0110,0000  
Channel Enable command  
Data for GREG4 (Channel 1 is enabled for programming)  
Coe-RAM read command (The address of '00000' is located in block 1, means that block 1 will be read.)  
After the preceding commands are executed, data will be sent out as follows:  
1000,0001  
byte 1  
byte 2  
Identification code  
data read out from high byte of word 8 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 8 in block 1  
byte 3  
byte 4  
data read out from high byte of word 7 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 7 in block 1  
byte 5  
byte 6  
data read out from high byte of word 6 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 6 in block 1  
byte 7  
byte 8  
data read out from high byte of word 5 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 5 in block 1  
byte 9  
data read out from high byte of word 4 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 4 in block 1  
data read out from high byte of word 3 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 3 in block 1  
data read out from high byte of word 2 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 2 in block 1  
data read out from high byte of word 1 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 1 in block 1  
byte 10  
byte 11  
byte 12  
byte 13  
byte 14  
byte 15  
byte 16  
5.4.1.4  
Example of Programming the FSK-RAM via MPI  
• Writing to the FSK-RAM:  
1100,0001  
FSK-RAM write command (The address is '00001', means that data will be written to word 2 and word 1.)  
byte 1  
byte 2  
byte 3  
byte 4  
data for high byte of word 2  
data for low byte of word 2  
data for high byte of word 1  
data for low byte of word 1  
84  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Reading from the FSK-RAM:  
0100,0001  
FSK-RAM read command (The address is '00001', means that word 2 and word 1 will be read.)  
After this command is executed, data will be sent out as follows:  
1000,0001  
byte 1  
byte 2  
byte 3  
byte 4  
Identification code  
data read out from high byte of word 2  
data read out from low byte of word 2  
data read out from high byte of word 1  
data read out from low byte of word 1  
5.4.2  
PROGRAMMING EXAMPLES FOR GCI MODE  
5.4.2.1  
Example of Programming the Local Registers via GCI  
Writing to LREG2 and LREG1 of Channel 1:  
1000,0001  
1000,0001  
0000,0001  
0000,0000  
Program start command (provided channel A is the destination)  
Local register write command (The address is '00001', means that data will be written to LREG2 and LREG1.)  
data for LREG2  
data for LREG1  
Reading from LREG2 and LREG1 of Channel 1:  
1000,0001  
0000,0001  
Program start command (provided channel A is the source)  
Local register read command (The address is '00001', means that LREG2 and LREG1 will be read.)  
After the preceding commands are executed, data will be read out as follows:  
1000,0001  
0000,0001  
0000,0000  
Program start byte  
data read out from LREG2  
data read out from LREG1  
5.4.2.2  
Example of Programming the Global Registers via GCI  
In GCI mode, the global registers are addressed in the similar manner as the local registers except the A/B bit in the Program Start byte is  
neglected. See the descriptions above for details.  
5.4.2.3  
Example of Programming the Coefficient-RAM via GCI  
Writing to the Coe-RAM of Channel 1:  
1000,0001  
1110,0000  
byte 1  
Program Start command (provided channel A is the destination)  
Coe-RAM write command (The address is '00001', means that data will be written to block 1.)  
data for high byte of word 8 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 8 in block 1  
byte 2  
byte 3  
byte 4  
data for high byte of word 7 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 7 in block 1  
byte 5  
byte 6  
data for high byte of word 6 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 6 in block 1  
byte 7  
byte 8  
data for high byte of word 5 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 5 in block 1  
byte 9  
data for high byte of word 4 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 4 in block 1  
data for high byte of word 3 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 3 in block 1  
data for high byte of word 2 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 2 in block 1  
data for high byte of word 1 in block 1 (the highest two bits (b7b6) are ignored)  
data for low byte of word 1 in block 1  
byte 10  
byte 11  
byte 12  
byte 13  
byte 14  
byte 15  
byte 16  
Reading from the Coe-RAM of Channel 1:  
1000,0001  
0110,0000  
Program Start command (provided channel A is the source)  
Coe-RAM read command (The address is '00000', means that block 1 will be read.)  
After these commands are executed, data will be sent out as follows:  
1000,0001  
byte 1  
Program start byte  
data read out from high byte of word 8 in block 1 (the highest two bits (b7b6) are meaningless)  
85  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
byte 2  
byte 3  
byte 4  
byte 5  
byte 6  
byte 7  
byte 8  
byte 9  
byte 10  
byte 11  
byte 12  
byte 13  
byte 14  
byte 15  
byte 16  
data read out from low byte of word 8 in block 1  
data read out from high byte of word 7 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 7 in block 1  
data read out from high byte of word 6 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 6 in block 1  
data read out from high byte of word 5 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 5 in block 1  
data read out from high byte of word 4 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 4 in block 1  
data read out from high byte of word 3 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 3 in block 1  
data read out from high byte of word 2 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 2 in block 1  
data read out from high byte of word 1 in block 1 (the highest two bits (b7b6) are meaningless)  
data read out from low byte of word 1 in block 1  
5.4.2.4  
Example of Programming the FSK-RAM via GCI  
Writing to the FSK-RAM:  
100X,0001  
1100,0001  
byte 1  
byte 2  
byte 3  
Program Start command  
FSK-RAM write command (The address is '00001', means that data will be written to word 2 and word 1.)  
data for high byte of word 2  
data for low byte of word 2  
data for high byte of word 1  
data for low byte of word 1  
byte 4  
Reading from the FSK-RAM:  
100X,0001  
0100,0001  
Program Start command  
FSK-RAM read command (The address is '00001', means that word 2 and word 1 will be read.)  
After the preceding commands are executed, data will be sent out as follows:  
100X,0001  
byte 1  
byte 2  
byte 3  
byte 4  
Program Start byte  
data read out from high byte of word 2  
data read out from low byte of word 2  
data read out from high byte of word 1  
data read out from low byte of word 1  
86  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
RSLIC CONTROL SIGNALING  
6.1.1  
6
OPERATIONAL DESCRIPTION  
The CODEC provides three common mode selection pins M1 to M3  
and four individual chip selection pins CS1 to CS4 for the four RSLICs to  
control their operating modes. See Figure - 38 for details.  
The CS1 to CS4 pins of the CODEC are ternary logic pins as  
illustrated in the following:  
6.1  
OPERATING MODES  
In many applications, the system power consumption is an important  
parameter. For large and remotely fed systems, this parameter is more  
critical and must be limited to a given value to meet cooling  
requirements and save power.  
CSn = 0:  
The CODEC will send mode control data to the RSLICn  
through the M1 to M3 pins.  
Generally, the system power dissipation is determined mainly by the  
high-voltage part. The most effective power-saving method is to limit  
SLIC functionality and reduce supply voltage in line according to  
different requirements. The RSLIC-CODEC chipset achieves this goal  
by providing different operating modes according to different loop states  
or testing requirements. See the following descriptions for details.  
CSn = 1:  
The CODEC will receive the temperature information of  
the RSLICn through the M3 pin.  
CSn = 1.5 V:The CODEC will not send or receive data to/from the  
RSLICn through the M1 to M3 pins.  
Note that the M3 pin of the CODEC is bidirectional. Its direction is  
determined by the active CSn as described above. Figure - 39 shows  
the RSLIC control timing diagram.  
RSLIC 1#  
CODEC  
CS  
CS1  
M1~M3  
M1~M3  
RSLIC 2#  
CS  
CS2  
M1~M3  
RSLIC 3#  
CS3  
CS4  
CS  
M1~M3  
RSLIC 4#  
CS  
M1~M3  
Figure - 38 RSLIC Mode Control Signaling  
87  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
125 µs  
31.25 µs  
FS  
7.8125 µs  
CS1  
CS2  
CS3  
CS4  
M1  
M2  
M3  
output  
output  
output  
M3 I/O Control  
output  
input  
input  
input  
input  
Figure - 39 RSLIC Control Timing Diagram  
88  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
6.1.2 RSLIC OPERATING MODES  
INDUSTRIAL TEMPERATURE RANGE  
The RSLICs can be operated in nine different modes as shown in  
Table - 26. The operating mode is configured by the SM[2:0] bits in  
LREG6 (MPI mode) or in the downstream C/I channel (GCI mode).  
The SCAN_EN bit in LREG6 (MPI mode) or downstream C/I channel  
(GCI mode) determines whether the corresponding RSLIC will be  
accessed. If this bit is set to 1, the RSLIC will receive data from the  
CODEC when the corresponding CSn pin is logic low and transmit data  
to the CODEC when the corresponding CSn pin is logic high (as  
illustrated in Figure - 39). If this bit is set to 0, the corresponding CSn pin  
will be set to 1.5 V and the RSLIC will not be accessed.  
RS  
TIS  
TIP  
RSLIC  
2 k  
RING  
Table - 26 RSLIC Operating Mode  
RS  
RSLIC Mode Control Pins  
RSLIC Operating Mode  
RIS  
CS  
M3  
M2  
M1  
0
Normal Active  
External Ring  
Internal Ring  
0
0
0
0
0
0
1
Figure - 40 RSLIC Internal Test Circuit  
• Low Power Standby  
0
0
1
0
Ring Open  
0
0
1
1
In this mode, all functions except off-hook detection are switched off  
to reduce power consumption. Two 2.5 kresistors are connected from  
TIP to BGND and from RING to VBAT respectively. A simple sense  
circuit monitors the DC current flowing through these resistors. By  
calculating the transversal DC current and feeding it to the CODEC, off-  
hook can be detected. Once the subscriber goes off-hook, the whole  
chipset should be activated and put into active mode.  
Tip Open  
0
1
0
0
Internal Test  
0
1
0
1
Low Power Standby  
Power Down  
0
1
1
0
0
1
1
1
Overtemp Check (read)  
1
X
1
1
• Power Down  
In this mode, all functions are disabled, including the off-hook  
detection. The tip and ring power amplifiers are both switched off so that  
the power consumption is minimal.  
• Normal Active  
In this mode, a regular call can be performed. Voice can be  
transferred via the telephone line. Besides providing low-impedance  
voltage (VBL) feeding to the line, the RSLIC senses, scales and  
separates transversal and longitudinal line currents.  
• External Ring  
The RSLIC receives an external ringing signal provided at pins RSP  
and RSN and feeds it to the telephone line. The RSLIC also provides a  
ring trip signal for the CODEC via the RT pin.  
• Overtemp Check  
In this mode, the RSLIC will report the temperature state of itself to  
the CODEC through the M3 pin. This temperature state will be indicated  
by the OTMP bit in LREG21. If the temperature exceeds the limit  
o
(150 C), the RSLIC will be automatically shut down. Every time the  
OTMP bit changes from 0 to 1, representing the temperature of the  
RSLIC becoming overloaded, an interrupt will be generated if the OTMP  
bit is not masked by the OTMP_M bit in LREG18.  
• Internal Ring  
The CODEC generates a balanced ringing signal and outputs it to  
the RSLIC through the DCP and DCN pins. The RSLIC amplifies this  
ringing signal and feeds it to the telephone line.  
6.1.3  
CODEC OPERATING MODES  
• Ring Open  
The CODEC can work in five modes: Power Down, Standby, Active,  
Ramp and Ring. These modes are enabled by setting the P_DOWN,  
STANDBY, ACTIVE and RAMP bits in LREG6 and RING bit in LREG7  
respectively.  
In ring open mode, the ring power amplifier is switched off and the  
ring terminal presents a high impedance to the line. This mode is used to  
measure the leakage current Tip/GND.  
• Tip Open  
• Power Down  
In tip open mode, the tip power amplifier is switched off and the tip  
terminal presents a high impedance to the line. This mode is used for  
ground-key detection and the leakage current Ring/GND measurement.  
• Internal Test  
This mode can be used to test the RSLIC-CODEC chipset without  
external circuits.  
When the RSLIC is set to internal test mode, it works in a similar way  
as normal active mode. The only difference is that a built-in resistor will  
be connected between the TIP and RING pins to form a loop for testing.  
See Figure - 40 for details.  
This mode is applicable for the line (channel) that is not in use. In this  
mode, all functions of the CODEC are switched off so that the power  
dissipation can be minimized. Both AC and DC loops are inactive, no  
current is fed to the line and the hook switch can not be detected.  
Each channel of the CODEC can be powered down individually by  
setting the P_DOWN bit in corresponding LREG6. If four channels are  
powered down, the clock cycles fed to the MCLK and BCLK pins should  
be shut off to achieve the lowest power consumption.  
The CODEC can be changed from Power Down mode to any other  
modes by properly setting LREG6 and LREG7.  
89  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
• Standby  
6.2  
PLL POWER DOWN  
The standby mode is applicable for system state of subscriber being  
on-hook. In this mode, only the AC loop is active, all functions except for  
the off-hook detection are switched off. The sensed voltage from the  
RSLIC is fed to an analog comparator in the CODEC via VTAC pin. The  
loop state can be determined by comparing the sensed voltage with a  
fixed off-hook threshold. If off-hook state is detected, the overall circuits  
should be activated and switched to the active mode.  
The PLL_PD bit in GREG1 is used to power down the PLL block of  
the CODEC to reduce the power consumption. If the PLL_PD bit is set to  
1, the PLL block is turned off and the DSP operation is disabled. As  
described above, each of the channels can be individually powered  
down by setting the corresponding P_DOWN bit in LREG6 to 1. When  
all four channels and the PLL block are powered down, the lowest power  
consumption can be achieved.  
• Active  
The active mode corresponds to the system state of off-hook. In this  
mode, both AC and DC loops are active. The RSLIC provides low-  
impedance voltage (VBL) fed to the line. The RSLIC senses the  
transversal and longitudinal line currents and separates the transversal  
current to AC and DC parts. The CODEC scales the currents and  
converts the AC part of the transversal current to voice data. On the  
other hand, the CODEC expands the voice data from the PCM bus and  
converts them to an analog signal. The DC voltage fed to the line can be  
automatically achieved by the chipset according to certain loop lengths,  
power optimized solution.  
6.3  
PROGRAMMABLE I/OS OF THE CODEC  
The CODEC provides four programmable IO pins per channel as  
shown in the following:  
IO1:  
IO2:  
IO3:  
IO4:  
IO pin with relay-driving capability  
IO pin with relay-driving capability  
IO pin with analog input capability  
IO pin with analog input capability  
The four IO pins IO4 to IO1 can be independently configured as input  
or output by the corresponding control bits IO_C[3] to IO_C[0] in  
LREG20.  
If the IO pins are configured as inputs, the status of the IO pins will be  
indicated by the IO[3:0] bits in LREG20. If the IO pins are configured as  
outputs, the data written in the IO[3:0] bits in LREG20 will be sent out  
through the IO pins.  
If the IO1 and IO2 pins are configured as outputs, they are capable of  
driving external relays. Based on this, the IO1 pin automatically acts as  
an output to control the external ring relay when external ringing mode is  
selected. Refer to “3.4.2 External Ringing Mode” on page 24 for details.  
If the IO3 and IO4 pins are configured as inputs, they are capable of  
receiving analog inputs. With this capability external voltages can be fed  
to the DC level meter via the IO3 and/or IO4 pins to be measured. Refer  
to “3.9.6.6 Voltage Measurement” on page 48 for details.  
• Ring  
This mode corresponds to the system state of ringing. The chipset  
provides both internal ringing and external ringing modes to be selected.  
Refer to Table - 26 for details.  
If internal ringing mode is selected, an internal balanced ringing  
signal of up to 70 Vp (with high voltage battery (VBH) of 70 V) can be  
generated without any external components. In applications that high  
ringing voltage is not needed, a DC offset can be added to support the  
DC ring trip detection, which is more reliable than AC ring trip detection.  
If an external ring generator and ring relays are used, the RSLIC can  
be switched to power down mode. An individual operation amplifier in  
the RSLIC is supplied for ring trip detection.  
• Ramp  
If ramp mode is selected (LREG6: RAMP = 1), the integrated ramp  
generator in the CODEC is active and able to generate a ramp signal to  
help measuring the capacitance. The ramp generator is fully  
programmable. By programming the ramp slope, ramp start voltage and  
end voltage, a desired ramp can be generated by the CODEC and  
output to the line via the RLSIC. With this ramp signal as the source, the  
line capacitance can be measured via the DC level meter. See “3.9.6.5  
Capacitance Measurement” on page 47 for detailed information.  
The input signals from the four IOs will be filtered by a programmable  
debounce filter (see Figure - 41). The output of the debounce filter  
remains in its present state unless the input remains in the opposite  
state for the entire period of time programmed by the DB_IO[3:0] bits in  
LREG11. The debounce period is programmable from 0 ms to 30 ms in  
steps of 2 ms, corresponding to the minimal debounce time of 2.5 ms to  
32.5 ms (a delay time of about 2.5 ms added). The default value of  
DB_IO[3:0] is ‘0000’.  
IO  
Debounced IO  
D
Q
D
Q
D
Q
D
Q
En  
DB_IO[3:0]  
Debounce Period  
D
Q
(0 30ms)  
8 bit Debounce  
Counter  
FS  
RST  
Figure - 41 IO Debounce Filter  
90  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
The debounced IO data are stored in the IO[3:0] bits in LREG20. The  
four bits IO[3] to IO[0] have their respective mask bits - IO_M[3] to  
IO_M[0] in LREG19. Each change of the IO[n] bit will generate an  
interrupt if its mask bit IO_M[n] is set to 0 (n = 0 to 3).  
• Level metering finished  
• Special tone detected  
• Ramp generation finished  
The interrupt status register GREG26 contains the results of hook/  
ring trip detection and ground-key detection for four channels (two bits  
per channel). Other interrupt status of each channel is contained by the  
respective interrupt status registers LREG20 and LREG21 (each  
interrupt function has one bit). These bits are set when an interrupt is  
pending for the associated source. Two interrupt mask registers  
(LREG18 and LREG19) per channel contain one mask bit for each of  
the above interrupt functions except special tone detected and level  
metering completed. If a mask bit is set to high, the corresponding  
interrupt will be masked. Refer to Table - 27 for detailed information.  
6.4  
INTERRUPT HANDLING  
The RSLIC-CODEC chipset is capable of generating interrupts for  
the following event:  
• Off-hook/on-hook detected  
• ground-key detected  
• ground-key polarity changed  
• Ring trip detected  
• IO status changed  
• Over temperature detected  
Table - 27 Interrupt Source and Interrupt Mask  
Interrupt Source  
Hook Status  
Ground-key Status  
Ring Trip Status  
Status bits  
Interrupt Generating Conditions  
Each change of the HK[n] bit  
Each change of the GK[n] bit  
Each change of the HK[n] bit  
Mask Bit  
HK_M bit in LREG18  
GK_M bit in LREG18  
HK_M bit in LREG18  
HK[n] bit in GREG26 (n = 0 to 3)  
GK[n] bit in GREG26 (n = 0 to 3)  
HK[n] bit in GREG26 (n = 0 to 3)  
Each change of the IO[n] bit when the corresponding IO  
pin is configured as an input  
RSLIC IO Status  
IO[n] bit in LREG20 (n = 0 to 3)  
IO_M[n] bit in LREG19  
Ground-key Polarity  
Over Temperature Status  
Ramp Generation  
UTD Result  
GK_POL bit in LREG21  
OTMP bit in LREG21  
RAMP_OK bit in LREG21  
UTD_OK bit in LREG21  
LM_OK bit in LREG21  
Each change of the GK_POL bit  
GKP_M bit in LREG18  
OTMP_M bit in LREG18  
RAMP_M bit in LREG18  
None  
A change of the OTMP bit from 0 to 1  
A change of the RAMP_OK bit from 0 to 1  
A change of the UTD_OK bit from 0 to 1  
A change of the LM_OK bit from 0 to 1  
Level Meter Sequence  
None  
In MPI mode, the interrupt output pin INT/INT will be set to active  
level if any interrupt is generated. In GCI mode, if any interrupt is  
generated in a channel, the corresponding INT_CHA or INT_CHB bit in  
upstream C/I channel will be set to active level. The valid polarity of the  
INT/INT pin and the INT_CHA, INT_CHB bits is determined by the  
INT_POL bit in register GREG24 as shown below:  
status registers will be cleared.  
A hardware or power-on reset of the CODEC clears all interrupt  
status registers and resets the INT/INT pin to inactive (MPI mode) or  
resets the INT_CHA and INT_CHB bits in the GCI C/I channel (GCI  
mode). A software reset applied to one channel clears all local interrupt  
status registers of that channel but does not effect those of the other  
channels and the global interrupt status register.  
INT_POL = 0: active low;  
INT_POL = 1: active high.  
In both MPI and GCI mode, the pending interrupts can be cleared by  
a read operation on the corresponding interrupt register. For example,  
reading GREG26 clears the interrupts generated by hook/ring trip  
detection and ground-key detection. Additionally, the CODEC provides a  
dedicated command to clear all the interrupts at one time. That is, by  
applying a write operation to GREG26, all the global and local interrupt  
6.5  
SIGNAL PATH AND TEST LOOPBACKS  
Figure - 42 on the following page shows the main AC and DC signal  
paths and the integrated analog and digital loopbacks inside the  
CODEC. Refer to the register descriptions on GREG6 and LREG3 for  
details.  
91  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Figure - 42 AC/DC Signal Path and Test Loopbacks  
92  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
In GCI mode, time slot assignment is determined by the logic  
levels of the CCLK/S0 and CI/S1 pins. The data rate is always  
2.048 MHz, no matter 2.048 MHz or 4.096 MHz is applied to the  
DCL pin. The GCI data is transferred via the DU/DD pin on rising  
edges of DCL.  
6.6  
RSLIC POWER ON SEQUENCE  
It is recommended to power on the RSLIC following the sequence  
below:  
1. Apply Ground to the AGND and BGND pins;  
2. Apply +3.3 V power supply to the VDD pin;  
6. A-law is selected;  
7. Default register settings are selected;  
8. All IO pins are configured as inputs;  
9. All maskable interrupts are masked by corresponding mask bits;  
10.All function blocks including level meter, UTD unit, FSK generator,  
tone generators etc., are disabled.  
3. Apply battery voltage (70 V VBH ≤ −52 V) to the VBH pin;  
4. Apply battery voltage (52 V VBL ≤ −20 V) to the VBL pin;  
But if the recommended application circuit (Figure - 49 on page 104  
or Figure - 50 on page 105) is used, the above mentioned RSLIC power  
on sequence is not necessary.  
6.7  
CODEC POWER ON SEQUENCE  
6.8.2  
SOFTWARE RESET  
Each channel of the CODEC can be individually reset by a software  
reset command. The RCH_SEL[3:0] bits in GREG5 determine whether  
Channel 4 to Channel 1 will be software reset or not. Setting the  
SW_RST bit and any desired bit of RCH_SEL[3:0] to 1 will reset the  
corresponding channel. Once a software reset is performed, the device  
will enter the following state:  
To power on the CODEC, the operating sequence should be as  
follows:  
1. Apply Ground to all ground pins;  
2. Apply VDD voltage to all power supply pins;  
3. Select master clock frequency (via GREG4);  
4. Program filter coefficients and other parameters as required.  
1. The reset channel(s) are powered down;  
2. All test loopbacks and cutoff on the reset channel(s) are disabled;  
3. The DX1/DU and DR1/DD pins are selected for the reset  
channel(s) to transmit and receive PCM data.  
6.8  
DEFAULT STATE AFTER RESET  
6.8.1  
POWER-ON RESET AND HARDWARE RESET  
4. In MPI mode, Time Slot 0 to Time Slot 3 are selected for Channel  
1 to Channel 4 to transmit and receive the PCM data. The PCM  
data rate is the same as the Bit Clock (BCLK) frequency. The  
PCM data is transmitted on the rising edges of BCLK and  
received on the falling edges.  
The CODEC can be reset by a power-on reset or a hardware reset. A  
hardware reset of the CODEC can be accomplished by setting the signal  
to the RESET pin to low level for at least 50 µs or setting the HW_RST  
bit in GREG5 to 1. After a power-on reset or a hardware reset, the  
default register settings are used. The CODEC will then enter the default  
state as described below:  
In GCI mode, time slot assignment is determined by the logic  
levels of the CCLK/S0 and CI/S1 pins. The data rate is always  
2.048 MHz, no matter 2.048 MHz or 4.096 MHz is applied to the  
DCL pin. The GCI data is transferred via DU/DD pin on rising  
edges of DCL.  
1. All four channels are powered down;  
2. All loopbacks and cutoff are disabled;  
3. The DX1/DU pin is selected for all channels to transmit PCM  
data. The DR1/DD pin is selected for all channels to receive PCM  
data.  
4. The master clock (MCLK) frequency is 2.048 MHz;  
5. In MPI mode, Time Slot 0 to Time Slot 3 are selected for Channel  
1 to Channel 4 to transmit and receive data. The PCM data rate is  
the same as the Bit Clock (BCLK) frequency. The PCM data is  
transmitted on the rising edges of BCLK and received on the  
falling edges.  
5. All default coefficients and register setting except the highpass  
filter (the HPF bit in LREG5 is set to 1) are selected for the reset  
channel(s).  
6. All IO pins of the reset channel(s) are configured as inputs;  
7. All maskable interrupts of the reset channel(s) are masked by  
corresponding mask bits.  
93  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
7
ELECTRICAL CHARACTERISTICS  
7.1  
RSLIC ELECTRICAL CHARACTERISTICS  
7.1.1  
RSLIC ABSOLUTE MAXIMUM RATINGS  
Ratings  
Min.  
Max.  
Unit  
V
Power supply voltage VDD  
VDD-VBH  
0.5  
+5  
75  
V
Tip/Ring negative pulse  
Tip/Ring positive pulse  
ESD voltage (Human body model)  
VBH 0.7  
VDD + 0.7  
1
V
V
kV  
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended  
periods may affect reliability.  
7.1.2  
RSLIC RECOMMENDED OPERATING CONDITIONS  
Parameter  
Min.  
40  
Max.  
+85  
Unit  
°C  
V
Operating temperature  
Power supply voltage VDD  
Low battery power supply VBL  
High battery power supply VBH  
+3.135  
52  
+3.465  
20  
V
70  
52  
V
7.1.3  
RSLIC THERMAL INFORMATION  
Parameter  
Min.  
Max.  
70  
Unit  
°C/W  
°C  
Thermal resistance  
Maximum junction temperature (plastic)  
150  
7.1.4  
RSLIC POWER CONSUMPTION  
Description  
Min.  
Typ.  
90  
Max.  
100  
180  
450  
Units  
mW  
Test Conditions  
RSLIC power consumption in power down mode  
RSLIC power consumption in standby mode  
RSLIC power consumption in normal active mode  
VDD = +3.3 V, VBH = 70 V, VBL = 48 V;  
without load.between the Tip pin and the  
Ring pin.  
160  
400  
mW  
mW  
94  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
7.2  
CODEC ELECTRICAL CHARACTERISTICS  
7.2.1  
CODEC ABSOLUTE MAXIMUM RATINGS  
Ratings  
Min.  
0.3  
0.3  
0.3  
0.3  
0.3  
Max.  
4.6  
+0.3  
+0.3  
3.6  
5.5  
100  
125  
85  
Unit  
V
Supply pins referred to the corresponding ground pin  
Ground pins referred to any other ground pin  
Supply pins referred to any other supply pin  
Analog input and output pins  
V
V
V
Digital input and output pins  
V
DC input and output current at any input or output pin (free from latch-up)  
Storage temperature  
mA  
°C  
°C  
W
kV  
65  
40  
Ambient temperature under bias  
Power dissipation  
1
ESD voltage (Human body model)  
2
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended  
periods may affect reliability.  
7.2.2  
CODEC RECOMMENDED OPERATING CONDITIONS  
Description  
Min.  
+3.135  
0
Typ.  
Max.  
+3.465  
+3.3  
Units  
V
Test Conditions  
Supply pins referred to the corresponding ground pin  
Analog input pins referred to the ground pin  
Ambient temperature  
+3.3  
V
40  
+85  
°C  
7.2.3  
CODEC DIGITAL INTERFACE  
Parameter  
Description  
Input low voltage  
Min.  
2.0  
Typ.  
Max.  
Units  
V
Test Conditions  
VIL  
VIH  
VOL  
VOH  
VAOL  
VAOH  
II  
0.8  
0.8  
0.4  
All digital inputs  
All digital inputs  
IL = 4 mA  
Input high voltage  
V
Output low voltage  
V
IL = 4 mA  
Output high voltage  
VDD 0.6  
V
IL = 10 mA  
Output low voltage on relay driver pin  
Output high voltage on relay driver pin  
Input current  
V
IL = 4 mA  
VDD 0.6  
10  
V
10  
10  
5
µA  
µA  
pF  
All digital inputs  
IOZ  
Output current in high-impedance digital pin  
Input capacitance  
10  
CI  
7.2.4  
CODEC POWER DISSIPATION  
Parameter  
VDD  
Description  
Power supply voltage  
Operating current  
Min.  
Typ.  
3.3  
95  
Max.  
Units  
V
Test Conditions  
IDD1  
mA  
mA  
IDD0  
Standby current  
7
95  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
7.3  
CHIPSET TRANSMISSION CHARACTERISTICS  
0 dBm0 of PCM bus is defined as 0.775 Vrms for 600 load. 0 dBm0 of analog input or output of the CODEC is relative to the 0 dBm0 of the PCM  
bus output or input. Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave. The digital input is a PCM bit stream equivalent to that  
obtained by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. The output level is sin(x)/x-corrected. Typical values are tested at VDD  
= 3.3 V and TA = 25°C.  
7.3.1  
ABSOLUTE GAIN  
Description  
Parameter  
Min.  
0.25  
0.25  
Typ.  
Max.  
0.25  
0.25  
Units  
dB  
Test Conditions  
GXA  
GRA  
Transmit gain, absolute  
Receive gain, absolute  
Signal output of 0 dBm0, normal mode  
A-law or µ-law, PCM input of 0 dBm0, 1014 Hz  
dB  
7.3.2  
GAIN TRACKING  
Description  
Parameter  
GTX  
Min.  
Typ.  
Max.  
Units  
Test Conditions  
Transmit gain tracking  
+3 dBm0 to 40 dBm0  
40 dBm0 to 50 dBm0  
50 dBm0 to 55 dBm0  
0.25  
0.5  
1.4  
0.25  
0.5  
1.4  
Tested by sinusoidal method, A-law or µ-law,  
f = 1014 Hz, reference level 10 dBm0  
dB  
Receive gain tracking  
+3 dBm0 to 40 dBm0  
40 dBm0 to 50 dBm0  
50 dBm0 to 55 dBm0  
0.25  
0.5  
1.4  
0.25  
0.5  
1.4  
Tested by sinusoidal method, A-law or µ-law,  
f = 1014 Hz, reference level 10 dBm0  
GTR  
dB  
7.3.3  
FREQUENCY RESPONSE  
Parameter  
Description  
Min.  
Typ.  
Max.  
Units  
Test Conditions  
Transmit gain, relative to GXA  
30  
30  
0.25  
0.25  
0.10  
35  
f = 50 Hz  
f = 60 Hz  
f = 300 Hz to 3000 Hz  
f = 3000 Hz to 3400 Hz  
f = 3600 Hz  
GXR  
0.25  
0.40  
dB  
The highpass filter is enabled.  
f 4600 Hz  
Receive gain, relative to GRA  
0.10  
0.25  
0.25  
0.20  
35  
f < 300 Hz  
0.25  
0.40  
f = 300 Hz to 3000 Hz  
f = 3000 Hz to 3400 Hz  
f = 3600 Hz  
GRR  
dB  
f 4600 Hz  
7.3.4  
RETURN LOSS  
Parameter  
Description  
Return loss (2-wire)  
Min.  
26  
Typ.  
Max.  
Units  
dB  
Test Conditions  
300 - 3400 Hz  
300 - 3400 Hz  
300 - 3400 Hz  
300 - 3400 Hz  
RL  
HB  
L-4  
L-T  
Hybrid balance (4-wire)  
Input longitudinal interface loss  
Longitudinal conversion loss  
26  
dB  
52  
55  
55  
dB  
52  
dB  
96  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
7.3.5  
GROUP DELAY  
Description  
Parameter  
Min.  
Typ.  
Max.  
Units  
Test Conditions  
Transmit delay, relative to 1800 Hz  
f = 500 Hz to 600 Hz  
80  
80  
DXR  
f = 600 Hz to 1000 Hz  
µs  
f = 1000 Hz to 2600 Hz  
f = 2600 Hz to 2800 Hz  
50  
280  
Receive delay, relative to 1800 Hz  
f < 300 Hz  
50  
80  
120  
150  
DRR  
DR  
f = 300 Hz to 3400 Hz  
f = 3600 Hz  
f 4600 Hz  
µs  
µs  
Round-trip delay  
900  
7.3.6  
DISTORTION  
Parameter  
Description  
Min.  
Typ.  
Max.  
Units  
Test Conditions  
Transmit signal to total distortion ratio  
45 dBm0  
40 dBm0  
30 dBm0  
20 dBm0  
10 dBm0  
3 dBm0  
25  
29  
34  
36  
36  
36  
Output connection: LX = 0 dBr  
f = 1014 Hz (C message weighted for µ-law,  
psophometrically weighted for A-law)  
STDX  
dB  
Receive signal to total distortion ratio  
45 dBm0  
40 dBm0  
30 dBm0  
20 dBm0  
10 dBm0  
3 dBm0  
25  
29  
34  
36  
36  
36  
Input connection: LR = 0 dBr  
f = 1014 Hz (C message weighted for µ-law,  
psophometrically weighted for A-law)  
STDR  
dB  
7.3.7  
NOISE  
Parameter  
NXC  
Description  
Min.  
Typ.  
Max.  
Units  
Test Conditions  
Transmit noise, C message weighted for µ-law  
18  
68  
12  
dBrnC0  
dBm0p  
dBrnC0  
dBm0  
NXP  
NRC  
NRP  
Transmit noise, psophometrically weighted for A-law  
Receive noise, C message weighted for µ-law  
Receive noise, psophometrically weighted for A-law  
78  
Power supply rejection, transmit  
f = 300 Hz to 3.4 kHz  
PSRX  
PSRR  
30  
25  
dB  
dB  
VDD = 3.3 VDC+100 mVrms  
f = 3.4 kHz to 20 kHz  
Power supply rejection, receive  
f = 300 Hz to 3.4 kHz  
VDD = 3.3 VDC+100 mVrms, PCM code is  
positive LSB one  
30  
25  
f = 3.4 kHz to 20 kHz  
97  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
7.3.8  
INTERCHANNEL CROSSTALK  
Description  
Parameter  
Min.  
Typ.  
Max.  
Units  
Test Conditions  
300 Hz to 3400 Hz, 0 dBm0 signal into VTAC of  
interfering channel. Idle PCM code into channel  
under test  
XTX-R  
XTR-X  
XTX-X  
XTR-R  
Transmit to receive crosstalk  
Receive to transmit crosstalk  
Transmit to transmit crosstalk  
Receive to receive crosstalk  
85  
78  
dB  
300 Hz to 3400 Hz, 0 dBm0 PCM code into inter-  
fering channel. VTAC = 0 Vrms for channel  
under test  
85  
85  
85  
80  
78  
80  
dB  
dB  
dB  
300 Hz to 3400 Hz, 0 dBm0 signal into VTAC of  
interfering channel. VTAC = 0 Vrms for channel  
under test  
300 Hz to 3400 Hz, 0 dBm0 PCM code into inter-  
fering channel. Idle PCM code into channel  
under test  
98  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
7.4  
CODEC TIMING CHARACTERISTICS  
7.4.1  
CLOCK TIMING  
Symbol  
Description  
CCLK period  
Min.  
122  
48  
Typ.  
Max.  
Units  
ns  
Test Conditions  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
100 k  
CCLK pulse width  
ns  
CCLK rise and fall time  
BCLK period  
25  
ns  
122  
48  
ns  
BCLK pulse width  
ns  
BCLK rise and fall time  
MCLK pulse width  
MCLK rise and fall time  
15  
15  
ns  
48  
90  
ns  
ns  
DCL period  
t9  
f = 2.048 kHz  
f = 4.096 kHz  
488  
244  
ns  
t10  
t11  
DCL rise and fall time  
DCL pulse width  
60  
ns  
ns  
t2  
t5  
t7  
t1  
t4  
CCLK  
BCLK  
MCLK  
t3  
t3  
t6  
t8  
t2  
t5  
t7  
t6  
t8  
t11  
t9  
DCL  
t10  
t10  
Figure - 43 Clock Timing  
99  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
7.4.2  
MICROPROCESSOR INTERFACE TIMING  
Symbol  
Description  
Min.  
Typ.  
Max.  
Units  
Test Conditions  
t12  
t13  
CS setup time  
15  
ns  
8 n t1  
(n 2)  
CS pulse width  
ns  
t14  
t15  
t16  
t17  
t18  
t19  
t20  
t21  
CS off time  
250  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Input data setup time  
Input data hold time  
SLIC output latch valid  
Output data turn on delay  
Output data hold time  
Output data turn off delay  
output data valid  
30  
1000  
50  
0
0
50  
50  
CCLK  
t12  
t14  
t13  
CS  
t15  
t16  
CI  
t17  
RSLIC  
Output  
Figure - 44 MPI Input Timing  
CCLK  
t13  
t14  
t12  
CS  
t21  
t19  
t18  
t20  
CO  
Figure - 45 MPI Output Timing  
100  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
7.4.3  
PCM INTERFACE TIMING  
Symbol  
Description  
Min.  
122  
48  
Typ.  
Max.  
Units  
ns  
Test Conditions  
BCLK period 1)  
t22  
t23  
t24  
t25  
t26  
t27  
t28  
t29  
t30  
t31  
t32  
t33  
BCLK high time  
ns  
FSC period  
125  
µs  
ns  
FSC setup time  
25  
50  
25  
5
t22 50  
FSC hold time  
ns  
DR1/DR2 setup time  
DR1/DR2 hold time  
DX1/DX2 output delay  
DX1/DX2 output hold time  
DX1/DX2 output delay to high-Z  
ns  
ns  
5
70  
70  
70  
80  
80  
ns  
5
ns  
5
ns  
Delay to TSX1/TSX2 valid 2)  
Delay to TSX1/TSX2 off 3)  
5
ns  
5
ns  
t23  
t22  
BCLK  
t24  
t25  
t26  
FSC  
t27  
t28  
DR1/DR2  
first bit  
t29  
t30  
t31  
High Z  
first bit  
DX1/DX2  
t33  
t32  
TSX1/TSX2  
Figure - 46 PCM Interface Timing (Single Clock Mode)  
101  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
t23  
t22  
BCLK  
t24  
t25  
t26  
FSC  
t27  
t28  
DR1/DR2  
first bit  
t29  
t31  
t30  
High Z  
first bit  
DX1/DX2  
t32  
t33  
TSX1/TSX2  
Figure - 47 PCM Interface Timing (Double Clock Mode)  
NOTES:  
1) The BCLK frequency must be an integer multiple of the FSC frequency. The maximum BCLK frequency is 8.192 MHz. The minimum BCLK frequency is 64 kHz in compressed mode  
and 128 kHz in linear mode if only one channel is used. The minimum BCLK frequency is 256 kHz in compressed mode and 512 kHz in linear mode if all four channels are used.  
2) TSX1 or TSX2 typically delays from the FSC for 8 N t22 ns in compressed mode and 16 N t22 ns in linear mode, where N is the specified time slot (value of TT[6:0] in register  
LREG1).  
3) t33 is defined to be the time when the TSX1 or TSX2 output achieves high level.  
4) Figure - 46 and Figure - 47 show the timing of transmit at the rising edges of BCLK and receive at the falling edges of it.  
102  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
7.4.4  
GCI INTERFACE TIMING  
Symbol  
Description  
FSC rise and fall time  
FSC setup time  
Min.  
Typ.  
Max.  
60  
Units  
ns  
Test Conditions  
t34  
t35  
t36  
t37  
t38  
t39  
t40  
70  
50  
t9 50  
ns  
FSC hold time  
ns  
FSC high pulse width  
DU data delay time  
DD data delay time  
DD data hold time  
130  
ns  
100  
ns  
110  
50  
ns  
ns  
DCL  
FSC  
B7  
B6  
B0  
DD/DU  
Detail A  
Detail A  
DCL  
2.048MHz  
t35  
t35  
t37  
FSC  
t37  
t38  
t36  
B7  
t40  
t38  
DU  
DD  
B6  
t39  
B6  
B7  
DCL  
t35  
4.096 MHZ  
t35  
t38  
t37  
FSC  
DU  
t37  
t38  
t36  
B7  
t39  
t40  
DD  
B7  
Figure - 48 GCI Interface Timing  
103  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
8
APPLICATION CIRCUITS  
8.1  
APPLICATION CIRCUIT FOR THE INTERNAL RINGING MODE  
The RSLIC-CODEC chipset can provide an internal ringing signal without any external components. The amplitude of the internal ringing signal  
can be up to 70 Vp. The off-hook detection and ring trip detection are also internally performed. Figure - 49 shows an application circuit for the internal  
ringing mode.  
AGND  
0.1µF  
10µF  
+3.3V  
+
+3.3VD  
0.1µF  
D1 (1 A/200 V)  
+3.3VA  
+3.3VA  
+
+
VBL  
0.1µF  
10µF  
D2 (1 A/200 V)  
0.1µF  
10µF  
0.1µF  
D3 (1 A/200 V)  
AGN  
D
VBH  
AGND  
VDDD VDDA  
AGND  
DGND  
1
28  
5
CINT  
D4  
1N4148  
VDDB  
MPI/GCI  
VBH  
VBL  
VDD  
14  
CA  
RPROT  
RS  
D5  
1N4148  
4
60  
61  
31  
TIS  
TIP  
17  
16  
13  
15  
RTIN1  
CB  
27  
32  
34  
33  
CSTAB  
BGND  
CSTAB  
VL  
VTAC  
VTDC  
VL1  
CS  
VTAC1  
VTDC1  
PROTECTION  
26  
2
62  
63  
RING  
RIS  
CCLK/S0  
CI/S1  
RPROT  
RS  
9
41  
40  
ACN1  
ACP1  
ACN  
ACP  
10  
25  
64  
67  
VCMB  
CO  
11  
12  
39  
38  
DCN  
DCP  
DCN1  
RESET  
IDT82V1671  
24  
23  
CA2  
RSP  
RSN  
CA2_1  
66  
77  
MCLK  
8
37  
36  
VCM  
CS  
CA1_1  
DCP1  
INT/INT  
CA1  
21  
IDT82V1074  
(Channel1)  
76  
75  
68  
69  
70  
72  
DCL/BCLK  
FSC  
22  
20  
19  
18  
RT  
M1  
M2  
M3  
50  
49  
48  
47  
IO1_1  
IO2_1  
IO3_1  
IO4_1  
TSX1  
DX1/DU  
DR1/DD  
TSX2  
AGND BGND CF  
6
3
7
52  
CS1  
73  
74  
CF  
DX2  
DR2  
54  
55  
56  
M1  
M2  
M3  
59  
AGND  
BGND  
RSYNC  
17  
15  
VCM  
CNF  
CNF  
0.1  
GNDA  
GNDD  
DGND  
AGND  
AGND  
Figure - 49 Application Circuit for the Internal Ringing Mode  
104  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
8.2  
APPLICATION CIRCUIT FOR THE EXTERNAL RINGING MODE  
The chipset also supports the external ringing mode. Figure - 50 shows an application circuit for the external ringing mode.  
AGND  
0.1µF  
10µF  
+3.3V  
+
D1 (1 A/200 V)  
+3.3VD  
0.1µF  
+3.3VA  
+3.3VA  
VBL  
+
+
0.1µF  
10µF  
D2 (1 A/200 V)  
0.1µF  
10µF  
0.1µF  
AGND  
VDDD VDDA  
RTIN1  
D3 (1 A/200 V)  
1
AGN  
D
VBH  
AGND  
VDDB  
MPI/GCI  
DGND  
28  
5
CINT  
D4  
1N4148  
14  
17  
VBH  
VBL  
VDD  
CA  
RPROT  
D5  
1N4148  
RS  
4
31  
60  
TIS  
TIP  
CB  
27  
16  
13  
15  
32  
34  
33  
61  
CSTAB  
VL  
VTAC  
VTDC  
VL1  
CS  
PROTECTION  
VTAC1  
VTDC1  
BGND  
CSTAB  
Relay  
26  
2
62  
63  
RING  
RIS  
CCLK/S0  
CI/S1  
RPROT  
RS  
9
41  
40  
ACN1  
ACP1  
ACN  
ACP  
10  
64  
67  
25  
CO  
VCMB  
11  
12  
39  
38  
DCN  
DCP  
DCN1  
RESET  
IDT82V1671  
+5V  
CA2  
CA1  
C1  
R1  
CA2_1  
66  
77  
D6  
MCLK  
IN4148  
8
23  
24  
37  
36  
VCM  
CS  
RSN  
RSP  
CA1_1  
DCP1  
INT/INT  
D7  
IN4148  
21  
IDT82V1074  
(Channel1)  
76  
75  
68  
69  
70  
72  
DCL/BCLK  
FSC  
C2  
20  
19  
18  
R3  
M1  
M2  
M3  
50  
49  
48  
47  
R2  
IO1_1  
IO2_1  
IO3_1  
IO4_1  
22  
TSX1  
RT  
R4  
R5  
DX1/DU  
DR1/DD  
TSX2  
Ring  
AGND BGND CF  
Generator  
-48V DC  
80Vrms  
6
3
7
52  
CS1  
73  
74  
CF  
DX2  
DR2  
54  
55  
56  
R7  
R8  
M1  
M2  
M3  
R6  
BGND  
AGND  
17  
59  
15  
VCM  
RSYNC  
CNF  
GNDA  
AGND  
GNDD  
DGND  
CNF  
AGND  
Figure - 50 Application Circuit for the External Ringing Mode  
Table - 28 External Components in Application Circuits  
Symbol  
RPROT  
RS  
Value  
Unit  
Tolerance  
Rating  
50  
50  
1 W  
1 W  
±5%  
±1%  
R1, R2  
R3, R6  
100  
150  
10  
kΩ  
±10%  
±10%  
±10%  
±10%  
±10%  
±10%  
±10%  
±10%  
±10%  
±10%  
1 W  
R4, R5, R7, R8  
CSTAB  
ΜΩ  
nF  
22  
100 V  
50 V  
CINT  
0.47  
0.047  
0.047  
0.47  
0.1  
µF  
µF  
µF  
µF  
µF  
µF  
CA1  
CA2  
CF  
50 V  
CNF  
C1, C2  
1
105  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
9
ORDERING INFORMATION  
RSLIC (IDT82V1671):  
IDT  
XXXXXXX  
X
X
Process/  
Temperature  
Range  
Dev ice Ty pe  
Package  
Blank  
Industrial (-40 °C to +85 °C)  
J
Plastic Leaded Chip Carrier (PLCC, PL28)  
82V1671 Ringing SLIC  
CODEC (IDT82V1074):  
IDT  
XXXXXXX  
Dev ice Ty pe  
XX  
X
Process/  
Temperature  
Range  
Package  
Blank  
PF  
Industrial (-40 °C to +85 °C)  
Thin Quad Flat Pack (TQFP, PK100)  
82V1074 Quad Programmable PCM CODEC  
106  
RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET  
INDUSTRIAL TEMPERATURE RANGE  
Data Sheet Document History  
11/05/2002  
01/09/2003  
02/28/2003  
04/22/2003  
11/18/2003  
02/16/2004  
pgs. 1, 17, 36, 44 - 48, 60, 63, 77 - 78, 83 - 85, 88, 94, 103, 104  
pgs. 1, 105  
pgs. 29, 66, 93, 103, 104  
pgs. 73, 93, 94  
pgs. 1, 19, 21, 29, 61, 63, 75  
pgs. 18, 19, 21, 26, 29, 60, 61, 63, 73, 75, 77, 83-85, 93, 94  
CORPORATE HEADQUARTERS  
2975 Stender Way  
for SALES:  
800-345-7015 or 408-727-6116  
for Tech Support:  
email: telecomhelp@idt.com  
Santa Clara, CA 95054  
fax: 408-492-8674  
www.idt.com  
phone: 408-330-1552  
107  

相关型号:

IDT82V1671

CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT (RSLIC) & QUAD PROGRAMMABLE PCM CODEC
IDT

IDT82V1671J

CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT (RSLIC) & QUAD PROGRAMMABLE PCM CODEC
IDT

IDT82V1671J8

SLIC, 2-4 Conversion, Hybrid, PQCC28
IDT

IDT82V2041E

SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
IDT

IDT82V2041EPP

SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
IDT

IDT82V2041EPP8

PCM Transceiver, 1-Func, PQFP44, TQFP-44
IDT

IDT82V2041EPPG

SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
IDT

IDT82V2041EPPG8

PCM Transceiver, 1-Func, PQFP44, GREEN, TQFP-44
IDT

IDT82V2044

QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
IDT

IDT82V2044BB

QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
IDT

IDT82V2044BBG

QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
IDT

IDT82V2044DA

QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
IDT